2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
HUF75945G3, HUF75945P3, HUF75945S3ST
38A, 200V, 0.071 Ohm, N-Channel,
UltraFET Power MOSFETs
Packaging
Symbol
Features
Ultra Low On-Resistance
- r
DS(ON)
= 0.071
,
V
GS
=
10V
Simulation Models
- Temperature Compensated PSPICE and SABERTM
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
Peak Current vs Pulse Width Curve
UIS Rating Curve
JEDEC TO-247
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(TAB)
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
GATE
SOURCE
DRAIN
(FLANGE)
D
G
S
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75945G3
TO-247
75945G
HUF75945P3
TO-220AB
75945P
HUF75945S3ST
TO-263AB
75945S
NOTE: When ordering, use the entire part number.
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
HUF75945G3,HUF75945P3,
HUF75945S3ST
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
200
V
Drain to Gate Voltage (R
GS
= 20k
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
200
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
20
V
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
38
27
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310
2.07
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
NOTES:
1. T
J
= 25
o
C to 150
o
C.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet
December 2001
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V (Figure 11)
200
-
-
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 190V, V
GS
= 0V
-
-
1
A
V
DS
= 180V, V
GS
= 0V, T
C
= 150
o
C
-
-
250
A
Gate to Source Leakage Current
I
GSS
V
GS
=
20V
-
-
100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A (Figure 10)
2
-
4
V
Drain to Source On Resistance
r
DS(ON)
I
D
= 38A, V
GS
= 10V (Figure 9)
-
0.056
0.071
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
R
JC
TO-247, TO-220, TO-263
-
-
0.48
o
C/W
Thermal Resistance Junction to
Ambient
R
JA
TO-247
-
-
30
o
C/W
TO-220, TO-263
-
-
62
o
C/W
SWITCHING SPECIFICATIONS (V
GS
= 10V)
Turn-On Time
t
ON
V
DD
= 100V, I
D
= 38A
V
GS
=
10V,
R
GS
= 3.0
(Figures 18, 19)
-
-
33
ns
Turn-On Delay Time
t
d(ON)
-
15
-
ns
Rise Time
t
r
-
64
-
ns
Turn-Off Delay Time
t
d(OFF)
-
65
-
ns
Fall Time
t
f
-
80 -
ns
Turn-Off Time
t
OFF
-
-
217
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 20V
V
DD
= 100V,
I
D
= 38A,
I
g(REF)
= 1.0mA
(Figures 13, 16, 17)
-
215
280
nC
Gate Charge at 10V
Q
g(10)
V
GS
= 0V to 10V
-
118
153
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 2V
-
8
10
nC
Gate to Source Gate Charge
Q
gs
-
15
-
nC
Gate to Drain "Miller" Charge
Q
gd
-
42
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz (Figure 12)
-
4023
-
pF
Output Capacitance
C
OSS
-
880
-
pF
Reverse Transfer Capacitance
C
RSS
-
240
-
pF
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 38A
-
-
1.25
V
I
SD
= 19A
-
-
1.00
V
Reverse Recovery Time
t
rr
I
SD
= 38A, dI
SD
/dt = 100A/
s
-
-
281
ns
Reverse Recovered Charge
Q
RR
I
SD
= 38A, dI
SD
/dt = 100A/
s
-
-
2700
nC
HUF75945G3, HUF75945P3, HUF75945S3ST
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
T
C
, CASE TEMPERATURE (
o
C)
P
O
W
E
R DI
S
S
IP
A
T
ION
MUL
T
IP
L
I
E
R
0
0
25
50
75
100
175
0.2
0.4
0.6
0.8
1.0
1.2
125
150
0
10
20
30
40
25
50
75
100
125
150
175
I
D
,
DRAIN CUR
RE
NT
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
V
GS
= 10V
0.1
1
2
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
10
-5
t, RECTANGULAR PULSE DURATION (s)
Z
JC
, NO
RM
AL
IZ
ED
T
H
ERM
A
L
IM
PED
ANCE
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
100
1000
10
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-5
I
DM
, P
E
AK CURRENT
(
A
)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
HUF75945G3, HUF75945P3, HUF75945S3ST
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
Typical Performance Curves
(Continued)
1
10
100
1
10
100
500
500
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT
(
A
)
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
100
s
10ms
1ms
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
1
10
100
0.001
0.01
0.1
1
200
10
I
AS
, A
V
AL
ANCHE CURRENT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
25
50
75
2
3
4
5
I
D,
DRAIN CURRENT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
0
25
50
75
0
1
2
3
4
5
6
I
D
,
DRAIN CURRENT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 4.5V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 10V
V
GS
= 5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-80
-40
0
40
80
120
200
NORM
AL
IZ
ED D
RAIN T
O
SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RE
SI
S
T
ANCE
V
GS
= 10V, I
D
= 38A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
160
0.4
0.6
0.8
1.0
1.2
-80
-40
0
40
80
120
160
200
N
O
RMAL
IZ
E
D
GA
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
A
T
HRES
H
O
L
D V
O
L
T
A
GE
HUF75945G3, HUF75945P3, HUF75945S3ST
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves
(Continued)
0.9
1.0
1.1
1.2
1.3
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
ED DRAIN T
O
SOURCE
BREAKDO
WN V
O
L
T
A
G
E
I
D
= 250
A
100
1000
10000
0.1
1.0
10
100 200
30
C, CAP
A
C
IT
ANCE (
p
F
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
RSS
=
C
GD
C
OSS
C
DS
+ C
GD
0
2
4
6
8
10
0
20
40
60
80
100
120
V
GS
, G
A
T
E
T
O
SOURCE V
O
L
T
A
G
E
(
V
)
V
DD
= 100V
Q
g
, GATE CHARGE (nC)
I
D
= 38A
I
D
= 10A
WAVEFORMS IN
DESCENDING ORDER:
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
HUF75945G3, HUF75945P3, HUF75945S3ST
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms
(Continued)
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
V
GS
= 10V
Q
g(TOT)
V
GS
= 20V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
HUF75945G3, HUF75945P3, HUF75945S3ST
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
PSPICE Electrical Model
.SUBCKT HUF75945 2 1 3 ;
rev 13 October 2000
CA 12 8 6.6e-9
CB 15 14 6.5e-9
CIN 6 8 3.80e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 221
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 8.05e-9
LSOURCE 3 7 5.8e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.0e-2
RGATE 9 20 0.77
RLDRAIN 2 5 10
RLGATE 1 9 80.5
RLSOURCE 3 7 58
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.8e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),2.5))}
.MODEL DBODYMOD D (IS = 2.8e-12 RS = 3.0e-3 XTI = 5.5 TRS1 = 3.5e-3 TRS2 = 1e-5 CJO = 2.55e-9 TT = 1.52e-7 M = 0.42)
.MODEL DBREAKMOD D (RS = 1.2e- 0TRS1 = 1e- 3TRS2 = 1e-6)
.MODEL DPLCAPMOD D (CJO = 4.6e- 9IS = 1e-30 N = 10 M = 0.9)
.MODEL MMEDMOD NMOS (VTO = 3.05 KP = 2.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.77)
.MODEL MSTROMOD NMOS (VTO = 3.55 KP = 100 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.69 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.70 )
.MODEL RBREAKMOD RES (TC1 =1.27e- 3TC2 = 1.0e-6)
.MODEL RDRAINMOD RES (TC1 = 9.90e-3 TC2 = 3.60e-5)
.MODEL RSLCMOD RES (TC1 = 3.0e-3 TC2 = 1.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.90e-3 TC2 = -1.10e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.80e- 3TC2 = 1.70e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -4.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF= -5.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.4)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.4 VOFF= -0.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUF75945G3, HUF75945P3, HUF75945S3ST
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
SABER Electrical Model
REV 13 October 2000
template huf75945 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.8e-12, rs = 3.0e-3, xti = 5.5, trs1 = 3.5e-3, trs2 = 1.0e-5, cjo = 2.55e-9, tt = 1.52e-7, m = 0.42)
dp..model dbreakmod = (rs = 1.2, trs1 = 1.0e-3, trs2 = 1.0e-6)
dp..model dplcapmod = (cjo = 4.6e-9, isl = 10e-30, nl=10, m = 0.9)
m..model mmedmod = (type=_n, vto = 3.05, kp = 2.5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.55, kp = 100, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.69, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -4.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4.5, voff = -5.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.4)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.3)
c.ca n12 n8 = 6.6e-9
c.cb n15 n14 = 6.5e-9
c.cin n6 n8 = 3.8e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 8.05e-9
l.lsource n3 n7 = 5.80e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.27e-3, tc2 = 1.00e-6
res.rdrain n50 n16 = 5.0e-2, tc1 = 9.9e-3, tc2 =3.6e-5
res.rgate n9 n20 = 0.77
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 80.5
res.rlsource n3 n7 = 58
res.rslc1 n5 n51= 1e-6, tc1 = 3e-3, tc2 = -1.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.8e-3, tc1 = 1.0e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.70e-6
res.rvthres n22 n8 = 1, tc1 = -2.9e-3, tc2 = 1.1e-5
spe.ebreak n11 n7 n17 n18 = 221
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*100))** 2.5))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUF75945G3, HUF75945P3, HUF75945S3ST
2001 Fairchild Semiconductor Corporation
HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
SPICE Thermal Model
REV 13 October 2000
HUF75945T
CTHERM1 th 6 6.45e-3
CTHERM2 6 5 3.00e-2
CTHERM3 5 4 1.40e-2
CTHERM4 4 3 1.65e-2
CTHERM5 3 2 4.85e-2
CTHERM6 2 tl 1.00e-1
RTHERM1 th 6 3.24e-3
RTHERM2 6 5 8.08e-3
RTHERM3 5 4 2.28e-2
RTHERM4 4 3 1.00e-1
RTHERM5 3 2 1.10e-1
RTHERM6 2 tl 1.40e-1
SABER Thermal Model
SABER thermal model HUF75945T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.45e-3
ctherm.ctherm2 6 5 = 3.00e-2
ctherm.ctherm3 5 4 = 1.40e-2
ctherm.ctherm4 4 3 = 1.65e-2
ctherm.ctherm5 3 2 = 4.85e-2
ctherm.ctherm6 2 tl = 1.00e-1
rtherm.rtherm1 th 6 = 3.24e-3
rtherm.rtherm2 6 5 = 8.08e-3
rtherm.rtherm3 5 4 = 2.28e-2
rtherm.rtherm4 4 3 = 1.00e-1
rtherm.rtherm5 3 2 = 1.10e-1
rtherm.rtherm6 2 tl = 1.40e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
HUF75945G3, HUF75945P3, HUF75945S3ST
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Definition
Advance Information
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Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
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changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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