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Электронный компонент: HUF76129D3

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2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
HUF76129D3, HUF76129D3S
20A, 30V, 0.016 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFETTM process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76129.
Features
Logic Level Gate Drive
20A, 30V
Ultra Low On-Resistance, r
DS(ON)
= 0.016
Temperature Compensating PSPICE
Model
Temperature Compensating SABER
Mode
Thermal Impedance SPICE Model
Thermal Impedance SABER Model
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
- TB334, "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76129D3
TO-251AA
76129D
HUF76129D3S
TO-252AA
76129D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76129D3ST.
D
G
S
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
Data Sheet
January 2003
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
30
V
Drain to Gate Voltage (R
GS
= 20k
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
20
V
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Continuous (T
C
= 100
o
C, V
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Continuous (T
C
= 100
o
C, V
GS
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
20
20
20
Figure 4
A
A
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
.83
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
TA = 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V (Figure 12)
30
-
-
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 25V, V
GS
= 0V
-
-
1
A
V
DS
= 25V, V
GS
= 0V, T
C
= 150
o
C
-
-
250
A
Gate to Source Leakage Current
I
GSS
V
GS
=
20V
-
-
100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A (Figure 11)
1
-
3
V
Drain to Source On Resistance
r
DS(ON)
I
D
= 20A, V
GS
= 10V (Figure 9, 10)
-
0.014
0.016
I
D
= 20A, V
GS
= 5V (Figure 9)
-
0.0175
0.021
I
D
= 20A, V
GS
= 4.5V (Figure 9)
-
0.0195
0.023
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
R
JC
(Figure 3)
-
-
1.20
o
C/W
Thermal Resistance Junction to Ambient
R
JA
TO-251, TO-252
-
-
100
o
C/W
SWITCHING SPECIFICATIONS (V
GS
= 4.5V)
Turn-On Time
t
ON
V
DD
= 15V, I
D
20A, R
L
= 0.75
,
V
GS
=
4.5V, R
GS
= 10
(Figures 15, 21, 22)
-
-
275
ns
Turn-On Delay Time
t
d(ON)
-
20
-
ns
Rise Time
t
r
-
165
-
ns
Turn-Off Delay Time
t
d(OFF)
-
30
-
ns
Fall Time
t
f
-
54
-
ns
Turn-Off Time
t
OFF
-
-
125
ns
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
SWITCHING SPECIFICATIONS (V
GS
= 10V)
Turn-On Time
t
ON
V
DD
= 15V, I
D
20A, R
L
= 0.75
,
V
GS
=
10V, R
GS
= 10
(Figures 16, 21, 22)
-
-
80
ns
Turn-On Delay Time
t
d(ON)
-
7
-
ns
Rise Time
t
r
-
47
-
ns
Turn-Off Delay Time
t
d(OFF)
-
60
-
ns
Fall Time
t
f
-
54
-
ns
Turn-Off Time
t
OFF
-
-
110
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 10V
V
DD
= 15V, I
D
20A,
R
L
= 0.75
I
g(REF)
= 1.0mA
(Figures 14, 19, 20)
-
38
46
nC
Gate Charge at 5V
Q
g(5)
V
GS
= 0V to 5V
-
22
26
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 1V
-
1.4
1.7
nC
Gate to Source Gate Charge
Q
gs
-
3.70
-
nC
Gate to Drain "Miller" Chatge
Q
gd
-
11.20
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 13)
-
1425
-
pF
Output Capacitance
C
OSS
-
720
-
pF
Reverse Transfer Capacitance
C
RSS
-
170
-
pF
Electrical Specifications
TA = 25
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 20A
-
-
1.25
V
Reverse Recovery Time
t
rr
I
SD
= 20A, dI
SD
/dt = 100A/
s
-
-
72
ns
Reverse Recovered Charge
Q
RR
I
SD
= 20A, dI
SD
/dt = 100A/
s
-
-
107
nC
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
T
A
, AMBIENT TEMPERATURE (
o
C)
P
O
W
E
R DIS
S
IP
A
T
IO
N M
U
L
T
IP
L
I
E
R
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
10
0
25
50
75
100
125
I
D
, DRAIN CURRE
NT
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
25
150
5
20
V
GS
=4.5V
V
GS
=10V
15
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
Typical Performance Curves
(Continued)
t , RECTANGULAR PULSE DURATION (s)
10
-5
10
-1
10
0
2
0.1
1
10
-2
Z
JC
, NO
RM
AL
IZ
E
D
T
H
E
R
M
A
L
IM
P
E
D
ANCE
0.01
10
-4
10
-3
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
10
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
T
C
= 25
o
C
I
=
I
25
150 - T
C
125
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I
DM
, P
E
AK CURRE
NT
(
A
)
2000
10
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t, PULSE WIDTH (s)
100
V
GS
= 5V
T
J
= MAX RATED
T
C
= 25
o
C
100
s
10ms
1ms
BV
DSS
MAX
= 30V
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
100
1
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
100
1000
10
I
D
,
DRAIN CURRE
NT
(
A
)
10
1
10
100
500
1
I
AS
, A
V
AL
A
NCHE
CURRE
NT

(
A
)
t
AV
, TIME IN AVALANCHE (ms)
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
0.1
10
0.01
100
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves
(Continued)
0
2
3
1
0
15
30
45
V
GS
, GATE TO SOURCE VOLTAGE (V)
150
o
C
-55
o
C
25
o
C
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
60
4
I
D
, DRAIN CURRE
NT
(
A
)
V
GS
= 4V
V
GS
= 3.5V
0
15
30
0
1
2
3
4
5
45
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 5V
V
GS
= 10V
V
GS
= 4.5V
60
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 3V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
18
21
24
30
12
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
2
6
10
8
I
D
= 20A
I
D
= 10A
I
D
= 5A
r
DS
(O
N)
, DRAIN T
O
S
O
URCE
O
N
RE
S
I
S
T
ANC
E
(
m
)
15
27
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.2
1.6
-80
0
40
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANCE
160
1.4
-40
80
120
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 20A
0.6
0.7
1.0
1.2
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
T
HRE
S
H
O
L
D V
O
L
T
A
G
E
V
GS
= V
DS
, I
D
= 250
A
0.9
0.8
1.1
-80
0
40
160
-40
80
120
1.15
1.05
1.00
0.95
0.90
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D

DRAIN T
O
S
O
URCE
BRE
AKDO
W
N
V
O
L
T
A
G
E
I
D
= 250
A
1.10
-80
0
40
160
-40
80
120
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes 7254 and 7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
(Continued)
2000
1200
0
0
10
15
20
C, CAP
A
C
IT
ANCE
(
p
F
) 1600
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
800
C
ISS
C
OSS
C
RSS
30
400
5
25
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
10
8
6
4
0
V
GS
, G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
V
DD
= 15V
2
30
0
Q
g
, GATE CHARGE (nC)
10
I
D
= 20A
I
D
= 10A
I
D
= 2A
WAVEFORMS IN
DESCENDING ORDER:
20
40
200
20
30
40
50
0
500
400
300
0
10
S
W
IT
CHING
T
I
M
E
(
n
s
)
R
GS
, GATE TO SOURCE RESISTANCE (
)
100
t
d(OFF)
t
d(ON)
t
r
t
f
V
GS
= 4.5V, V
DD
= 15V, I
D
= 20A, R
L
= 0.75
100
20
30
40
50
0
300
200
150
0
10
S
W
I
T
CHING
T
I
M
E
(
n
s
)
R
GS
, GATE TO SOURCE RESISTANCE (
)
t
d(OFF)
t
d(ON)
t
r
t
f
V
GS
= 10V, V
DD
= 15V, I
D
= 20A, R
L
= 0.75
50
250
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms
(Continued)
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10
V
DS
V
GS
I
g(REF)
0
0
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
PSPICE Electrical Model
SUBCKT HUF76129D 2 1 3 ;
REV April 1998
CA 12 8 1.95e-9
CB 15 14 1.85e-9
CIN 6 8 1.31e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 32
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 2.20e-9
LSOURCE 3 7 3.03e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.9e-3
RGATE 9 20 3.5
RLDRAIN 2 5 10
RLGATE 1 9 22
RLSOURCE 3 7 30.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*1000),3.5))}
.MODEL DBODYMOD D (IS = 1.2e-12 IKF = 8 TIKF = 1e-2 RS = 7.7e-3 TRS1 = 3e-4 TRS2 = 1e-6 CJO = 2.23e-9 TT = 35e-9 M = 4e-1 XTI =4.75 )
.MODEL DBREAKMOD D (RS = 9.5e-2 TRS1 = 4e-3 TRS2 = 3e-5 IKF = 1e-1)
.MODEL DPLCAPMOD D (CJO = 1.12e-10 IS = 1e-30 N = 10 M = 6.5e-1 VJ = 1.45)
.MODEL MMEDMOD NMOS (VTO = 1.87 KP = 5.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1)
.MODEL MSTROMOD NMOS (VTO = 2.15 KP = 90 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.49 KP =2e-2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10)
.MODEL RBREAKMOD RES (TC1 = 9.8e-4 TC2 = -1e-10)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-6 TC2 = 1.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 2.5e-3 TC2 = 2e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -1.1e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.65e-3 TC2 = 1.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -10.0 VOFF= -0.50)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= -10.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 0.50)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.50 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
SABER Electrical Model
nom temp=25 deg c 30v LL Ultrafet
REV April 1998
template huf76129D n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.2e-12, xti=4.75, cjo=2.23e-9,tt=35e-8, m=4e-1)
d..model dbreakmod = (is=1e-14)
d..model dplcapmod = (cjo=1.12e-9,is=1e-30,n=10,m=6.5e-1, vj=1.45, fc=5e-1)
m..model mmedmod = (type=_n,vto=1.87,kp=5.75,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.15,kp=90,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.49,kp=2e-2,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-10.0,voff=-0.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=10.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=0,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=0)
c.ca n12 n8 = 1.95e-9
c.cb n15 n14 = 1.85e-9
c.cin n6 n8 = 1.31e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.2e-9
l.lsource n3 n7 = 3.03e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9.8e-4,tc2=-1e-10
res.rdbody n71 n5 =7.7e-3, tc1=2.5e-3, tc2=1e-6
res.rdbreak n72 n5 =9.5e-2, tc1=4e-3, tc2=3e-5
res.rdrain n50 n16 = 1.9e-3, tc1=1e-2,tc2=1e-5
res.rgate n9 n20 = 3.6e-1
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 22
res.rlsource n3 n7 = 30.3
res.rslc1 n5 n51 = 1e-6, tc1=1e-6,tc2=-1.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1=2.5e-3,tc2=2e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1.1e-5
res.rvthres n22 n8 = 1, tc1=-1.65e-3,tc2=-1.45e-6
spe.ebreak n11 n7 n17 n18 = 37
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/1000))** 3.5 ))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76129D3, HUF76129D3S
background image
2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
SPICE Thermal Model
REV April 1998
HUF76129D
CTHERM1 th 6 1.10e-5
CTHERM2 6 5 2.70e-2
CTHERM3 5 4 3.90e-2
CTHERM4 4 3 1.00e-2
CTHERM5 3 2 2.30e-2
CTHERM6 2 tl 1.80
RTHERM1 th 6 1.00e-4
RTHERM2 6 5 5.00e-4
RTHERM3 5 4 2.90e-2
RTHERM4 4 3 4.80e-1
RTHERM5 3 2 2.80e-1
RTHERM6 2 tl 1.00e-1
SABER Thermal Model
Saber thermal model HUF76129D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 = 1.10e-5
ctherm.ctherm2 c2 c3 = 2.70e-2
ctherm.ctherm3 c3 c4 = 3.90e-2
ctherm.ctherm4 c4 c5 = 1.00e-2
ctherm.ctherm5 c5 c6 = 2.30e-2
ctherm.ctherm6 c6 tl = 1.80
rtherm.rtherm1 th c2 = 1.00e-4
rtherm.rtherm2 c2 c3 = 5.00e-4
rtherm.rtherm3 c3 c4 = 2.90e-2
rtherm.rtherm4 c4 c5 = 4.80e-1
rtherm.rtherm5 c5 c6 = 2.80e-1
rtherm.rtherm6 c6 tl = 1.00e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
HUF76129D3, HUF76129D3S
background image
Rev. I2
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PRODUCT STATUS DEFINITIONS
Definition of Terms
ACExTM
ActiveArrayTM
BottomlessTM
CoolFETTM
CROSSVOLTTM
DOMETM
EcoSPARKTM
E
2
CMOSTM
EnSignaTM
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