2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
75A, 30V, 0.011 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFETTM process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76132.
Features
Logic Level Gate Drive
75A, 30V
Ultra Low On-Resistance, r
DS(ON)
= 0.011
Temperature Compensating PSPICE
Model
Temperature Compensating SABER
Model
Thermal Impedance SPICE Model
Thermal Impedance SABER Model
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
- TB334, "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76132P3
TO-220AB
76132P
HUF76132S3S
TO-263AB
76132S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76132S3ST.
D
G
S
JEDEC TO-220AB
JEDEC TO-263AB
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data Sheet
January 2003
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
30
V
Drain to Gate Voltage (R
GS
= 20k
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
20
V
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Continuous (T
C
= 100
o
C, V
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Continuous (T
C
= 100
o
C, V
GS
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
75
44
41
Figure 4
A
A
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
0.97
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-40 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V (Figure 12)
30
-
-
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 25V, V
GS
= 0V
-
-
1
A
V
DS
= 25V, V
GS
= 0V, T
C
= 150
o
C
-
-
250
A
Gate to Source Leakage Current
I
GSS
V
GS
=
20V
-
-
100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A (Figure 11)
1
-
3
V
Drain to Source On Resistance
r
DS(ON)
I
D
= 75A, V
GS
= 10V (Figure 9, 10)
-
0.0085
0.011
I
D
= 44A, V
GS
= 5V (Figure 9)
-
0.013
0.016
I
D
= 41A, V
GS
= 4.5V (Figure 9)
-
0.015
0.018
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
R
JC
(Figure 3)
-
-
1.03
o
C/W
Thermal Resistance Junction to Ambient
R
JA
TO-220, TO-262 and TO-263
-
-
62
o
C/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
t
ON
V
DD
= 15V, I
D
41A,
R
L
= 0.366
, V
GS
=
4.5V,
R
GS
= 6.2
(Figures 15, 21, 22)
-
-
185
ns
Turn-On Delay Time
t
d(ON)
-
17
-
ns
Rise Time
t
r
-
105
-
ns
Turn-Off Delay Time
t
d(OFF)
-
33
-
ns
Fall Time
t
f
-
42
-
ns
Turn-Off Time
t
OFF
-
-
113
ns
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
t
ON
V
DD
= 15V, I
D
75A,
R
L
= 0.20, V
GS
=
10V,
R
GS
= 6.8
(Figures 16, 21, 22)
-
-
72
ns
Turn-On Delay Time
t
d(ON)
-
11
-
ns
Rise Time
t
r
-
37
-
ns
Turn-Off Delay Time
t
d(OFF)
-
65
-
ns
Fall Time
t
f
-
42
-
ns
Turn-Off Time
t
OFF
-
-
160
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 10V
V
DD
= 15V, I
D
44A,
R
L
= 0.341
I
g(REF)
= 1.0mA
(Figures 14, 19, 20)
-
44
52
nC
Gate Charge at 5V
Q
g(5)
V
GS
= 0V to 5V
-
25
30
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 1V
-
1.8
2.2
nC
Gate to Source Gate Charge
Q
gs
-
4.80
-
nC
Gate to Drain "Miller" Charge
Q
gd
-
13.50
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 13)
-
1650
-
pF
Output Capacitance
C
OSS
-
850
-
pF
Reverse Transfer Capacitance
C
RSS
-
200
-
pF
Electrical Specifications
T
A
= 25
o
C, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 44A
-
-
1.25
V
Reverse Recovery Time
t
rr
I
SD
= 44A, dI
SD
/dt = 100A/
s
-
-
71
ns
Reverse Recovered Charge
Q
RR
I
SD
= 44A, dI
SD
/dt = 100A/
s
-
-
104
nC
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
T
A
, AMBIENT TEMPERATURE (
o
C)
P
O
W
E
R DIS
S
IP
A
T
IO
N
M
U
L
T
I
P
L
I
E
R
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
20
0
25
50
75
100
125
150
I
D
,
DRAIN CURRE
NT
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
80
40
60
V
GS
= 10V
V
GS
= 4.5V
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
Typical Performance Curves
Unless Otherwise Specified (Continued)
t, RECTANGULAR PULSE DURATION (s)
10
-5
10
-1
10
0
2
0.1
1
10
-2
Z
JC
, NO
RM
AL
IZ
E
D
T
H
ER
M
A
L
I
M
PE
D
A
N
C
E
0.01
10
-4
10
-3
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
10
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
T
C
= 25
o
C
I
=
I
25
150 - T
C
125
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
I
DM
, P
E
AK CURRE
NT
(
A
)
2000
50
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t, PULSE WIDTH (s)
100
V
GS
= 5V
1000
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
1
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
100
1000
10
I
D
, DRAIN
CURRE
NT
(
A
)
10
10ms
T
J
= MAX RATED
T
C
= 25
o
C
1ms
100
s
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
BV
DSS
MAX
= 30V
1
10
100
0.01
500
10
I
AS
, A
V
AL
ANC
HE
CURRE
NT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
0.1
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
0
2
3
4
5
1
0
20
60
100
I
D,
DR
AIN CURRE
NT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
150
o
C
-40
o
C
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
120
80
25
o
C
40
V
GS
= 4.5V
V
GS
= 4V
0
1
2
3
4
0
20
40
80
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 5V
V
GS
= 10V
V
GS
= 3V
120
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 3.5V
100
60
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
10
12
14
18
6
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
2
6
10
8
I
D
= 75A
I
D
= 25A
r
DS
(O
N)
, DRAIN T
O
S
O
UR
CE
O
N
RE
S
I
S
T
ANCE
(
m
)
8
16
I
D
= 51A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.4
-60
0
60
120
180
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANCE
1.2
1.6 PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 75A
-60
0
60
120
180
0.6
0.8
1.2
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
T
HRE
S
H
O
L
D V
O
L
T
A
G
E
V
GS
= V
DS
, I
D
= 250
A
1.0
1.2
1.1
1.0
0.9
-60
0
60
120
180
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
BRE
AKDO
W
N
V
O
L
T
A
G
E
I
D
= 250
A
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
C
OSS
2500
1500
0
0
5
15
25
C, CAP
A
C
IT
ANCE
(
p
F
)
2000
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1000
30
500
C
ISS
C
RSS
10
20
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
10
8
6
4
0
V
GS
, G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
V
DD
= 15V
2
30
50
0
Q
g
, GATE CHARGE (nC)
10
I
D
= 75A
I
D
= 51A
I
D
= 25A
WAVEFORMS IN
DESCENDING ORDER:
20
40
100
20
30
40
50
0
400
300
200
0
10
S
W
IT
CHING
T
I
M
E
(
n
s
)
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 4.5V, V
DD
= 15V, I
D
= 41A, R
L
= 0.312
t
d(OFF)
t
d(ON)
t
r
t
f
20
30
40
50
0
400
200
100
0
10
S
W
IT
CHING
T
I
M
E
(
n
s
)
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 10V, V
DD
= 15V, I
D
= 75A, R
L
= 0.20
300
t
r
t
f
t
d(OFF)
t
d(ON)
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms
(Continued)
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10
V
DS
V
GS
I
g(REF)
0
0
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
PSPICE Electrical Model
SUBCKT HUF76132 2 1 3 ;
REV May 1998
CA 12 8 2.35e-9
CB 15 14 2.35e-9
CIN 6 8 1.45e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 33.34
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.42e-9
LSOURCE 3 7 4.16e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.5e-4
RGATE 9 20 2.61
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 41.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*450),3))}
.MODEL DBODYMOD D (IS = 1.79e-12 IKF = 20 RS = 5.32e-3 TRS1 = 7e-4 TRS2 = 1.21e-6 CJO = 2.65e-9 TT = 3.24e-8 M = 4.2e-1 XTI=6)
.MODEL DBREAKMOD D (RS = 8.25e-2 TRS1 = 9.12e-4 TRS2 = 8.14e-7)
.MODEL DPLCAPMOD D (CJO = 1.3e-9 IS = 1e-30 N = 10 M = 6.1e-1)
.MODEL MMEDMOD NMOS (VTO = 1.86 KP = 4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.61)
.MODEL MSTROMOD NMOS (VTO = 2.2 KP = 120 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.63 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.1 RS=1e-1)
.MODEL RBREAKMOD RES (TC1 = 9.97e-4 TC2 = 1.24e-7)
.MODEL RDRAINMOD RES (TC1 = 7.2e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1.07e-3 TC2 = 1.25e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-11 TC2 = 1e-11)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -9.2e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.08e-3 TC2 = 9.73e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.00 VOFF= -1.00)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.00 VOFF= -6.00)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 1.65)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.65 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
SABER Electrical Model
nom temp=25 deg c 30v LL Ultrafet
REV May 1998
template huf76132 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.79e-12,cjo=2.65e-9,tt=3.24e-8, m=4.2e-1, xti=6)
d..model dbreakmod = ()
d..model dplcapmod = (cjo=1.3e-9,is=1e-30,n=10,m=6.1e-1)
m..model mmedmod = (type=_n,vto=1.86,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.2,kp=120,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.63,kp=1e-1,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.00,voff=-1.00)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.00,voff=-6.00)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=0,voff=1.65)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.65,voff=0)
c.ca n12 n8 = 2.35e-9
c.cb n15 n14 = 2.35e-9
c.cin n6 n8 = 1.45e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 5.42e-9
l.lgate n1 n9 = 1.00e-9
l.lsource n3 n7 = 4.16e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9.97e-4,tc2=1.24e-7
res.rdbody n71 n5 =5.32e-3, tc1=7.0e-4, tc2=1.21e-6
res.rdbreak n72 n5 =8.25e-2, tc1=9.12e-4, tc2=8.14e-7
res.rdrain n50 n16 = 3.5e-4, tc1=7.2e-2,tc2=1e-4
res.rgate n9 n20 = 2.61
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 41.6
res.rslc1 n5 n51 = 1e-6, tc1=1.07e-3,tc2=-1.25e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1=1e-11,tc2=1e-11
res.rvtemp n18 n19 = 1, tc1=-1.08e-3,tc2=9.73e-7
res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-9.2e-6
spe.ebreak n11 n7 n17 n18 = 33.34
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/450))** 3))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76132P3, HUF76132S3S
2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
SPICE Thermal Model
REV May 1998
HUF76132
CTHERM1 th 6 5.00e-3
CTHERM2 6 5 1.18e-2
CTHERM3 5 4 15.5e-2
CTHERM4 4 3 1.85e-2
CTHERM5 3 2 2.00e-2
CTHERM6 2 tl 2.5e-2
RTHERM1 th 6 1.51e-2
RTHERM2 6 5 1.51e-2
RTHERM3 5 4 3.03e-2
RTHERM4 4 3 6.05e-2
RTHERM5 3 2 1.81e-1
RTHERM6 2 tl 2.45e-1
SABER Thermal Model
SABER thermal model HUF76132
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.50e-3
ctherm.ctherm2 6 5 = 1.18e-2
ctherm.ctherm3 5 4 = 1.55e-2
ctherm.ctherm4 4 3 = 1.85e-2
ctherm.ctherm5 3 2 = 2.00e-2
ctherm.ctherm6 2 tl = 2.50e-2
rtherm.rtherm1 th 6 = 1.51e-2
rtherm.rtherm2 6 5 = 1.51e-2
rtherm.rtherm3 5 4 = 3.03e-2
rtherm.rtherm4 4 3 = 6.05e-2
rtherm.rtherm5 3 2 = 1.81e-1
rtherm.rtherm6 2 tl = 2.45e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
HUF76132P3, HUF76132S3S
Rev. I2
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PRODUCT STATUS DEFINITIONS
Definition of Terms
ACExTM
ActiveArrayTM
BottomlessTM
CoolFETTM
CROSSVOLTTM
DOMETM
EcoSPARKTM
E
2
CMOSTM
EnSignaTM
FACTTM
FACT Quiet SeriesTM
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