ChipFind - документация

Электронный компонент: IRLU130

Скачать:  PDF   ZIP
IRLR/U130A
BV
DSS
= 100 V
R
DS(on)
= 0.12
I
D
= 13 A
100
13
8
45
20
225
13
4.6
6.5
2.5
46
0.37
- 55 to +150
300
2.7
50
110
--
--
--
1
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current: 10
A (Max.) @ V
DS
= 100V
Lower R
DS(ON)
: 0.101
(Typ.)
$GYDQFHG 3RZHU 026)(7
Thermal Resistance
Junction-to-Case
Junction-to-Ambient
Junction-to-Ambient
R
JC
R
JA
R
JA
C/W
Characteristic
Max.
Units
Symbol
Typ.
FEATURES
*
*
When mounted on the minimum pad size recommended (PCB Mount).
Absolute Maximum Ratings
Drain-to-Source Voltage
Continuous Drain Current (T
C
=25
C)
Continuous Drain Current (T
C
=100
C)
Drain Current-Pulsed
(1)
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
(2)
Avalanche Current
(1)
Repetitive Avalanche Energy
(1)
Peak Diode Recovery dv/dt
(3)
Total Power Dissipation (T
A
=25
C)
Total Power Dissipation (T
C
=25
C)
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8 from case for 5-seconds
Characteristic
Value
Units
Symbol
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
D
I
D
T
J
, T
STG
T
L
A
V
mJ
A
mJ
V/ns
W
W
W/
C
A
C
V
DSS
V
*
D-PAK
1. Gate 2. Drain 3. Source
1
2
3
I-PAK
1
3
2
1999 Fairchild Semiconductor Corporation
Rev. B
IRLR/U130A
100
--
1.0
--
--
--
--
--
0.1
--
--
--
--
--
140
60
10
11
29
15
16.9
2.7
9.7
--
--
2.0
100
-100
10
100
0.12
--
755
175
75
30
30
70
40
24
--
--
10.1
580
--
--
--
109
0.41
13
45
1.5
--
--
Notes;
(1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature
(2) L=2mH, I
AS
=13A, V
DD
=25V, R
G
=27
, Starting T
J
=25
C
(3) I
SD
14A, di/dt
350A/
s, V
DD
BV
DSS
, Starting T
J
=25
C
(4) Pulse Test: Pulse Width = 250
s, Duty Cycle
2%
(5) Essentially Independent of Operating Temperature
2
1&+$11(/
32:(5 026)(7
Electrical Characteristics
(T
C
=25
C unless otherwise specified)
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
Characteristic
Symbol
Max. Units
Typ.
Min.
Test Condition
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain ( Miller ) Charge
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
BV
DSS
BV/
T
J
V
GS(th)
R
DS(on)
I
GSS
I
DSS
V
V/
C
V
nA
A
pF
ns
nC
--
--
--
--
--
--
--
--
--
--
--
--
--
V
GS
=0V,I
D
=250
A
I
D
=250
A
See Fig 7
V
DS
=5V,I
D
=250
A
V
GS
=20V
V
GS
=-20V
V
DS
=100V
V
DS
=80V,T
C
=150
C
V
GS
=5V,I
D
=6.5A
(4)
V
DS
=40V,I
D
=6.5A
(4)
V
DD
=50V,I
D
=14A,
R
G
=6
See Fig 13
(4) (5)
V
DS
=80V,V
GS
=5V,
I
D
=14A
See Fig 6 & Fig 12
(4) (5)
Drain-to-Source Leakage Current
V
GS
=0V,V
DS
=25V,f =1MHz
See Fig 5
Source-Drain Diode Ratings and Characteristics
Continuous Source Current
Pulsed-Source Current
(1)
Diode Forward Voltage
(4)
Reverse Recovery Time
Reverse Recovery Charge
I
S
I
SM
V
SD
t
rr
Q
rr
Characteristic
Symbol
Max. Units
Typ.
Min.
Test Condition
--
--
--
--
--
A
V
ns
C
Integral reverse pn-diode
in the MOSFET
T
J
=25
C,I
S
=13A,V
GS
=0V
T
J
=25
C,I
F
=14A
di
F
/dt=100A/
s
(4)
IRLR/U130A
10
-1
10
0
10
1
10
0
10
1
10
2
@ Notes :
1. 250
s Pulse Test
2. T
C
= 25
o
C
V
GS
Top : 7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
I
D
,
Dr
ai
n C
urr
en
t
[A]
V
DS
, Drain-Source Voltage [V]
0
15
30
45
60
0.00
0.05
0.10
0.15
0.20
@ Note : T
J
= 25
o
C
V
GS
= 10 V
V
GS
= 5 V
R
DS
(o
n)
, [
]
Dr
ain
-S
our
ce On
-Re
sis
ta
nce
I
D
, Drain Current [A]
0
3
6
9
12
15
18
0
2
4
6
V
DS
= 80 V
V
DS
= 50 V
V
DS
= 20 V
@ Notes : I
D
= 14 A
V
GS
,
Gat
e-So
urce
Vol
tag
e [
V
]
Q
G
, Total Gate Charge [nC]
0
2
4
6
8
10
10
-1
10
0
10
1
25
o
C
150
o
C
- 55
o
C
@ Notes :
1. V
GS
= 0 V
2. V
DS
= 40 V
3. 250
s Pulse Test
I
D
,
Dra
in C
urre
nt
[A]
V
GS
, Gate-Source Voltage [V]
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
10
-1
10
0
10
1
150
o
C
25
o
C
@ Notes :
1. V
GS
= 0 V
2. 250
s Pulse Test
I
DR
,
Rev
erse
Dra
in C
urr
ent
[A]
V
SD
, Source-Drain Voltage [V]
10
0
10
1
0
200
400
600
800
1000
C
iss
= C
gs
+ C
gd
(
C
ds
= shorted
)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
@ Notes :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
oss
C
iss
Ca
pac
it
anc
e
[p
F]
V
DS
, Drain-Source Voltage [V]
1&+$11(/
32:(5 026)(7
Fig 1. Output Characteristics
Fig 2. Transfer Characteristics
Fig 6. Gate Charge vs. Gate-Source Voltage
Fig 5. Capacitance vs. Drain-Source Voltage
Fig 4. Source-Drain Diode Forward Voltage
Fig 3. On-Resistance vs. Drain Current
IRLR/U130A
-75
-50
-25
0
25
50
75
100
125
150
175
0.8
0.9
1.0
1.1
1.2
@ Notes :
1. V
GS
= 0 V
2. I
D
= 250
A
BV
DSS
,
(No
rmal
ized
)
Dr
ain-
Sour
ce B
reak
dow
n Vo
ltag
e
T
J
, Junction Temperature [
o
C]
25
50
75
100
125
150
0
3
6
9
12
15
I
D
,
Dr
ai
n C
urr
en
t
[A]
T
c
, Case Temperature [
o
C]
10
- 5
10
- 4
10
- 3
10
- 2
10
- 1
10
0
10
1
10
- 2
10
- 1
10
0
single pulse
0.2
0.1
0.01
0.02
0.05
D=0.5
@ Notes :
1. Z
J C
(t)=2.7
o
C/W Max.
2. Duty Factor, D=t
1
/t
2
3. T
J M
-T
C
=P
D M
*Z
J C
(t)
Z
JC
(t)
,
Ther
mal
Resp
onse
t
1
, Square Wave Pulse Duration [sec]
-75
-50
-25
0
25
50
75
100
125
150
175
0.0
0.5
1.0
1.5
2.0
2.5
@ Notes :
1. V
GS
= 5 V
2. I
D
= 7 A
R
DS
(o
n)
,
(N
or
mal
ize
d)
Dr
ain
-S
our
ce On
-Re
sis
ta
nce
T
J
, Junction Temperature [
o
C]
10
0
10
1
10
2
10
-1
10
0
10
1
10
2
DC
100
s
1 ms
10 ms
@ Notes :
1. T
C
= 25
o
C
2. T
J
= 150
o
C
3. Single Pulse
Operation in This Area
is Limited by R
DS(on)
I
D
,
Dra
in C
urre
nt
[A]
V
DS
, Drain-Source Voltage [V]
1&+$11(/
32:(5 026)(7
Fig 7. Breakdown Voltage vs. Temperature
Fig 8. On-Resistance vs. Temperature
Fig 11. Thermal Response
Fig 10. Max. Drain Current vs. Case Temperature
Fig 9. Max. Safe Operating Area
P
DM
t
1
t
2
IRLR/U130A
5
1&+$11(/
32:(5 026)(7
Fig 12. Gate Charge Test Circuit & Waveform
Fig 13. Resistive Switching Test Circuit & Waveforms
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
E
AS
=
L
L
I
AS
2
----
2
1
--------------------
BV
DSS
-- V
DD
BV
DSS
V
in
V
out
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
Vary t
p
to obtain
required peak I
D
5V
V
DD
C
L
L
V
DS
I
D
R
G
t
p
DUT
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
V
DD
( 0.5 rated V
DS
)
5V
V
out
V
in
R
L
DUT
R
G
3mA
V
GS
Current Sampling (I
G
)
Resistor
Current Sampling (I
D
)
Resistor
DUT
V
DS
300nF
50k
200nF
12V
Same Type
as DUT
Current Regulator
R
1
R
2