Features at +2.7V
80
A supply current per channel
1.2MHz gain bandwidth product
Output voltage range: 0.01V to 2.69V
Input voltage range: -0.25V to +1.5V
1.5V/
s slew rate
LMV321 directly replaces other industry standard LMV321
amplifiers; available in SC70-5 and SOT23-5 packages
LMV358 directly replaces other industry standard LMV358
amplifiers; available in MSOP-8 and SOIC-8 packages
LMV324 directly replaces other industry standard LMV324
amplifiers; available in TSSOP-14 and SOIC-14 packages
Fully specified at +2.7V and +5V supplies
Operating temperature range: -40C to +125C
Applications
Low cost general purpose applications
Cellular phones
Personal data assistants
A/D buffer
DSP interface
Smart card readers
Portable test instruments
Keyless entry
Infrared receivers for remote controls
Telephone systems
Audio applications
Digital still cameras
Hard disk drives
MP3 players
Description
The LMV321 (single), LMV358 (dual), and LMV324 (quad)
are a low cost, voltage feedback amplifiers that consume only
80
A of supply current per amplifier. The LMV3XX family
is designed to operate from 2.7V (1.35V) to 5.5V (2.75V)
supplies. The common mode voltage range extends below the
negative rail and the output provides rail-to-rail performance.
The LMV3XX family is designed on a CMOS process and
provides 1.2MHz of bandwidth and 1.5V/
s of slew rate at a
low supply voltage of 2.7V. The combination of low power,
rail-to-rail performance, low voltage operation, and tiny pack-
age options make the LMV3XX family well suited for use in
personal electronics equipment such as cellular handsets,
pagers, PDAs, and other battery powered applications.
LMV321, LMV358, LMV324
General Purpose, Low Voltage, Rail-to-Rail Output Amplifiers
www.fairchildsemi.com
Rev. 1 November 2002
+
-
LMV3XX
R
f
0.01
F
6.8
F
Out
+In
+V
s
+
R
g
Typical Application
Frequency Response vs. C
L
Magnitude (1dB/div)
Frequency (MHz)
0.01
0.1
1
10
C
L
= 200pF
R
s
= 0
C
L
= 20pF
R
s
= 0
C
L
= 200pF
R
s
= 225
C
L
= 100pF
R
s
= 0
C
L
= 10pF
R
s
= 0
C
L
= 2pF
R
s
= 0
C
L
= 50pF
R
s
= 0
+
-
10k
10k
R
s
C
L
2k
DATA SHEET
LMV321/LMV358/LMV324
2
Rev. 1 November 2002
LMV321
+
1
2
3
+In
-V
s
-In
+V
s
Out
5
4
+
1
2
3
+In
-V
s
-In
+V
s
Out
5
4
SC70-5
LMV358
-
+
-
+
1
2
3
4
Out1
-In1
+In1
-V
s
+V
s
Out2
-In2
+In2
8
7
6
5
MSOP-8
-
+
-
+
1
2
3
4
Out1
-In1
+In1
-V
s
+V
s
Out2
-In2
+In2
8
7
6
5
SOIC-8
LMV324
1
2
3
4
Out1
-In1
+In1
+V
s
Out4
-In4
+In4
-V
s
14
13
12
11
5
6
7
+In2
-In2
Out2
+In3
-In3
Out3
10
9
8
TSSOP-14
SOT23-5
Pin Assignments
1
2
3
4
Out1
-In1
+In1
+V
s
Out4
-In4
+In4
-V
s
14
13
12
11
5
6
7
+In2
-In2
Out2
+In3
-In3
Out3
10
9
8
SOIC-14
LMV321/LMV358/LMV324
DATA SHEET
Rev. 1 November 2002
3
Absolute Maximum Ratings
Parameter
Min.
Max.
Unit
Supply Voltages
0
+6
V
Maximum Junction Temperature
+175
C
Storage Temperature Range
-65
+150
C
Lead Temperature, 10 seconds
+260
C
Input Voltage Range
-Vs -0.5 +Vs +0.5
V
Electrical Specifications
(T
c
= 25C, V
s
= +2.7V, G = 2, R
L
= 10k
to V
s
/2, R
f
= 10k
, V
o (DC)
= V
cc
/2; unless otherwise noted)
Parameter
Conditions
Min.
Typ.
Max.
Unit
AC Performance
Gain Bandwidth Product
C
L
= 50pF, R
L
= 2k
to V
s
/2
1.2 MHz
Phase Margin
52
deg
Gain Margin
17
dB
Slew Rate
V
o
= 1V
pp
1.5 V/
s
Input Voltage Noise
>50kHz
36
nV/
Hz
Crosstalk: LMV358
100kHz
91
dB
LMV324
100kHz
80
dB
DC Performance
Input Offset Voltage
1
1.7
7
mV
Average Drift
8
V/C
Input Bias Current
2
<1
nA
Input Offset Current
2
<1
nA
Power Supply Rejection Ratio
1
DC
50
65
dB
Supply Current (Per Channel)
1
80
120
A
Input Characteristics
Input Common Mode Voltage Range
1
LO
0
-0.25
V
HI
1.5
1.3
V
Common Mode Rejection Ratio
1
50
70
dB
Output Characteristics
Output Voltage Swing
R
L
= 10k
to V
s
/2; LO
1
0.1
0.01
V
R
L
= 10k
to V
s
/2; HI
1
2.69
2.6
V
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Recommended Operating Conditions
Parameter
Min.
Max.
Unit
Operating Temperature Range
-40
+125
C
Power Supply Operating Range
2.5
5.5
V
DATA SHEET
LMV321/LMV358/LMV324
4
Rev. 1 November 2002
Electrical Specifications
(T
c
= 25C, V
s
= +5V, G = 2, R
L
= 10k
to V
s
/2, R
f
= 10k
, V
o (DC)
= V
cc
/2; unless otherwise noted)
Parameter
Conditions
Min.
Typ.
Max.
Unit
AC Performance
Gain Bandwidth Product
C
L
= 50pF, R
L
= 2k
to V
s
/2
1.4 MHz
Phase Margin
73
deg
Gain Margin
12
dB
Slew Rate
1.5
V/
s
Input Voltage Noise
>50kHz
33
nV/
Hz
Crosstalk: LMV358
100kHz
91
dB
LMV324
100kHz
80
dB
DC Performance
Input Offset Voltage
1
1
7
mV
Average Drift
6
V/C
Input Bias Current
2
<1
nA
Input Offset Current
2
<1
nA
Power Supply Rejection Ratio
1
DC
50
65
dB
Open Loop Gain
1
50
70
dB
Supply Current (Per Channel)
1
100
150
A
Input Characteristics
Input Common Mode Voltage Range
1
LO
0
-0.4
V
HI
3.8
3.6
V
Common Mode Rejection Ratio
1
50
75
dB
Output Characteristics
Output Voltage Swing
R
L
= 2k
to V
s
/2; LO/HI
0.036 to 4.95
V
R
L
= 10k
to V
s
/2; LO
1
0.1
0.013
V
R
L
= 10k
to V
s
/2; HI
1
4.98
4.9 V
Short Circuit Output Current
1
sourcing; V
o
= 0V
5
+34
mA
sinking; V
o
= 5V
10
-23
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Package Thermal Resistance
Package
JA
5 lead SC70
331.4C/W
5 lead SOT23
256C/W
8 lead SOIC
152C/W
8 lead MSOP
206C/W
14 lead TSSOP
100C/W
14 lead SOIC
88C/W
LMV321/LMV358/LMV324
DATA SHEET
Rev. 1 November 2002
5
Non-Inverting Freq. Response V
s
= +5V
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.01
0.1
G = 10
1
10
G = 5
G = 1
G = 2
Inverting Frequency Response V
s
= +5V
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.01
0.1
G = -10
1
10
G = -5
G = -1
G = -2
Non-Inverting Freq. Response V
s
= +2.7V
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.01
0.1
G = 10
1
10
G = 5
G = 1
G = 2
Inverting Freq. Response V
s
= +2.7V
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.01
0.1
G = -10
1
10
G = -5
G = -1
G = -2
Frequency Response vs. C
L
Magnitude (1dB/div)
Frequency (MHz)
0.01
0.1
1
10
C
L
= 200pF
R
s
= 0
C
L
= 20pF
R
s
= 0
C
L
= 200pF
R
s
= 225
C
L
= 100pF
R
s
= 0
C
L
= 10pF
R
s
= 0
C
L
= 2pF
R
s
= 0
C
L
= 50pF
R
s
= 0
+
-
10k
10k
R
s
C
L
2k
Frequency Response vs. R
L
Magnitude (1dB/div)
Frequency (MHz)
0.01
0.1
1
10
R
L
= 1k
R
L
= 2k
R
L
= 100k
R
L
= 10k
Small Signal Pulse Response
Output (V)
Time (
s)
0
20
2
4
6
8
10
12
14
16
18
-0.05
0.1
0.25
0
0.05
0.2
0.15
Large Signal Pulse Response
Output (V)
Time (
s)
0
20
2
4
6
8
10
12
14
16
18
-0.5
0.1
2.5
0
0.5
2
1.5
Typical Operating Characteristics
(T
c
= 25C, V
s
= +5V, G = 2, R
L
= 10k
to V
s
/2, R
f
= 10k
, V
o (DC)
= V
cc
/2; unless otherwise noted)
DATA SHEET
LMV321/LMV358/LMV324
6
Rev. 1 November 2002
Input Voltage Noise
nV/
Hz
Frequency (kHz)
1
10
100
1000
20
30
40
50
60
70
80
100
Total Harmonic Distortion
THD (%)
Frequency (kHz)
0.1
1
10
100
0
0.1
0.2
0.3
0.4
0.5
0.6
V
o
= 1V
pp
Open Loop Gain & Phase vs. Frequency
Open Loop Phase (deg)
Frequency (Hz)
10M
10
100
100k
10k
1k
1M
-270
-225
-180
0
-135
-45
-90
-20
0
20
100
40
80
60
Open Loop Gain (dB)
|Gain|
Phase
R
L
= 2k
C
L
= 50pF
Typical Operating Characteristics
(T
c
= 25C, V
s
= +5V, G = 2, R
L
= 10k
to V
s
/2, R
f
= 10k
, V
o (DC)
= V
cc
/2; unless otherwise noted)
LMV321/LMV358/LMV324
DATA SHEET
Rev. 1 November 2002
7
Application Information
General Description
The LMV3XX family are single supply, general purpose,
voltage-feedback amplifiers that are pin-for-pin compatible
and drop in replacements with other industry standard
LMV321, LMV358, and LMV324 amplifiers. The LMV3XX
family is fabricated on a CMOS process, features a rail-to-rail
output, and is unity gain stable.
The typical non-inverting circuit schematic is shown in
Figure 1.
Figure 1: Typical Non-inverting configuration
Power Dissipation
The maximum internal power dissipation allowed is directly
related to the maximum junction temperature. If the maximum
junction temperature exceeds 150C, some performance
degradation will occur. If the maximum junction temperature
exceeds 175C for an extended time, device failure may occur.
Driving Capacitive Loads
The Frequency Response vs C
L
plot on page 4, illustrates the
response of the LMV3XX family. A small series resistance (R
s
)
at the output of the amplifier, illustrated in Figure 2, will improve
stability and settling performance. R
s
values in the Frequency
Response vs C
L
plot were chosen to achieve maximum band-
width with less than 1dB of peaking. For maximum flatness,
use a larger R
s
. As the plot indicates, the LMV3XX family
can easily drive a 200pF capacitive load without a series
resistance. For comparison, the plot also shows the LMV321
driving a 200pF load with a 225
series resistance.
Driving a capacitive load introduces phase-lag into the output
signal, which reduces phase margin in the amplifier. The
unity gain follower is the most sensitive configuration. In a
unity gain follower configuration, the LMV3XX family
requires a 450
series resistor to drive a 200pF load. The
response is illustrated in Figure 3.
Figure 2: Typical Topology for driving a
capacitive load
Figure 3: Frequency Response vs C
L
for unity
gain configuration
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance. Fairchild has evaluation boards to
use as a guide for high frequency layout and as aid in device
testing and characterization. Follow the steps below as a
basis for high frequency layout:
Include 6.8
F and 0.01
F ceramic capacitors
Place the 6.8
F capacitor within 0.75 inches of
the power pin
Place the 0.01
F capacitor within 0.1 inches of
the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts shown in Figure 5 on
page 8 for more information.
+
-
LMV3XX
R
f
0.01
F
6.8
F
Out
+In
+V
s
+
R
g
+
-
10k
10k
R
s
C
L
2k
LMV3XX
Magnitude (dB)
Frequency (M H z )
0.01
0.1
1
10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
C
L
= 50pF
R
s
= 0
C
L
= 100pF
R
s
= 400
C
L
= 200pF
R
s
= 450
DATA SHEET
LMV321/LMV358/LMV324
8
Rev. 1 November 2002
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of this device:
Evaluation board schematics and layouts are shown in Figures
4 and 5.
Eval Bd
Description
Products
KEB013
Single Channel, Dual Supply,
LMV321AS5X
SOT23-5 for buffer-style pinout
KEB014
Single Channel, Dual Supply,
LMV321AP5X
SC70-5 for buffer-style pinout
KEB006
Dual Channel, Dual Supply,
LMV358AM8X
8 lead SOIC
KEB010
Dual Channel, Dual Supply,
LMV358AMU8X
8 lead MSOP
KEB012
Quad Channel, Dual Supply,
LMV324AMTC14X
14 lead TSSOP
KEB018
Quad Channel, Dual Supply,
LMV324AM14X
14 lead SOIC
Evaluation Board Schematic Diagrams
Figure 4a: LMV321 KEB013 schematic
Figure 4b: LMV321 KEB014 schematic
LMV321/LMV358/LMV324
DATA SHEET
Rev. 1 November 2002
9
Evaluation Board Schematic Diagrams (Continued)
Figure 4c: LMV358 KEB006/KEB010 schematic
Figure 4d: LMV324 KEB012/KEB018 schematic
DATA SHEET
LMV321/LMV358/LMV324
10
Rev. 1 November 2002
Figure 5a: KEB013 (top side)
Figure 5b: KEB013 (bottom side)
Figure 5c: KEB014 (top side)
Figure 5d: KEB014 (bottom side)
LMV321 Evaluation Board Layout
LMV321/LMV358/LMV324
DATA SHEET
Rev. 1 November 2002
11
Figure 5g: KEB010 (top side)
Figure 5h: KEB010 (bottom side)
LMV358 Evaluation Board Layout
Figure 5e: KEB006 (top side)
Figure 5f: KEB006 (bottom side)
DATA SHEET
LMV321/LMV358/LMV324
12
Rev. 1 November 2002
LMV324 Evaluation Board Layout
Figure 5i: KEB012 (top side)
Figure 5j: KEB012 (bottom side)
Figure 5k: KEB018 (top side)
Figure 5l: KEB018 (bottom side)
LMV321/LMV358/LMV324
DATA SHEET
Rev. 1 November 2002
13
LMV321 Package Dimensions
b
e
e1
D
CL
E
CL
CL
A
A2
A1
E1
C
2
DA
TUM 'A'
CL
NOTE:
1. All dimensions are in millimeters.
2 Foot length measured reference to flat
foot surface parallel to DATUM 'A' and lead surface.
3. Package outline exclusive of mold flash & metal burr.
4. Package outline inclusive of solder plating.
5. Comply to EIAJ SC74A.
6. Package ST 0003 REV A supercedes SOT-D-2005 REV C.
SYMBOL
MIN
MAX
A
0.90
1.45
A1
0.00
0.15
A2
0.90
1.30
b
0.25
0.50
C
0.09
0.20
D
2.80
3.10
E
2.60
3.00
E1
1.50
1.75
L
0.35
0.55
e
0.95 ref
e1
1.90 ref
0
10
SOT23-5
SYMBOL
MIN
MAX
e 0.65 BSC
D
1.80
2.20
b
0.15
0.30
E
1.15
1.35
HE
1.80
2.40
Q1
0.10
0.40
A2
0.80
1.00
A1
0.00
0.10
A
0.80
1.10
c
0.10
0.18
L
1.10
0.30
b
e
D
CL
HE
CL
CL
A
A2
A1
E
C
CL
NOTE:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flashing and metal burr.
4. All speccifications comply to EIAJ SC70.
L
Q1
SC70
DATA SHEET
LMV321/LMV358/LMV324
14
Rev. 1 November 2002
LMV358 Package Dimensions
H
E
CL
ZD
CL
e
D
Pin No. 1
B
A
A1
A2
7
L
DETAIL-A
DETAIL-A
C
h x 45
NOTE:
1. All dimensions are in millimeters.
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side(d).
SYMBOL
MIN
MAX
A1
0.10
0.25
B
0.36
0.46
C
0.19
0.25
D
4.80
4.98
E
3.81
3.99
e
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.41
1.27
A
1.52
1.72
0
ZD
0.53 ref
A2
1.37
1.57
8
SOIC-8
SOIC
e
S
E/2 2X
E3
E4
1
2
ccc A B C
B
2
3
7
2
6
4
D2
A2
A
A1
A
C
bbb
A B C
M
b
D
4
3
aaa A
E1
H
t1
t2
Gauge
Plane
0.25mm
R1
R
L
L1
03
02
01
Detail A
Scale 40:1
Section A - A
b
c
c1
b1
E2
E1
E
Detail A
5
A
A
SYMBOL
MIN
MAX
A
1.10
A1
0.10
0.05
A2
0.86
0.08
D
3.00
0.10
D2
2.95
0.10
E
4.90
0.15
E1
3.00
0.10
E2
2.95
0.10
E3
0.51
0.13
E4
0.51
0.13
R
0.15
+0.15/-0.06
R1
0.15
+0.15/-0.06
t1
0.31
0.08
t2
0.41
0.08
b
0.33
+0.07/-0.08
b1
0.30
0.05
c
0.18
0.05
c1
0.15
+0.03/-0.02
01
3.0
3.0
02
12.0
3.0
03
12.0
3.0
L
0.55
0.15
L1
0.95 BSC
aaa
0.10
bbb
0.08
ccc
0.25
e
0.65 BSC
S
0.525 BSC
MSOP-8
NOTE:
1 All dimensions are in millimeters (angle in degrees), unless otherwise specified.
2
Datums B and C to be determined at datum plane H .
3
Dimensions "D" and "E1" are to be determined at datum H .
4
Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package.
5
Cross sections A A to be determined at 0.13 to 0.25mm from the leadtip.
6
Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs.
7
Dimension "E1" and "E2" does not include interlead flash or protrusion.
MSOP
LMV321/LMV358/LMV324
DATA SHEET
Rev. 1 November 2002
15
E/2
2X
ddd C B A
6
6
1.0
1.0
1 2 3
9
e /2
E1 E
e
N
8
B
7
2X
N/2 TIPS
1.0 DIA
A
7
C
aaa C
ccc
8
3
D
C B A
bbb
M
b NX
A1
A2
A
c1
c
(b)
b1
5
SECTION AA
10
A
A
H
GAGE
PLANE
0.25
(0.20)
(02)
R1
R
01
(L1)
L
(03)
NOTES:
1 All dimensions are in millimeters (angle in degrees).
2
Dimensioning and tolerancing per ASME Y14.51994.
3
Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side .
4
Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side.
5
Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum
material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm
for 0.5mm pitch packages.
6
Terminal numbers are shown for reference only.
7
Datums A and B to be determined at datum plane H .
8
Dimensions "D" and "E1" to be determined at datum plane H .
9
This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center"
lead must be coincident with the package centerline, Datum A.
10
Cross sections A A to be determined at 0.10 to 0.25mm from the leadtip.
SYMBOL MIN NOM
MAX
A 1.10
A1 0.05 0.15
A2 0.85
0.90 0.95
L 0.50
0.60 0.75
R 0.09
R1 0.09
b 0.19 0.30
b1 0.19
0.22 0.25
c 0.09 0.20
c1 0.09 0.16
01 0 8
L1
1.0
REF
aaa 0.10
bbb 0.10
ccc 0.05
ddd 0.20
e
0.65
BSC
02
12
REF
03
12
REF
TSSOP-14
D 4.90
5.00 5.10
E1 4.30
4.40 4.50
E
6.4
BSC
e
0.65
BSC
N 14
TSSOP
LMV324 Package Dimensions
H
E
CL
ZD
CL
e
D
Pin No. 1
B
A
A1
A2
7
L
DETAIL-A
DETAIL-A
C
h x 45
NOTE:
1. All dimensions are in inches.
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side (d).
SYMBOL MIN
MAX
A1 .0040
.0098
B .014
.018
C .0075
.0098
D .337
.344
E .150
.157
e .050
BSC
H .2284
.2440
h .0099
.0196
L .016
.050
A .060
.068
0
ZD
0.20
ref
A2 .054
.062
8
SOIC-14
SOIC
www.fairchildsemi.com
2002 Fairchild Semiconductor Corporation
Ordering Information
Model Part Number Package Container
Pack Qty
LMV321
LMV321AP5X
SC70-5
Reel
3000
LMV321
LMV321AS5X
SOT23-5
Reel
3000
LMV358
LMV358AM8X
SOIC-8
Reel
2500
LMV358 LMV358AMU8X
MSOP-8
Reel
3000
LMV324 LMV324AMTC14X
TSSOP
Reel
2500
LMV324 LMV324AM14X
SOIC
Reel
2500
Temperature range for all parts: -40C to +125C.
DATA SHEET
LMV321/LMV358/LMV324
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN.
FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE
PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1.
Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury of the user.
2.
A critical component in any component of a life support device or system whose failure
to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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