2001 Fairchild Semiconductor Corporation
DS500698
www.fairchildsemi.com
November 2001
Revised November 2001
7
4
AL
VC1628
27
Low V
o
l
t
a
ge
20
-Bit
B
u
ff
er/
L
ine Dri
ver wit
h
3.
6V
T
o
l
e
ran
t
Input
s
a
nd
Out
puts and 26
Seri
es
Res
i
st
ors in the
O
u
tp
uts
74ALVC162827
Low Voltage 20-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26
Series Resistors in the Outputs
General Description
The ALVC162827 contains twenty non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is byte controlled. Each byte has NOR
output enables for maximum control flexibility.
The 74ALVC162827 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V. The
ALVC162827 is also designed with 26
resistors in the
outputs.
The 74ALVC162827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26
series resistors in outputs
s
t
PD
3.9 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
8.2 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix "X" to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
Package Number
Package Description
74ALVC162827T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
I
0
I
19
Inputs
O
0
O
19
Outputs
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2
74AL
VC162827
Connection Diagram
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
Functional Description
The 74ALVC162827 contains twenty non-inverting buffers
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of each
other. The control pins may be shorted together to obtain
full 20-bit operation. The 3-STATE outputs are controlled by
Output Enable (OE
n
) inputs. When OE
1
, and OE
2
are
LOW, O
0
O
10
are in the 2-state mode. When either OE
1
or
OE
2
are HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs. The same applies for byte two with
OE
3
and OE
4
.
Logic Diagrams
Inputs
Outputs
OE
1
OE
2
I
0
I
9
O
0
O
9
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
Inputs
Outputs
OE
3
OE
4
I
0
I
9
O
10
O
19
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
3
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7
4
AL
VC1628
27
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
(Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to 4.6V
Output Voltage (V
O
) (Note 3)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 - 1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
2 mA
1.65
1.2
I
OH
=
-
4 mA
2.3
1.9
I
OH
=
-
6 mA
2.3
1.7
3
2.4
I
OH
=
-
8 mA
2.7
2
I
OH
=
-
12 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
2 mA
1.65
0.45
I
OL
=
4 mA
2.3
0.4
I
OL
=
6 mA
2.3
0.55
3
0.55
I
OL
=
8 mA
2.7
0.6
I
OL
=
12 mA
3
0.8
I
I
Input Leakage Current
0
V
I
3.6V
3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
3.6
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
3 - 3.6
750
A
5
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7
4
AL
VC1628
27
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
TABLE 1. Values for Figure 1
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
0
=
50
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
L
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5V
0.2V
1.8V
0.15V
V
mi
1.5V
1.5V
V
CC
/2
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
CC
/2
V
X
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
OL
+
0.15V
V
Y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
V
OH
-
0.15V
V
L
6V
6V
V
CC
*2
V
CC
*2
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