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Электронный компонент: MM74HC132N

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September 1983
Revised February 1999
MM74HC132 Q
u
ad
2-
Inp
u
t NA
ND Schm
i
t
t
T
r
i
gger
1999 Fairchild Semiconductor Corporation
DS005309.prf
www.fairchildsemi.com
MM74HC132
Quad 2-Input NAND Schmitt Trigger
General Description
The MM74HC132 utilizes advanced silicon-gate CMOS
technology to achieve the low power dissipation and high
noise immunity of standard CMOS, as well as the capability
to drive 10 LS-TTL loads.
The 74HC logic family is functionally and pinout compatible
with the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to V
CC
and ground.
Features
s
Typical propagation delay: 12 ns
s
Wide power supply range: 2V6V
s
Low quiescent current: 20
A maximum (74HC Series)
s
Low input current: 1
A maximum
s
Fanout of 10 LS-TTL loads
s
Typical hysteresis voltage: 0.9V at V
CC
=
4.5V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (Tape and Reel not available in N14A.)
Connection Diagram
Pin Assignment for DIP, SOIC, SOP, and TSSOP
Top View
Logic Diagram
Order Number
Package Number
Package Description
MM74HC132M M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body
MM74HC132SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC132MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC132N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
MM
74HC132
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
-
DC Electrical Characteristics
(Note 4)
Note 4: For a power supply of 5V
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
20 mA
DC Output Current, per pin (I
OUT
)
25 mA
DC V
CC
or GND Current, per pin (I
CC
)
50 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
0
V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
-
40
+
125
C
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
= -40 to 85
C T
A
= -40 to 125
C
Units
Typ
Guaranteed Limits
V
T
+
Positive Going
Min
2.0V
1.0
1.0
1.0
V
Threshold Voltage
4.5V
2.0
2.0
2.0
V
6.0V
3.0
3.0
3.0
V
Max
2.0V
1.5
1.5
1.5
V
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
V
T
-
Negative Going
Min
2.0V
0.3
0.3
0.3
V
Threshold Voltage
4.5V
0.9
0.9
0.9
V
6.0V
1.2
1.2
1.2
V
Max
2.0V
1.0
1.0
1.0
V
4.5V
2.2
2.2
2.2
V
6.0V
3.0
3.0
3.0
V
V
H
Hysteresis Voltage
Min
2.0V
0.2
0.2
0.2
V
4.5V
0.4
0.4
0.4
V
6.0V
0.5
0.5
0.5
V
Max
2.0V
1.0
1.0
1.0
V
4.5V
1.4
1.4
1.4
V
6.0V
1.5
1.5
1.5
V
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
2.0V
2.0
1.9
1.9
1.9
V
Output Voltage
|I
OUT
|
20
A
4.5V
4.5
4.4
4.4
4.4
V
V
IN
=
V
IH
or V
IL
6.0V
6.0
5.9
5.9
5.9
V
|I
OUT
|
4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
V
OL
Maximum
LOW
Level V
IN
=
V
IH
or V
IL
2.0V
0
0.1
0.1
0.1
V
Output Voltage
|I
OUT
|
20
A
4.5V
0
0.1
0.1
0.1
V
V
IN
=
V
IH
or V
IL
6.0V
0
0.1
0.1
0.1
V
|I
OUT
|
4.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
5.2 mA
6.0V
0.2
0.26
0.33
0.4
V
I
IN
Maximum Input Current
V
IN
=
V
CC
or GND
6.0V
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
6.0V
2.0
20
40
A
Supply Current
I
OUT
=
0
A
3
www.fairchildsemi.com
MM74HC132
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Note 5: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
t
PHL
, t
PLH
Maximum Propagation Delay
12
20
ns
Symbol
Parameter
Conditions
V
CC
T
A
= 25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum
2.0V
63
125
158
186
ns
Propagation Delay
4.5V
13
25
32
37
ns
6.0V
11
21
27
32
ns
t
TLH
, t
THL
Maximum Output
2.0V
30
75
95
110
ns
Rise and Fall Time
4.5V
8
15
19
22
ns
6.0V
7
13
16
19
ns
C
PD
Power Dissipation
(per gate)
130
pF
Capacitance (Note 5)
C
IN
Maximum Input Capacitance
5
10
10
pF
www.fairchildsemi.com
4
MM
74HC132
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
MM74HC132
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM
74HC132

Quad 2-I
nput NAND
Schmit
t T
r
i
gger
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A