September 1983
Revised February 1999
MM74HC259 8-Bi
t Address
able Lat
ch/3-
to-
8
Line Decoder
1999 Fairchild Semiconductor Corporation
DS005006.prf
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MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
The MM74HC259 device utilizes advanced silicon-gate
CMOS technology to implement an 8-bit addressable latch,
designed for general purpose storage applications in digital
systems.
The MM74HC259 has a single data input (D), 8 latch out-
puts (Q1Q8), 3 address inputs (A, B, and C), a common
enable input (G), and a common CLEAR input. To operate
this device as an addressable latch, data is held on the D
input, and the address of the latch into which the data is to
be entered is held on the A, B, and C inputs. When
ENABLE is taken LOW the data flows through to the
addressed output. The data is stored when ENABLE transi-
tions from LOW-to-HIGH. All unaddressed latches will
remain unaffected. With enable in the HIGH state the
device is deselected, and all latches remain in their previ-
ous state, unaffected by changes on the data or address
inputs. To eliminate the possibility of entering erroneous
data into the latches, the enable should be held HIGH
(inactive) while the address lines are changing.
If enable is held HIGH and CLEAR is taken LOW all eight
latches are cleared to a LOW state. If enable is LOW all
latches except the addressed latch will be cleared. The
addressed latch will instead follow the D input, effectively
implementing a 3-to-8 line decoder.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 18 ns
s
Wide supply range: 26V
s
Low input current: 1
A maximum
s
Low quiescent current: 80
A maximum (74HC Series)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Latch Selection Table
H
=
HIGH level, L
=
LOW level
D
=
the level at the data input
Q
i0
the level of Q
i
(i
=
0, 1 .. .7, as appropriate)
before the indicated steady-state input
conditions were established.
Order Number
Package Number Package Description
MM74HC259M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
MM74HC259SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC259MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC259N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Select Inputs
Latch
C
B
A
Addressed
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
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2
MM
74HC259
Truth Table
Logic Diagram
Inputs
Outputs of
Each
Addressed
Other
Function
Clear
G
Latch
Output
H
L
D
Q
i0
Addressable Latch
H
H
Q
i0
Q
i0
Memory
L
L
D
L
8-Line Decoder
L
H
L
L
Clear
3
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MM74HC259
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
-
12 mW/
C from 65
C to 85
C
DC Electrical Characteristics
(Note 4)
Note 4: For a power supply of 5V
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current
(I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
20 mA
DC Output Current, per pin (I
OUT
)
25 mA
DC V
CC
or GND Current, per pin (I
CC
)
50 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
0
V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
-
40
+
85
C
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
1000
ns
V
CC
=
4.5V
500
ns
V
CC
=
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
V
IL
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
20
A
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
V
OL
Maximum LOW Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
20
A
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
5.2 mA
6.0V
0.2
0.26
0.33
0.4
V
I
IN
Maximum Input
V
IN
=
V
CC
or GND
6.0V
0.1
1.0
1.0
A
Current
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
6.0V
8.0
80
160
A
Supply Current
I
OUT
=
0
A
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4
MM
74HC259
AC Electrical Characteristics
(V
CC
=
5.0V, T
A
=
25
C, t
r
=
t
f
=
6 ns, C
L
=
15 pF unless otherwise specified.)
AC Electrical Characteristics
t
r
=
t
f
=
6 ns, C
L
=
50 pF, V
CC
=
2.0V 6.0V
Note 5: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
s V
CC
sf
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
t
PHL
, t
PLH
Maximum Propagation Delay
18
32
ns
Data to Output
t
PHL
, t
PLH
Maximum Propagation Delay
20
38
ns
Select to Output
t
PHL
, t
PLH
Maximum Propagation Delay
20
35
ns
Enable to Output
t
PHL
Maximum Propagation Delay
17
27
ns
Clear to Output
t
W
Minimum Enable Pulse Width
10
16
ns
t
W
Minimum Clear Pulse Width
10
16
ns
t
r
, t
f
Maximum Input Rise and Fall Time
500
ns
t
s
Minimum Setup Time Select or
15
20
ns
Data to Enable
t
H
Minimum Hold Time Data or
-
2
0
ns
Address to Enable
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation Delay
2.0V
60
180
225
250
ns
Data to Output
4.5V
19
37
46
52
ns
6.0V
17
32
40
45
ns
t
PHL
, t
PLH
Maximum Propagation Delay
2.0V
72
220
275
310
ns
Select to Output
4.5V
21
43
54
60
ns
6.0V
18
37
46
52
ns
t
PHL
, t
PLH
Maximum Propagation Delay
2.0V
65
200
250
280
ns
Enable to Output
4.5V
27
40
50
58
ns
6.0V
23
35
44
50
ns
t
PHL
Maximum Propagation Delay
2.0V
50
150
190
210
ns
Clear to Output
4.5V
18
31
39
44
ns
6.0V
16
26
32
37
ns
t
W
Minimum Pulse Width
2.0V
80
100
120
ns
Clear or Enable
4.5V
16
20
24
ns
6.0V
14
18
20
ns
t
s
Minimum Setup Time Address
2.0V
100
125
150
ns
or Data to Enable
4.5V
20
25
28
ns
6.0V
15
19
25
ns
t
H
Minimum Hold Time Address
2.0V
-
10
0
0
0
ns
or Data to Enable
4.5V
-
2
0
0
0
ns
6.0V
-
2
0
0
0
ns
t
TLH
, t
THL
Maximum Output Rise
2.0V
30
75
95
110
ns
and Fall Time
4.5V
8
15
19
22
ns
6.0V
7
13
16
19
ns
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
Power Dissipation
(per package)
80
pF
Capacitance (Note 5)
5
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MM74HC259
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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