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Электронный компонент: MM74HC4020N

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2003 Fairchild Semiconductor Corporation
DS005216
www.fairchildsemi.com
February 1984
Revised December 2003
MM74HC4020
MM74HC4040 14-St
age Binar
y

Count
er
12
-St
a
ge
Bi
nary Count
er
MM74HC4020 MM74HC4040
14-Stage Binary Counter 12-Stage Binary Counter
General Description
The MM74HC4020, MM74HC4040, are high speed binary
ripple carry counters. These counters are implemented uti-
lizing advanced silicon-gate CMOS technology to achieve
speed performance similar to LS-TTL logic while retaining
the low power and high noise immunity of CMOS.
The MM74HC4020 is a 14 stage counter and the
MM74HC4040 is a 12-stage counter. Both devices are
incremented on the falling edge (negative transition) of the
input clock, and all their outputs are reset to a low level by
applying a logical high on their reset input.
These devices are pin equivalent to the CD4020 and
CD4040 respectively. All inputs are protected from damage
due to static discharge by protection diodes to V
CC
and
ground.
Features
s
Typical propagation delay: 16 ns
s
Wide operating voltage range: 26V
s
Low input current: 1
A maximum
s
Low quiescent current: 80
A maximum (74HC Series)
s
Output drive capability: 10 LS-TTL loads
Ordering Code:
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
MM74HC4020
MM74HC4040
Order Number
Package Number
Package Description
MM74HC4020M
(Note 1)
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC4020SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4020N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC4040M
(Note 1)
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC4040SJ
(Note 1)
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4040MTC
(Note 1)
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4040N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
MM
74
H
C
40
20

M
M
74HC4040
Logic Diagrams
MM74HC4020
MM74HC4040
3
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MM74HC4020

MM74HC4040
Absolute Maximum Ratings
(Note 2)
(Note 3)
Recommended Operating
Conditions
Note 2: Maximum Ratings are those values beyond which damage to the
device may occur.
Note 3: Unless otherwise specified all voltages are referenced to ground.
Note 4: Power Dissipation temperature derating -- plastic "N" package:
-
12 mW/
C from 65
C to 85
C.
DC Electrical Characteristics
(Note 5)
Note 5: For a power supply of 5V
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
CD
)
20 mA
DC Output Current, per pin (I
OUT
)
25 mA
DC V
CC
or GND Current, per pin (I
CC
)
50 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 4)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
0
V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
-
40
+
85
C
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
1000
ns
V
CC
=
4.5V
500
ns
V
CC
=
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level Input
2.0V
1.5
1.5
1.5
V
Voltage
4.5V
3.15
3.15
3.15
6.0V
4.2
4.2
4.2
V
IL
Maximum LOW Level Input
2.0V
0.5
0.5
0.5
V
Voltage 4.5V
1.35
1.35
1.35
6.0V
1.8
1.8
1.8
V
OH
Minimum HIGH Level Output
V
IN
=
V
IH
or V
IL
V
Voltage
|I
OUT
|
20
A
2.0V
2.0
1.9
1.9
1.9
4.5V
4.5
4.4
4.4
4.4
6.0V
6.0
5.9
5.9
5.9
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
4.2
3.98
3.84
3.7
|I
OUT
|
5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
OL
Maximum LOW Level Output
V
IN
=
V
IH
or V
IL
V
Voltage
|I
OUT
|
20
A
2.0V
0
0.1
0.1
0.1
4.5V
0
0.1
0.1
0.1
6.0V
0
0.1
0.1
0.1
V
IN
=
V
IH
or V
IL
|I
OUT
|
4.0 mA
4.5V
0.2
.26
0.33
0.4
|I
OUT
|
5.2 mA
6.0V
0.2
.26
0.33
0.4
I
IN
Maximum Input Current
V
IN
=
V
CC
or GND
6.0V
0.1
1.0
1.0
A
I
CC
Maximum Quiescent Supply
V
IN
=
V
CC
or GND
6.0V
8.0
80
160
A
Current
I
OUT
=
0
A
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4
MM
74
H
C
40
20

M
M
74HC4040
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Note 6: Typical Propagation delay time to any output can be calculated using: t
P
=
17
+
12(N1) ns; where N is the number of the output, Q
W
, at V
CC
=
5V.
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Note 7: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
f
MAX
Maximum Operating Frequency
50
30
MHz
t
PHL
, t
PLH
Maximum Propagation
(Note 6)
17
35
ns
Delay Clock to Q
t
PHL
Maximum Propagation
16
40
ns
Delay Reset to any Q
t
REM
Minimum Reset
10
20
ns
Removal Time
t
W
Minimum Pulse Width
10
16
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
2.0V
10
6
5
4
MHz
Frequency
4.5V
40
30
24
20
6.0V
50
35
28
24
t
PHL
, t
PLH
Maximum Propagation
2.0V
80
210
265
313
ns
Delay Clock to Q
1
4.5V
21
42
53
63
6.0V
18
36
45
53
t
PHL,
t
PLH
Maximum Propagation
2.0V
80
125
156
188
ns
Delay Between Stages
4.5V
18
25
31
38
from Q
n
to Q
n
+
1
6.0V
15
21
26
31
t
PHL
Maximum Propagation
2.0V
72
240
302
358
ns
Delay Reset to any Q
4.5V
24
48
60
72
(4020 and 4040)
6.0V
20
41
51
61
t
REM
Minimum Reset
2.0V
100
126
149
ns
Removal Time
4.5V
20
25
50
6.0V
16
21
25
t
W
Minimum Pulse Width
2.0V
90
100
120
ns
4.5V
16
20
24
6.0V
14
18
20
t
TLH
, t
THL
Maximum
2.0V
30
75
95
110
ns
Output Rise
4.5V
10
15
19
22
and Fall Time
6.0V
9
13
16
19
t
r
, t
f
Maximum Input Rise and
1000
1000
1000
ns
Fall Time
500
500
500
400
400
400
C
PD
Power Dissipation
(per package)
55
pF
Capacitance (Note 7)
C
IN
Maximum Input
5
10
10
10
pF
Capacitance
5
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MM74HC4020

MM74HC4040
Timing Diagram