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Электронный компонент: MM74HCT245N

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February 1984
Revised February 1999
MM74HCT245 Octal

3-
ST
A
T
E T
r
anscei
ver
1999 Fairchild Semiconductor Corporation
DS005366.prf
www.fairchildsemi.com
MM74HCT245
Octal 3-STATE Transceiver
General Description
The MM74HCT245 3-STATE bi-directional buffer utilizes
advanced silicon-gate CMOS technology and is intended
for two-way asynchronous communication between data
buses. It has high drive current outputs which enable high
speed operation even when driving large bus capaci-
tances. This circuit possesses the low power consumption
of CMOS circuitry, yet has speeds comparable to low
power Schottky TTL circuits.
This device is TTL input compatible and can drive up to 15
LS-TTL loads, and all inputs are protected from damage
due to static discharge by diodes to V
CC
and ground.
The MM74HCT245 has one active low enable input (G),
and a direction control (DIR). When the DIR input is HIGH,
data flows from the A inputs to the B outputs. When DIR is
LOW, data flows from B to A.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s
TTL input compatible
s
3-STATE outputs for connection to system busses
s
High output drive current: 6 mA (min)
s
High speed: 16 ns typical propagation delay
s
Low power: 80
A (74HCT Series)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
Order Number
Package Number
Package Description
MM74HCT245WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT245SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT245N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Control
Operation
Inputs
G
DIR
245
L
L
B data to A bus
L
H
A data to B bus
H
X
isolation
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2
MM
74HCT245
Logic Diagram
3
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MM74HCT245
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
-
12 mW/
C from 65
C to 85
C.
DC Electrical Characteristics
(V
CC
=
5V
10%, unless otherwise specified.)
Note 4: Measured per input. All other inputs at V
CC
or ground.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
20 mA
DC Output Current,
35 mA
DC V
CC
or GND Current, per pin (I
CC
)
70 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min
Max
Units
Supply Voltage (V
CC
)
4.5
5.5
V
DC Input or Output Voltage
(V
IN
, V
OUT
)
0
V
CC
V
Operating Temperature Range (T
A
)
-
40
+
85
C
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Symbol
Parameter
Conditions
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0
2.0
2.0
V
Input Voltage
V
IL
Maximum LOW Level
0.8
0.8
0.8
V
Input Voltage
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
=
20
A
V
CC
V
CC
-
0.1
V
CC
-
0.1
V
CC
-
0.1
V
|I
OUT
|
=
6.0 mA, V
CC
=
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
=
7.2 mA, V
CC
=
5.5V
5.2
4.98
4.84
4.7
V
V
OL
Maximum LOW Level
V
IN
=
V
IH
or V
IL
Voltage
|I
OUT
|
=
20
A
0
0.1
0.1
0.1
V
|I
OUT
|
=
6.0 mA, V
CC
=
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
=
7.2 mA, V
CC
=
5.5V
0.2
0.26
0.33
0.4
V
I
IN
Maximum Input
V
IN
=
V
CC
or GND,
0.1
1.0
1.0
A
Current
V
IH
or V
IL
, Pin 1 or 19
I
OZ
Maximum 3-STATE
V
OUT
=
V
CC
or GND
0.5
5.0
10
A
Output Leakage
G
=
V
IH
Current
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
8
80
160
A
Supply Current
I
OUT
=
0
A
V
IN
=
2.4V or 0.5V (Note 4)
0.6
1.0
1.3
1.5
mA
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4
MM
74HCT245
AC Electrical Characteristics
V
CC
=
5.0V, t
r
=
t
f
=
6 ns, T
A
=
25
C (unless otherwise specified)
AC Electrical Characteristics
V
CC
=
5.0V
10%, t
r
=
t
f
=
6 ns (unless otherwise specified)
Note 5: C
PD
determines the no load power consumption, P
D
=
C
PD
V
CC
2 f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
t
PHL
, t
PLH
Maximum Output
C
L
=
45 pF
16
20
ns
Propagation Delay
t
PZL
, t
PZH
Maximum Output
C
L
=
45 pF
29
40
ns
Enable Time
R
L
=
1 k
t
PLZ
, t
PHZ
Maximum Output
C
L
=
5 pF
20
25
ns
Disable Time
R
L
=
1 k
Symbol
Parameter
Conditions
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum Output
C
L
=
50 pF
17
23
29
34
ns
Propagation Delay
C
L
=
150 pF
24
30
38
45
ns
t
PZL
Maximum Output
R
L
=
1 k
31
42
53
63
ns
Enable Time
C
L
=
50 pF
t
PZH
Maximum Output
R
L
=
1 k
23
33
41
49
ns
Enable Time
C
L
=
50 pF
t
PHZ
, t
PLZ
Maximum Output
R
L
=
1 k
21
30
38
45
ns
Disable Time
C
L
=
50 pF
t
THL
, t
TLH
Maximum Output
C
L
=
50 pF
8
12
15
18
ns
Rise and Fall Time
C
IN
Maximum Input
10
15
15
15
pF
Capacitance
C
OUT
Maximum Output/Input
20
25
25
25
pF
Capacitance
C
PD
Power Dissipation
G
=
V
CC
(Note 5)
7
pF
Capacitance
G
=
GND
100
pF
5
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MM74HCT245
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D