June 1997
NDS332P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
________________________________________________________________________________
Asolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
NDS332P
Units
V
DSS
Drain-Source Voltage
-20
V
V
GSS
Gate-Source Voltage - Continuous
8
V
I
D
Drain Current - Continuous
(Note 1a)
-1
A
- Pulsed
-10
P
D
Maximum Power Dissipation
(Note 1a)
0.5
W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
75
C/W
NDS332P Rev. E
-1 A, -20 V, R
DS(ON)
= 0.41
@ V
GS
= -2.7 V
R
DS(ON)
= 0.3
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface Mount
package.
D
S
G
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
1997 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 A
-20
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -16 V, V
GS
= 0 V
-1
A
T
J
= 55C
-10
A
I
GSS
Gate - Body Leakage
Current
V
GS
= 8 V, V
DS
= 0 V
100
nA
I
GSS
Gate - Body Leakage
Current
V
GS
= -8 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 A
-0.4
-0.6
-1
V
T
J
=125C
-0.3
-0.45
-0.8
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -2.7 V, I
D
= -1 A
0.35
0.41
T
J
=125C
0.5
0.74
V
GS
= -4.5 V, I
D
= -1.1 A
0.26
0.3
I
D(ON)
On-State Drain Current
V
GS
= -2.7 V, V
DS
= -5 V
-1.5
A
V
GS
= -4.5 V, V
DS
= -5 V
-2.5
g
F
S
Forward Transconductance
V
DS
= -5 V, I
D
= -1 A
2.2
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
195
pF
C
oss
Output Capacitance
105
pF
C
rss
Reverse Transfer Capacitance
40
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -6 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
8
15
ns
t
r
Turn - On Rise Time
30
45
ns
t
D(off)
Turn - Off Delay Time
25
45
ns
t
f
Turn - Off Fall Time
27
45
ns
Q
g
Total Gate Charge
V
DS
= -5 V, I
D
= -1 A,
V
GS
= -4.5 V
3.7
5
nC
Q
gs
Gate-Source Charge
0.5
nC
Q
gd
Gate-Drain Charge
0.9
nC
NDS332P Rev. E
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Source Current
-0.42
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.42 A
(Note 2)
-0.75
-1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDS332P Rev. E
P
D
(
t
) =
T
J
-
T
A
R
JA
(
t
)
=
T
J
-
T
A
R
JC
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
@
T
J
1 a
1b
NDS332P Rev.E
Figure 1. On-Region Characteristics
.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
.
Typical Electrical Characteristics
Figure 3. On-Resistance Variation
with Temperature
.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
Figure 5. Transfer Characteristics
.
Figure 6. Gate Threshold Variation
with Temperature.
-3
-2.5
-2
-1.5
-1
-0.5
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = -2.7 V
GS
T = 125C
J
25C
-55C
-2
-1.75
-1.5
-1.25
-1
-0.75
-0.5
-1.5
-1.2
-0.9
-0.6
-0.3
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = - 3V
DS
25C
125C
GS
D
T = -55C
J
-50
-25
0
25
50
75
100
125
150
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE (V)
J
I = -250A
D
V = V
DS
GS
V , NORMALIZED
th
-50
-25
0
25
50
75
100
125
150
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
V = -2.7
GS
I = -1A
D
J
R , NORMALIZED
DS(ON)
-3
-2.5
-2
-1.5
-1
-0.5
0
-2.5
-2
-1.5
-1
-0.5
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
-2.5
DS
D
V = -4.5V
GS
-3.5
-2.0
-1.5
-2.7
-3.0
-3
-2.5
-2
-1.5
-1
-0.5
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V =-2.0V
GS
D
-2.7
R , NORMALIZED
DS(ON)
-3.0
-4.5
-3.5
-2.5
NDS332PRev. E
Figure 7. Breakdown Voltage Variation with
Temperature
.
Typical Electrical Characteristics
(continued)
G
D
S
V
DD
R
L
V
V
IN
OUT
V
GS
DUT
R
GEN
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics
.
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
-50
-25
0
2 5
5 0
7 5
1 0 0
1 2 5
1 5 0
0.92
0.96
1
1.04
1.08
1.12
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = -250A
D
BV , NORMALIZED
DSS
J
0
0.2
0.4
0.6
0.8
1
0.0001
0.001
0.01
0.05
0.1
1
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V =0V
GS
SD
S
0.1
0.2
0.5
1
2
5
10
20
20
30
50
100
200
300
500
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
f = 1 MHz
V = 0V
GS
C
oss
C
iss
C
rss
0
1
2
3
4
5
0
1
2
3
4
5
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -1A
D
V = -5V
DS
-10V
-15V
10%
50%
90%
10%
90%
90%
50%
V
IN
V
OUT
o n
off
d(off)
f
r
d(on)
t
t
t
t
t
t
INVERTED
10%
PULSE WIDTH
Figure 8. Body Diode ForwardVoltageVariation with
Source Current and Temperature
.
NDS332PRev. E
Figure 14. Maximum Safe Operating Area
.
Typical Electrical Characteristics
(continued)
Figure 17. Transient Thermal Response Curve.
Note : Characterization performed using the conditions described in note 1b. Transient thermal response will
change depending on the circuit board design.
-3
-2.5
-2
-1.5
-1
-0.5
0
0
1
2
3
4
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55C
J
D
FS
V =- 5V
DS
125C
25C
0.1
0.2
0.5
1
2
5
10
20
50
0.01
0.03
0.1
0.5
1
2
5
10
20
-V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN CURRENT (A)
DS
D
RDS(ON) LIMIT
V = -2.7V
SINGLE PULSE
R = See Note 1b
T = 25C
GS
A
JA
1s
100ms
1ms
10ms
DC
10s
0
0.1
0.2
0.3
0.4
0.6
0.8
1
1.2
1.4
2oz COPPER MOUNTING PAD AREA (in )
-I , STEADY-STATE DRAIN CURRENT (A)
2
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = -2.7V
A
o
GS
D
0
0.1
0.2
0.3
0.4
0
0.2
0.4
0.6
0.8
1
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
A
o
Figue 15. SuperSOT
TM _
3 Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
Figure 13. Transconductance Variation with
Drain Current and Temperature
.
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad Area
.
0.0001
0.001
0.01
0.1
1
10
100
300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
Duty Cycle, D = t /t
1 2
R (t) = r(t) * R
R = See Note 1b
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
PDF 
ZIP