March 1999
FDC6323L
Integrated Load Switch
General Description
Features
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
FDC6323L
Units
V
IN
Input Voltage Range
3 - 8
V
V
ON/OFF
On/Off Voltage Range
1.5 - 8
V
I
L
Load Current @ V
DROP
=0.5V - Continuous
(Note 1)
1.5
A
- Pulsed
(Note 1 & 3)
2.5
P
D
Maximum Power Dissipation
(Note 2a)
0.7
W
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
ESD
Electrostatic Discharge Rating MIL-STD-883D Human Body
Model (100pf/1500Ohm)
6
kV
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 2a)
180
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 2)
60
C/W
FDC6323L Rev.F
These Integrated Load Switches are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance and
provide superior switching performance. These
devices are particularly suited for low voltage high
side load switch application where low conduction loss
and ease of driving are needed.
V
DROP
=0.2V @ V
IN
=5V, I
L
=1A, V
ON/OFF
= 1.5V to 8V
V
DROP
=0.3V @ V
IN
=3.3V, I
L
=1A, V
ON/OFF
= 1.5V to 8V.
High density cell design for extremely low on-resistance.
V
ON/OFF
Zener protection for ESD ruggedness.
>6KV Human Body Model.
SuperSOT
TM
-6 package design using copper lead frame
for superior thermal and electrical capabilities.
S e e A p p l i c a t i o n C i r c u i t
1
5
6
3
2
V i n , R 1
V o u t , C 1
R 2
O N / O FF
R 1 , C 1
Q 2
Q 1
V o u t , C 1
4
IN
O U T
O N / O FF
E Q U I V A L E N T C I R C U I T
V
D R O P
+
-
SuperSOT -6
TM
pin
1
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
1999 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
I
FL
Forward Leakage Current
V
IN
= 8 V, V
ON/OFF
= 0 V
1
A
I
RL
Reverse Leakage Current
V
IN
= -8 V, V
ON/OFF
= 0 V
-1
A
ON CHARACTERISTICS
(Note 3)
V
IN
Input Voltage
3
8
V
V
ON/OFF
On/Off Voltage
1.5
8
V
V
DROP
Conduction Voltage Drop @ 1A
V
IN
= 5 V, V
ON/OFF
= 3.3 V
0.145
0.2
V
V
IN
= 3.3 V, V
ON/OFF
= 3.3 V
0.178
0.3
I
L
Load Current
V
DROP
= 0.2 V, V
IN
= 5 V, V
ON/OFF
= 3.3 V
1
A
V
DROP
= 0.3 V, V
IN
= 3.3 V, V
ON/OFF
= 3.3 V
1
Notes:
1. V
IN
=8V, V
ON/OFF
=8V, V
DROP
=0.5V, T
A
=25
o
C
2. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed
by design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
J A
(
t
)
=
T
J
-
T
A
R
J C
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
@T
J
Typical R
JA
for single device operation using the board layouts shown below on FR-4 PCB in a still air environment:
a. 180
o
C/W when mounted on a 2oz minimum copper pad.
Scale 1 : 1 on letter size paper
3. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%
FDC6323L Rev.F
2a
FDC6323L Rev.F
Typical Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Figure 1. V
DROP
Versus I
L
at V
IN
=5V.
Figure 2. V
DROP
Versus I
L
at V
IN
=3.3V.
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
I (A)
V (V)
DROP
L
V = 5V
V = 1.5 - 8V
PW =300us, D
2%
ON/OFF
IN
T = 125C
J
T = 25C
J
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
I (A)
V (V)
V = 3.3V
V = 1.5 - 8V
PW =300us, D
2%
L
DROP
ON/OFF
IN
T = 125C
J
T = 25C
J
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
V (V)
V (V)
IN
I = 1A
V = 1.5 - 8V
PW =300us, D
2%
ON/OFF
L
DROP
T = 125C
J
T = 25C
J
Figure 3. V
DROP
Versus V
IN
at I
L
=1A.
0
1
2
3
4
5
0.1
0.15
0.2
0.25
0.3
0.35
0.4
I ,(A)
R ,(Ohm)
(ON)
L
T = 125C
J
T = 25C
J
I = 1A
V = 3.3V
PW =300us, D
2%
IN
L
Figure 4. R
(ON)
Versus I
L
at V
IN
=3.3V.
Figure 5. On Resistance Variation with
Input Voltage.
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
V ,(V)
R ,(Ohm)
IN
I = 1A
V = 1.5 - 8V
PW =300us, D
2%
ON/OFF
L
(ON)
T = 125C
J
T = 25C
J
FDC6323L Rev.F
Typical Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
0
2
4
6
8
10
0
10
20
30
40
50
R2 (K )
Time ( s)
td(on)
tr
td(off)
tf
Vin = 5V
IL = 1A
Von/off = 3.3V
R1 = 20K
Ci = 10 F
Co = 1 F
0
2
4
6
8
10
0
10
20
30
40
50
R2 (K )
Time ( s)
td(on)
tr
td(off)
tf
Vin = 3.3V
IL = 1A
Von/off = 3.3V
R1 = 20K
Ci = 10 F
Co = 1 F
Figure 6. Switching Variation with
R2 at Vin=5V and R1=20KOhm.
Figure 7. Switching Variation with R2
at Vin=3.3V and R1=20KOhm.
0
2
4
6
8
10
0
10
20
30
40
50
R2 (K )
Time ( s)
td(on)
tr
td(off)
tf
Vin = 2.5V
IL = 1A
Von/off = 3.3V
R1 = 20K
Ci = 10 F
Co = 1 F
0
2
4
6
8
10
0
50
100
150
200
250
R2 (K )
% of Current Overshoot
Vin = 5V
3.3V
2.5V
IL = 1A
Von/off = 3.3V
R1 = 20K
Ci = 10 F
Co = 1 F
Figure 8. Switching Variation with R2
at Vin=2.5V and R1=20KOhm.
Figure 9. % of Current Overshoot
Variation with Vin and R2.
0
20
40
60
80
100
0
100
200
300
400
500
R2 (K )
Vdrop (mV)
Vin = 2.5V
3.3V
5V
IL = 1A
Von/off = 3.3V
R1 = 20K
Ci = 10 F
Co = 1 F
Figure 10. Vdrop Variation with Vin and R2.
Figure 11. Switching Waveforms.
10%
50%
90%
10%
90%
90%
50%
V
IN
V
OUT
o n
off
d (off)
f
r
d (on)
t
t
t
t
t
t
INVERTED
10%
PULSE W IDTH
FDC6323L Rev.F
Typical Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
0.1
0.2
0.5
1
2
5
10
20
30
0.01
0.03
0.1
0.3
1
3
10
V (V)
I , DRAIN CURRENT (A)
DROP
L
100ms
10ms
1s
1ms
R(ON) LIMIT
DC
100us
V = 5V
SINGLE PULSE
R = See Note 2a
T = 25C
IN
A
JA
Figure 12. Safe Operating Area.
0.00001
0.0001
0.001
0.01
0.1
1
10
100
300
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
1
2
R (t) = r(t) * R
R = See Note 2a
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
r(t), NORMALIZED EFFECTIVE
Figure 13. Transient Thermal Response Curve.
Note: Thermal characterization performed on the conditions described in Note 2a.
Transient thermal response will change depends on the circuit board design.
FDC6323L Load Switch Application
General Description
This device is particularly suited for compact
computer peripheral switching applications
where 8V input and 1A output current capability
are needed. This load switch integrates a small
N-Channel Power MOSFET (Q1) which drives a
large P-Channel Power MOSFET (Q2) in one
tiny SuperSOT
TM
-6 package.
A load switch is usually configured for high side
switching so that the load can be isolated from
the active power source. A P-Channel Power
MOSFET, because it does not require its drive
voltage above the input voltage, is usually more
cost effective than using an N-Channel device in
this particular application. A large P-Channel
Power MOSFET minimizes voltage drop. By
using a small N-Channel device the driving
stage is simplified.
Component Values
R1
Typical 10k - 1M
R2
Typical 0 - 100k
(optional)
C1
Typical 1000pF
(optional)
Design Notes
R1 is needed to turn off Q2.
R2 can be used to soft start the switch in case the output capacitance Co is small.
R2 should be at least 10 times smaller than R1 to guarantee Q1 turns on.
By using R1 and R2 a certain amount of current is lost from the input. This bias current loss is given by
the equation
when the switch is ON. I
BIAS_LOSS
can be minimized by selecting a large
I
BIAS_LOSS
=
Vin
R 1
+
R2
value for R1.
R2 and C
RSS
of Q2 make ramp for slow turn on. If excessive overshoot current occurs due to fast turn on,
additional capacitance C1 can be added externally to slow down the turn on.
FDC6323L Rev.F
APPLICATION CIRCUIT
I N
O U T
O N / O FF
R1
R2
C1
LOAD
Co
Q2
Q1
1998 Fairchild Semiconductor Corporation
SSOT-6 Unit Orientation
Conductive Embossed
Carrier Tape
F63TNR
Label
Customize Label
Antistatic Cover Tape
SSOT-6 Packaging
Configuration: Figure 1.0
Components
Leader Tape
390mm minimum
Trailer Tape
160mm minimum
SSOT-6 Tape Leader
Trailer
Configuration: Figure 2.0
Cover Tape
Carrier
Pin 1
Tape
Note/Comments
Packaging Option
SSOT-6 Packaging Information
Standard
(no flow code)
D87Z
Packaging type
Reel Size
TNR
7" Dia
TNR
13"
Qty per Reel/Tube/Bag
3,000
10,000
Box Dimension (mm)
184x187x47
343x343x64
Max qty per Box
9,000
20,000
Weight per unit (gm)
0.0158
0.0158
Weight per Reel (kg)
0.1440
0.4700
184mm x 184mm x 47mm
Pizza Box for Standard Option
F63TNR
Label
F63TNR Label
F63TNR Label sample
343mm x 342mm x 64mm
Intermediate box for D87Z Option
631
631
631
631
LOT: CBVK741B019
FSID: FDC633N
D/C1: D9842
QTY1:
SPEC REV: QARV:
SPEC:
QTY: 3000
D/C2:
QTY2:
CPN:
(F63TNR)2
F63TNR
Label
SuperSOT
TM
-6 Tape and Reel Data and Package Dimensions
December 1998, Rev. B
P1
A0
D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
8mm
7" Dia
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 0.429
7.9 10.9
8mm
13" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 0.429
7.9 10.9
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SSOT-6 Embossed Carrier Tape
Configuration: Figure 3.0
SSOT-6 Reel Configuration: Figure 4.0
Dimensions are in millimeter
Pkg type
A0
B0
W
D0
D1
E1
E2
F
P1
P0
K0
T
Wc
Tc
SSOT-6
(8mm)
3.23
+/-0.10
3.18
+/-0.10
8.0
+/-0.3
1.55
+/-0.05
1.00
+/-0.125
1.75
+/-0.10
6.25
min
3.50
+/-0.05
4.0
+/-0.1
4.0
+/-0.1
1.37
+/-0.10
0.255
+/-0.150
5.2
+/-0.3
0.06
+/-0.02
SuperSOT
TM
-6 Tape and Reel Data and Package Dimensions, continued
December 1998, Rev. B
1998 Fairchild Semiconductor Corporation
SuperSOT
TM
-6 (FS PKG Code 31, 33)
1 : 1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0158
SuperSOT
TM
-6 Tape and Reel Data and Package Dimensions, continued
September 1998, Rev. A
TRADEMARKS
ACExTM
CoolFETTM
CROSSVOLTTM
E
2
CMOS
TM
FACTTM
FACT Quiet SeriesTM
FAST
FASTrTM
GTOTM
HiSeCTM
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
ISOPLANARTM
MICROWIRETM
POPTM
PowerTrenchTM
QSTM
Quiet SeriesTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
TinyLogicTM
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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