July 1996
NDS8958
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
________________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
N-Channel
P-Channel
Units
V
DSS
Drain-Source Voltage
30
-30
V
V
GSS
Gate-Source Voltage
20
-20
V
I
D
Drain Current - Continuous
(Note 1a)
5.3
-4
A
- Pulsed
20
-15
P
D
Power Dissipation for Dual Operation
2
W
Power Dissipation for Single Operation
(Note 1a)
1.6
(Note 1b)
1
(Note 1c)
0.9
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
40
C/W
NDS8958 Rev. C
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
N-Channel 5.3A, 30V, R
DS(ON)
=0.035
@ V
GS
=10V.
P-Channel -4.0A, -30V, R
DS(ON)
=0.065
@ V
GS
=-10V.
High density cell design or extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
1
5
6
7
8
4
3
2
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
N-Ch
30
V
V
GS
= 0 V, I
D
= -250 A
P-Ch
-30
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
N-Ch
1
A
T
J
= 55C
10
A
V
DS
= -24 V, V
GS
= 0 V
P-Ch
-1
A
T
J
= 55C
-10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
All
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
All
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
N-Ch
1
1.6
2.8
V
T
J
= 125C
0.7
1.2
2.2
V
DS
= V
GS
, I
D
= -250 A
P-Ch
-1
-1.6
-2.8
T
J
= 125C
-0.7
-1.2
-2.2
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 5.3 A
N-Ch
0.033
0.035
T
J
= 125C
0.046
0.063
V
GS
= 4.5 V, I
D
= 4.4 A
0.046
0.05
V
GS
= -10 V, I
D
= -4.0 A
P-Ch
0.052
0.065
T
J
= 125C
0.075
0.13
V
GS
= -4.5 V, I
D
= -3.3 A
0.085
0.1
I
D(on)
On-State Drain Current
V
GS
= 10 V, V
DS
= 5 V
N-Ch
20
A
V
GS
= -10 V, V
DS
= -5 V
P-Ch
-15
g
FS
Forward Transconductance
V
DS
= 10 V, I
D
= 5.3 A
N-Ch
10.5
S
V
DS
= -10 V, I
D
= -4.0 A
P-Ch
7
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
N-Channel
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
P-Channel
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
N-Ch
720
pF
P-Ch
690
C
oss
Output Capacitance
N-Ch
370
pF
P-Ch
430
C
rss
Reverse Transfer Capacitance
N-Ch
250
pF
P-Ch
160
NDS8958 Rev. C
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
N-Channel
V
DD
= 10 V, I
D
= 1 A,
V
GEN
= 10 V, R
GEN
= 6
P-Channel
V
DD
= -10 V, I
D
= -1 A,
V
GEN
= -10 V, R
GEN
= 6
N-Ch
12
20
ns
P-Ch
9
20
t
r
Turn - On Rise Time
N-Ch
13
30
ns
P-Ch
20
25
t
D(off)
Turn - Off Delay Time
N-Ch
29
50
ns
P-Ch
40
50
t
f
Turn - Off Fall Time
N-Ch
10
20
ns
P-Ch
19
40
Q
g
Total Gate Charge
N-Channel
V
DS
= 10 V,
I
D
= 5.3 A, V
GS
= 10 V
P-Channel
V
DS
= -10 V,
I
D
= -4.0 A, V
GS
= -10 V
N-Ch
19
30
nC
P-Ch
21
30
Q
gs
Gate-Source Charge
N-Ch
2.2
P-Ch
3.1
Q
gd
Gate-Drain Charge
N-Ch
5.5
P-Ch
5.1
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
N-Ch
1.3
A
P-Ch
-1.3
V
SD
Drain-Source Diode Forward
Voltage
V
GS
= 0 V, I
S
= 1.3 A
(Note 2)
N-Ch
0.9
1.2
V
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
P-Ch
-0.85
-1.2
t
rr
Reverse Recovery Time
V
GS
= 0 V, I
F
= 1.3 A, dI
F
/dt = 100 A/s
N-Ch
100
ns
V
GS
= 0 V, I
F
= -1.3 A, dI
F
/dt = 100 A/s
P-Ch
100
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
JA
(
t
)
=
T
J
-
T
A
R
JC
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
T
J
Typical R
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 0.5 in
2
pad of 2oz copper.
b. 125
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
c. 135
o
C/W when mounted on a 0.003 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDS8958 Rev. C
1a
1b
1c
NDS8958 Rev. C
Typical Electrical Characteristics: N-Channel
Figure 1. N-Channel On-Region Characteristic.
Figure 2. N-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
Figure 3. N-Channel On-Resistance Variation with
Temperature.
Figure 4. N-Channel On-Resistance Variation with
Drain Current and Temperature.
Figure 5. N-Channel Transfer Characteristic.
Figure 6. N-Channel Gate Threshold Variation
with Temperature.
0
0.5
1
1.5
2
2.5
3
0
5
1 0
1 5
2 0
2 5
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
DS
D
V =10V
GS
6.0
4.0
3.5
3.0
5.0
4.5
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V =10V
G S
I = 5.3A
D
R , NORMALIZED
DS(ON)
-50
-25
0
25
50
75
100
125
150
0.6
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE
J
I = 250A
D
V = V
DS
GS
V , NORMALIZED
th
0
5
10
15
20
25
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
R , NORMALIZED
DS(ON)
V = 3.0V
GS
D
4.0
1 0
6.0
4.5
5.0
3.5
0
5
10
15
20
25
0.5
0.75
1
1.25
1.5
1.75
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
V = 10V
GS
T = 125C
J
25C
-55C
R , NORMALIZED
DS(ON)
1
2
3
4
5
6
0
5
1 0
1 5
2 0
2 5
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = 10V
DS
GS
D
T = -55C
J
25C
125C
NDS8958 Rev. C
Figure 7. N-Channel Breakdown Voltage Variation
with Temperature.
Figure 8. N-Channel Body Diode Forward Voltage
Variation with Current and Temperature
.
Figure 9. N-Channel Capacitance Characteristics.
Figure 10. N-Channel Gate Charge Characteristics.
Typical Electrical Characteristics: N-Channel
(continued)
Figure 11. N-Channel Transconductance Variation
with Drain Current and Temperature.
-50
-25
0
25
50
75
100
125
150
0.9
0.95
1
1.05
1.1
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = 250A
D
BV , NORMALIZED
DSS
J
0.2
0.4
0.6
0.8
1
1.2
1.4
0.001
0.01
0.1
1
1 0
2 5
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V =0V
GS
SD
S
0
5
10
15
20
25
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 5.3A
D
V = 5V
DS
10V
20V
0.1
0.2
0.5
1
2
5
1 0
2 0
3 0
1 0 0
2 0 0
5 0 0
1 0 0 0
1 5 0 0
2 0 0 0
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0V
GS
C oss
C rss
0
5
1 0
1 5
2 0
2 5
0
4
8
1 2
1 6
2 0
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55C
J
D
FS
V = 10V
DS
125C
25C
NDS8958 Rev. C
Typical Electrical Characteristics: P-Channel (continued)
Figure 12. P-Channel On-Region Characteristics.
Figure 13. P-Channel On-Resistance Variation
with Gate Voltage and Drain Current.
Figure 14. P-Channel On-Resistance Variation with
Temperature.
Figure 15. P-Channel On-Resistance Variation with
Drain Current and Temperature.
Figure 16. P-Channel Transfer Characteristics.
Figure 17. P-Channel Gate Threshold Variation
with Temperature.
-4
-3
-2
-1
0
-20
-15
-10
-5
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
V = -10V
GS
DS
D
-4.0
-6.0
-5.0
-3.5
-3.0
-4.5
-50
-25
0
2 5
5 0
7 5
1 0 0
1 2 5
1 5 0
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V = -10V
GS
I = -4.0A
D
R , NORMALIZED
DS(ON)
-50
-25
0
25
50
75
100
125
150
0.6
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE
I = -250A
D
V = V
DS
GS
J
V , NORMALIZED
th
-20
-16
-12
-8
-4
0
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = -3.5V
GS
-10
-5.0
-6.0
- 4.0
-4.5
-6
-5
-4
-3
-2
-1
-20
-15
-10
-5
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = -10V
DS
GS
D
T = -55C
J
25C
125C
-20
-16
-12
-8
-4
0
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = -10V
GS
T = 125C
J
25C
-55C
NDS8958 Rev. C
Figure 18. P-Channel Breakdown Voltage
Variation with Temperature.
Figure 19. P-Channel Body Diode Forward Voltage
Variation with Current and Temperature
.
Figure 20. P-Channel Capacitance Characteristics.
Figure 21. P-Channel Gate Charge Characteristic.
Typical Electrical Characteristics: P-Channel
(continued)
Figure 22. P-Channel Transconductance Variation with
Drain Current and Temperature.
-50
-25
0
25
50
75
100
125
150
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = -250A
D
BV , NORMALIZED
DSS
J
0
0.4
0.8
1.2
1.6
2
0.001
0.01
0.1
1
5
1 0
2 0
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0V
GS
SD
S
0
5
1 0
1 5
2 0
2 5
0
2
4
6
8
1 0
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -4.0A
D
V = -5V
DS
-10V
-20V
0.1
0.2
0.5
1
2
5
1 0
3 0
1 0 0
2 0 0
3 0 0
5 0 0
1 0 0 0
2 0 0 0
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0V
GS
C oss
C rss
-20
-16
-12
-8
-4
0
0
3
6
9
1 2
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55C
J
25C
D
FS
V = -10V
DS
125C
NDS8958 Rev. C
Typical Thermal Characteristics:
N & P-Channel
0
0.1
0.2
0.3
0.4
0.5
2
3
4
5
6
2oz COPPER MOUNTING PAD AREA (in )
I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1 b
1a
4.5"x5" FR-4 Board
T = 2 5 C
Still Air
V = 1 0 V
A
o
G S
D
Figure 24. N-Ch Maximum Steady-State Drain
Current versus Copper Mounting Pad
Area.
0
0.1
0.2
0.3
0.4
0.5
2
2.5
3
3.5
4
4.5
2oz COPPER MOUNTING PAD AREA (in )
-I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1 b
1a
4.5"x5" FR-4 Board
T = 2 5 C
Still Air
V = -10V
A
o
G S
D
Figure 25. P-Ch Maximum Steady- State
Drain Current versus Copper Mounting
Pad Area.
0.1
0.2
0.5
1
2
5
1 0
3 0
5 0
0.01
0.05
0.1
0.5
1
5
1 0
2 0
5 0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
1s
100ms
10s
10ms
RDS(ON) LIMIT
1ms
DC
100us
V = 10V
SINGLE PULSE
R = See Note 1c
T = 25C
GS
A
J A
Figure 26. N-Channel Maximum Safe Operating
Area.
0.1
0.2
0.5
1
2
5
1 0
3 0
5 0
0.01
0.05
0.1
0.5
1
5
1 0
2 0
5 0
- V , DRAIN-SOURCE CURRENT (V)
-
I
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
DS
D
10ms
100ms
10s
1s
DC
100us
1ms
RDS(ON) LIMIT
V = -10V
SINGLE PULSE
R = See Note 1c
T = 25C
GS
A
J A
Figure 27. P-Channel Maximum Safe Operating
Area.
0
0.2
0.4
0.6
0.8
1
0.5
1
1.5
2
2.5
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1c
1 b
4.5"x5" FR-4 Board
T = 2 5 C
Still Air
A
o
Power for Single Operation
Total Power for Dual Operation
1a
Figure 23. SO-8 Dual Package Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
NDS8958 Rev. C
G
D
S
V
DD
R
L
V
V
IN
OUT
V
GS
DUT
R
GEN
1 0 %
5 0 %
9 0 %
1 0 %
9 0 %
9 0 %
5 0 %
V
IN
V
O U T
o n
off
d(off)
f
r
d(on)
t
t
t
t
t
t
1 0 %
PULSE WIDTH
Figure 29. N or P-Channel Switching Test Circuit
.
Figure 30. N or P-Channel Switching Waveforms
.
Typical Thermal Characteristics:
N & P-Channel
0 .0001
0 .001
0 .0 1
0 .1
1
1 0
1 0 0
3 0 0
0 .0 0 1
0 .0 0 2
0 .0 0 5
0 .0 1
0 .0 2
0 .0 5
0 .1
0 .2
0 .5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
1
2
R (t) = r(t) * R
R = See Note 1c
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
Figure 28. Transient Thermal Response Curve
.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
SOIC(8lds) Packaging
Configuration: Figure 1.0
Components
Leader Tape
1680mm minimum or
210 empty pockets
Trailer Tape
640mm minimum or
80 empty pockets
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Cover Tape
Carrier Tape
Note/Comments
Packaging Option
SOIC (8lds) Packaging Information
Standard
(no flow code)
L86Z
F011
Packaging type
Reel Size
TNR
13" Dia
Rail/Tube
-
TNR
13" Dia
Qty per Reel/Tube/Bag
2,500
95
4,000
Box Dimension (mm)
343x64x343
530x130x83
343x64x343
Max qty per Box
5,000
30,000
8,000
D84Z
TNR
7" Dia
500
184x187x47
1,000
Weight per unit (gm)
0.0774
0.0774
0.0774
0.0774
Weight per Reel (kg)
0.6060
-
0.9696
0.1182
F63TN Label
ESD Label
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
F63TNLabel
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1:
SPEC REV:
SPEC:
QTY: 2500
D/C2:
QTY2:
CPN:
N/F: F (F63TNR)3
F852
NDS
9959
SOIC-8 Unit Orientation
F
85
2
NDS
99
59
Pin 1
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Antistatic Cover Tape
ESD Label
EL ECT RO ST AT IC
SEN SIT IVE DEVI CES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC
EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE
PT NUMB ER
PEEL STREN GTH MIN ___ __ ____ __ ___gms
MAX ___ ___ ___ ___ _ gms
Customized
Label
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
F
85
2
NDS
99
59
F
85
2
NDS
99
59
F
85
2
NDS
99
59
SO-8 Tape and Reel Data and Package Dimensions
July 1999, Rev. B
1998 Fairchild Semiconductor Corporation
Dimensions are in millimeter
Pkg type
A0
B0
W
D0
D1
E1
E2
F
P1
P0
K0
T
Wc
Tc
SOIC(8lds)
(12mm)
6.50
+/-0.10
5.30
+/-0.10
12.0
+/-0.3
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
5.50
+/-0.05
8.0
+/-0.1
4.0
+/-0.1
2.1
+/-0.10
0.450
+/-
0.150
9.2
+/-0.3
0.06
+/-0.02
P1
A0
D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
12mm
7" Dia
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
12mm
13" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
7.00
178
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
SOIC(8lds) Reel Configuration: Figure 4.0
SO-8 Tape and Reel Data and Package Dimensions, continued
July 1999, Rev. B
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
SO-8 Tape and Reel Data and Package Dimensions, continued
September 1998, Rev. A
9
TRADEMARKS
ACExTM
CoolFETTM
CROSSVOLTTM
E
2
CMOS
TM
FACTTM
FACT Quiet SeriesTM
FAST
FASTrTM
GTOTM
HiSeCTM
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
SyncFETTM
TinyLogicTM
UHCTM
VCXTM
ISOPLANARTM
MICROWIRETM
POPTM
PowerTrench
QFETTM
QSTM
Quiet SeriesTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
Rev. D
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