July 1996
NDT455N
N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
________________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
NDT455N
Units
V
DSS
Drain-Source Voltage
30
V
V
GSS
Gate-Source Voltage
20
V
I
D
Drain Current
- Continuous
(Note 1a)
11.5
A
- Pulsed
40
P
D
Maximum Power Dissipation
(Note 1a)
3
W
(Note 1b)
1.3
(Note 1c)
1.1
T
J
,T
STG
Operating and Storage Temperature Range
-65 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
42
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
12
C/W
NDT455N Rev.F
11.5 A, 30 V. R
DS(ON)
= 0.015
@ V
GS
= 10 V
R
DS(ON)
= 0.02
@ V
GS
= 4.5 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process
is especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as DC
motor control and DC/DC conversion where fast switching, low
in-line power loss, and resistance to transients are needed.
D
D
S
G
D
S
G
1997 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
30
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
A
T
J
= 55C
10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
1
1.5
3
V
T
J
= 125C
0.7
0.9
2.2
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 11.5 A
0.013
0.015
T
J
= 125C
0.019
0.03
V
GS
= 4.5 V, I
D
= 10 A
0.018
0.02
I
D(on)
On-State Drain Current
V
GS
= 10 V , V
DS
= 5 V
30
A
V
GS
= 4.5 V, V
DS
= 5 V
15
g
FS
Forward Transconductance
V
GS
= 10 V, I
D
= 11.5 A
26
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= 15, V
GS
= 0 V,
f = 1.0 MHz
1220
pF
C
oss
Output Capacitance
715
pF
C
rss
Reverse Transfer Capacitance
280
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= 15 V, I
D
= 1 A,
V
GEN
= 10 V, R
GEN
= 6
11
20
ns
t
r
Turn - On Rise Time
16
30
ns
t
D(off)
Turn - Off Delay Time
48
80
ns
t
f
Turn - Off Fall Time
40
70
ns
Q
g
Total Gate Charge
V
DS
= 10 V,
I
D
= 11.5 A, V
GS
= 10 V
43
61
nC
Q
gs
Gate-Source Charge
4
nC
Q
gd
Gate-Drain Charge
11
nC
NDT455N Rev.F
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
2.5
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 2.5 A
(Note 2)
0.845
1.2
V
t
rr
Reverse Recovery Time
V
GS
= 0 V, I
F
= 2.5 A dI
F
/dt = 100 A/s
140
ns
Notes:
1.
R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the
P
D
(
t
) =
T
J
-
T
A
R
JA
(
t
)
=
T
J
-
T
A
R
JC
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
@
T
J
solder mounting surface of the drain pins. R
JC
is guaranteed by design while R
CA
is defined by users. For general reference: Applications on 4.5"x5" FR-4 PCB under still air environment, typical
R
JA
is found to be:
a. 42
o
C/W with 1 in
2
of 2 oz copper mounting pad.
b. 95
o
C/W with 0.066 in
2
of 2 oz copper mounting pad.
c. 110
o
C/W with 0.0123 in
2
of 2 oz copper mounting pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDT455N Rev.F
1a
1b
1c
NDT455N Rev.F
0
0.5
1
1.5
2
2.5
3
0
8
16
24
32
40
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
3.5
3.0
V =10V
GS
DS
D
5.0
4.5
6.0
4.0
-50
-25
0
2 5
50
7 5
1 0 0
1 2 5
1 5 0
0.5
0.75
1
1.25
1.5
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 10V
GS
I = 11.5A
D
R , NORMALIZED
DS(ON)
-50
-25
0
25
50
75
100
125
150
0.4
0.6
0.8
1
1.2
1.4
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE
J
V , NORMALIZED
GS(th)
I = 250A
D
V = V
GS
DS
0
8
16
24
32
40
0.5
1
1.5
2
2.5
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
R , NORMALIZED
V = 3.5V
GS
D
DS(on)
4.5
6.0
10
4.0
5.0
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
0.8
1.6
2.4
3.2
4
0
10
20
30
40
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25C
125C
V = 10V
DS
GS
D
T = -55C
J
0
8
16
24
32
40
0
0.5
1
1.5
2
2.5
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 10V
GS
T = 125C
J
25C
-55C
D
R , NORMALIZED
DS(on)
NDT455N Rev.F
-50
-25
0
25
50
75
100
125
150
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = 250A
D
BV , NORMALIZED
DSS
J
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0.0001
0.001
0.01
0.1
1
1 0
4 0
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
V = 0V
GS
T = 125C
J
25C
-55C
SD
S
0
10
20
30
40
50
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 11.5A
D
10V
15V
V = 5.V
DS
0.1
0.2
0.5
1
2
5
10
20 30
100
200
300
500
800
1000
2000
4000
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0V
GS
C oss
C rss
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
.
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
Typical Electrical Characteristics
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
G
D
S
V
DD
R
L
V
V
IN
OUT
V
GS
DUT
R
GEN
10%
50%
90%
10%
90%
90%
50%
V
IN
V
OUT
on
off
d(off)
f
r
d(on)
t
t
t
t
t
t
INVERTED
10%
PULSE WIDTH
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