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www.fairchildsemi.com
REV. 1.0.1 12/7/00
Features
Two separate analog receiver channels
Converts ARINC 429 levels to serial data
Built-in TTL compatible complete channel test inputs
TTL and CMOS compatible outputs
Low power dissipation
Internal bandgap
Short circuit protected
Available in 20-Lead ceramic DIP
Description
The RM3283 consists of two analog ARINC 429 receivers
which take differentially encoded ARINC level data and
convert it to serial TTL level data. The RM3283 provides
two complete analog ARINC receivers and no external
components are required.
Input level shifting thin film resistors and bipolar technology
allow ARINC input voltage transients up to 100V without
damage to the RM3283.
Each channel is identical, featuring symmetrical propagation
delays for better high speed performance. Input common
mode rejection is excellent and threshold voltage is stable,
independent of supply voltage. Data outputs are TTL and
CMOS compatible.
Two TTL compatible test inputs used to test the ARINC
channels are available. They can be used to override the
ARINC input data and set the channel outputs to a known
state.
The Fairchild RM3182A line driver is the companion chip to
the RM3283 line receiver. Together they provide the analog
functions needed for the ARINC 429 interface. Digital data
processing involving serial-to-parallel conversion and clock
recovery can be accomplished using one of the ARINC
interface IC's available or by an equivalent gate array
implementation.
Block Diagram
65-3283-01
-V
S
+V
S
Gnd
+V
L
Bit
Detection
and Level
Shifting
Hysteresis
Channel
Test
Circuitry
Bit Detection
and Level
Shifting
Hysteresis
Out 1A
Out 1B
Out 2A
Out 2B
In 1A
In 1B
Cap 1A
Cap 1B
Test A
Test B
In 2A
In 2B
Cap 2A
Cap 2B
18
16
19
17
2
20
6
4
7
3
1
14
11
9
15
12
8
5
Output
Driver
Output
Driver
Bandgap Voltage
Reference
Threshold
Generator
RM3283
RM3283
Dual ARINC 429 Line Receiver
RM3283
PRODUCT SPECIFICATION
2
REV. 1.0.1 12/7/00
Functional Description
The RM3283 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor input network, a window comparator, and a logic
output buffer stage. The first stage provides overvoltage
protection and biases the signal using voltage dividers and
current sources, providing excellent input common mode
rejection. The test inputs are provided to set the outputs to a
predetermined state for built-in channel test capability. If the
test inputs are not used, they should be grounded.
The window comparator section detects data from the resis-
tor input network. A Logic 1 corresponds to ARINC "High"
state (OUTA) and a Logic 0, to ARINC "Low" state (OutB).
An ARINC "Null" state at the inputs forces both outputs to
Logic 0. Threshold and hysteresis voltages are generated by
a bandgap voltage reference to maintain stable switching
characteristics over temperature and power supply
variations.
The output stage generates a TTL compatible logic output
capable of driving 3mA of load.
Pin Assignments
20
2
3
4
5
6
7
8
9
10
-V
S
TestA
DIP
Top View
Cap2B
In2B
Out2B
In2A
Cap2A
Out2A
+V
L
NC
11
12
13
14
15
16
17
18
19
TestB
+V
S
Out1B
NC
GND
Out1A
In1B
Cap1B
In1A
Cap1A
65-3283-02
Absolute Maximum Ratings
Parameter
Min.
Max.
Units
Supply Voltage (V
CC
to V
EE
)
+36
V
V
LOGIC
Voltage
+7
V
Logic Input Voltage
-0.3
V
LOGIC
+ 0.3
V
Temperature Range
Storage
-65
+150
C
Operating
-55
+125
C
Junction Temperature
-55
+175
C
Lead Soldering Temperature
60 sec., DIP, LCC
+300
C
10 sec., SOIC
+260
C
PRODUCT SPECIFICATION
RM3283
REV. 1.0.1 12/7/00
3
Thermal Characteristics
(Still air, soldered on a PC board)
Note:
1. MIL-STD-1835.
Notes:
1. As stated in ARINC429.
2. V
T
refers ot the threshold voltage at which the channels output switches from low to high or from high to low.
3. Common mode voltage present at both ARINC inputs.
4. Guaranteed by design.
5. Test inputs should be connected to ground if not used.
6. Sample tested.
Parameter
DIP
Maximum Junction Temperature
+175C
Thermal Resistance,
JC
70C/W
Thermal Resistance,
JC
28C/W
1
DC Electrical Characteristics
T
A
= -55C to +125C, 12V
V
S
15V, V
L
= +5V, unless otherwise noted.
Symbol
Parameter
Conditlons
Min.
Typ.
Max.
Units
I
CC
(+V
S
)
Test inputs = 0V
4.3
6.0
mA
I
EE
(-V
S
)
Test inputs = 0V
10.1
12.0
mA
I
L
(V
L
)
Test inputs = 5V
14.0
17.5
mA
V
TL
2
V(A)-V(B)
Low threshold
4.7
5.0
5.3
V
V
TH
2
V(A)-V(B)
High threshold
5.7
6.0
6.3
V
V
IN
V(A)-V(B)
OutA and OutB = 0
-2.5
0
2.5
V
V
IC
3
V(A) and V(B)-GND
Maximum common mode
frequency = 80 kHz
5
V
R
I
Input resistance, Input A to Input B
35
50
k
R
H
Input resistance, Input A to Gnd
20
25
k
R
G
Input resistance, B to Gnd
Filter caps disconnected
20
25
k
C
I
1,4
Input capacitance, A to B
10
pF
C
H
1,4
Input capacitance, A to Gnd
Filter caps disconnected
10
pF
C
G
1,4
Input capacitance, B to Gnd
Filter caps disconnected
10
pF
Test Inputs (TestA, TestB)
V
IH
5
Logic 1 input voltage
2.7
V
V
IL
5
Logic 0 input voltage
0
0.8
V
I
IH
Logic 1 input current
V
IH
= 5V
120
300
A
I
IL
Logic 0 input voltage
V
IL
= 0.8V
15
40
A
Outputs
V
OH
I
OH
= 100 A
T
A
= 25C
4.0
4.3
V
I
OH
= 2.8 mA
Full temperature range
3.5
4.0
V
V
OL
I
OL
= 100 A
T
A
= 25C
0.02
0.1
V
I
OL
= 2.0 mA
Full temperature range
0
0.8
V
Tr
6
Rise Time
C
L
= 50 pF, @ 25C
50
70
ns
Tf
6
Fall Time
C
L
= 50 pF, @ 25C
40
70
ns
T
PLH
Propagation delay
Output low to high
C
L
= 50 pF, f = 400 kHz
Filter caps = 39 pF
T
A
= 25C
700
ns
T
PHL
Output high to low
700
ns
RM3283
PRODUCT SPECIFICATION
4
REV. 1.0.1 12/7/00
Typical Performance Characteristics
Figure 1. Propagation Delay vs. Temperature
Figure 2. Supply Current vs. Temperature
C
L
= 50 pF, C
FILTER
= 39 pF
Figure 3. Output Voltage Low vs. Output Current
Figure 4. Output Voltage High vs. Output Current
Figure 5. T
R
and T
F
vs. Temperature
Figure 6. Propagation Delay vs. Filter Capacitance
T
A
= 25C
65-3283-04
900
800
700
600
500
400
300
200
100
0
Temperature (
C)
TP
HL
, TP
LH
(ns)
-55
TP
HL
TP
LH
25
125
65-3283-05
20
18
16
14
12
10
8
6
4
2
0
Temperature (
C)
Current (mA)
-55
I
CC
25
125
I
EE
I
L
65-3283-06
1.00
0.75
0.50
0.25
0
I
OL
(mA)
V
OL
(V
olts)
3.0
0
0.5
1.0
1.5
2.0
2.5
+125
C
+25
C
+55
C
65-3283-07
4.5
4.3
4.1
3.9
3.7
3.5
I
OH
(mA)
V
OH
(V
olts)
3.0
0
0.5
1.0
1.5
2.0
2.5
+125
C
+25
C
-55
C
65-3283-08
70
60
50
40
30
20
10
0
Temperature ( C)
Rise/Fall Time (ns)
-55
T
F
T
R
25
125
65-3283-09
3.0
2.5
2.0
1.5
1.0
0.5
0
Filter Capacitance (pF)
Prop Delay (
s)
50
150
200
250
350
400
0
100
300
T = +25 C
A
T
PLH
T
PHL
PRODUCT SPECIFICATION
RM3283
REV. 1.0.1 12/7/00
5
AC Test Waveforms
Figure 7. Propagation Delay
Figure 8. Rise/Fall Times
Test Circuit
Figure 9. AC Test Schematic Diagram
+10V
0V
TPLH
T
PHL
ARINC In
(Differential)
Logic Out
(A Output)
65-3283-10
10%
90%
90%
10%
T
R
T
F
65-3283-11
Logic
Out
65-3283-12
In1 A
In2 A
V
REF
18
6
16
4
19
17
7
3
14
5
8
12
15
9
1
11
RM3283
39pF
39pF
39pF
39pF
0.1 F
+15V
-15V
+5V
50 pF
Out 1A
50 pF
50 pF
Out 1B
Out 2A
Out 2B
0.01 F
0.01 F
50 pF
Notes:
1. V
IN
= 400 kHz square wave, -3.5V to +3.5V.
2. Set V
REF
= +3.5 V to test V
OUT1
and V
OUT3
.
Set V
REF
= -3.5 V to test V
OUT2
and V
OUT4
.
3. 50 pF load capacitance includes probe and wiring capacitance.
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