2000 Fairchild Semiconductor Corporation
DS011543
www.fairchildsemi.com
January 1993
Revised August 2000
SCAN18254
1A Non-
Inver
ti
ng L
i
ne
Dri
ver
wit
h
25
Seri
es
Resi
st
or O
u
t
put
s
SCAN182541A
Non-Inverting Line Driver
with 25
Series Resistor Outputs
General Description
The SCAN182541A is a high performance BiCMOS line
driver featuring separate data inputs organized into dual 9-
bit bytes with byte-oriented paired output enable control
signals. This device is compliant with IEEE 1149.1 Stan-
dard Test Access Port and Boundary-Scan architecture
with the incorporation of the defined Boundary-Scan test
logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
Features
s
IEEE 1149.1 (JTAG) Compliant
s
High performance BiCMOS technology
s
25
series resistor outputs eliminate need for external
terminating resistors
s
Dual output enable signals per byte
s
3-STATE outputs for bus-oriented applications
s
25 mil pitch SSOP (Shrink Small Outline Package)
s
Includes CLAMP, IDCODE and HIGHZ instructions
s
Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
s
Power up 3-STATE for hot insert
s
Member of Fairchild's SCAN Products
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package
Number
Package Description
SCAN182541ASSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin
Names
Description
AI
(08)
Input Pins, A Side
BI
(08)
Input Pins, B Side
AOE
1
,
AOE
2
3-STATE Output Enable Input Pins, A Side
BOE
1
,
BOE
2
3-STATE Output Enable Input Pins, B Side
AO
(08)
Output Pins, A Side
BO
(08)
Output Pins, B Side
3
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SCAN18254
1A
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
SCAN182541A Product IDCODE
(32-Bit Code per IEEE 1149.1)
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required
to shift in the 8-bit instruction for SAMPLE/PRELOAD. The
sequence of: CAPTURE-IR
EXIT1-IR
UPDATE-IR will
update the SAMPLE/PRELOAD instruction. For more infor-
mation refer to the section on instruction definitions.
Instruction Register Scan Chain Definition
MSB
LSB
Scan Cell TYPE1
Scan Cell TYPE2
Version Entity
Part
Manufacture
r
Required b
y
Number
ID
1149.1
0000
111111 000000100
1
00000001111
1
MSB
LSB
Instruction Code
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGH-Z
01000001
SAMPLE-IN
01000010
SAMPLE-OUT
00100010
EXTEST-OUT
10101010
IDCODE
11111111
BYPASS
All Others
BYPASS
5
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SCAN18254
1A
Description of BOUNDARY-SCAN Circuitry
(Continued)
Input BOUNDARY-SCAN Register
Scan Chain Definition (22 Bits in Length)
When SAMPLE-IN is Active
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