2002 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.1
Features
Low Start up Current
Maximum Duty Clamp
UVLO With Hysteresis
Operating Frequency up to 500KHz
Description
The UC3842/UC3843/UC3844/UC3845 are fixed
frequencycurrent-mode PWM controller. They are specially
designed for Off-Line and DC to DC converter applications
with minimum external components. These integrated
circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain
error amplifier, current sensing comparator and a high
current totempole output for driving a Power MOSFET. The
UC3842 and UC3844 have UVLO thresholds of 16V (on)
and 10V (off). The UC3843 and UC3845 are 8.5V(on) and
7.9V (off). The UC3842 and UC3843 can operate within
100% duty cycle. The UC3844 and UC3845 can operate
with 50% duty cycle.
8-DIP
14-SOP
1
1
8-SOP
1
Internal Block Diagram
UC3842/UC3843/UC3844/UC3845
SMPS Controller
* NORMALLY 8DIP/8SOP PIN NO.
* ( ) IS 14SOP PINNO.
* TOGGLE FLIP FLOP USED ONLY IN UC3844, UC3845
UC3842/UC3843/UC3844/UC3845
2
Absolute Maximum Ratings
Note:
1. Board Thickness 1.6mm, Board Dimension 76.2mm
114.3mm, (Reference EIA / JSED51-3, 51-7)
2. Do not exceeed P
D
and SOA (Safe Operation Area)
Power Dissipation Curve
Thermal Data
Pin Array
Parameter
Symbol
Value
Unit
Supply Voltage
V
CC
30
V
Output Current
I
O
1
A
Analog Inputs (Pin 2.3)
V
(ANA)
-0.3 to 6.3
V
Error Amp Output Sink Current
I
SINK (E.A)
10
mA
Power Dissipation at T
A
25
C (8DIP)
P
D
(Note1,2)
1200
mW
Power Dissipation at T
A
25
C (8SOP)
P
D
(Note1,2)
460
mW
Power Dissipation at T
A
25
C (14SOP)
P
D
(Note1,2)
680
mW
Storage Temperature Range
T
STG
-65 ~ +150
C
Lead Temperature (Soldering, 10sec)
T
LEAD
+300
C
Characteristic
Symbol
8-DIP
8-SOP
14-SOP
Unit
Thermal Resistance Junction-ambient
R
thj-amb(MAX)
100
265
180
C/W
800
700
600
500
400
300
900
1000
1100
0
10
20
30
40
50
60
70
80
90
100 110 120 130 140 150
AMBIENT TEMPERATURE (
)
P
O
W
E
R DI
SS
I
P
A
T
I
O
N (
m
W
)
1200
8DIP
14SOP
8SOP
800
700
600
500
400
300
900
1000
1100
0
10
20
30
40
50
30
40
50
60
70
80
60
70
80
90
100 110
90
100 110 120 130 140
120 130 140 150
AMBIENT TEMPERATURE (
)
P
O
W
E
R DI
SS
I
P
A
T
I
O
N (
m
W
)
1200
8DIP
14SOP
8SOP
V
CC
GND
PWR GND
COMP 1
N/C 2
V
FB
N/C
3
4
V
REF
N/C
PWR V
C
14
13
12
11
CURRENT SENSE
5
N/C
R
T/
C
T
6
7
OUTPUT
10
9
8
COMP 1
V
FB
2
CURRENT SENSE
R
T/
C
T
3
4
V
REF
V
CC
OUTPUT
GND
8
7
6
5
8DIP,8SOP
14SOP
V
CC
GND
PWR GND
COMP 1
N/C 2
V
FB
N/C
3
4
V
REF
N/C
PWR V
C
14
13
12
11
CURRENT SENSE
5
N/C
R
T/
C
T
6
7
OUTPUT
10
9
8
V
CC
GND
PWR GND
COMP 1
N/C 2
V
FB
N/C
3
4
V
REF
N/C
PWR V
C
14
13
12
11
CURRENT SENSE
5
N/C
R
T/
C
T
6
7
OUTPUT
10
9
8
COMP 1
V
FB
2
CURRENT SENSE
R
T/
C
T
3
4
V
REF
V
CC
OUTPUT
GND
8
7
6
5
COMP 1
V
FB
2
CURRENT SENSE
R
T/
C
T
3
4
V
REF
V
CC
OUTPUT
GND
8
7
6
5
8DIP,8SOP
14SOP
UC3842/UC3843/UC3844/UC3845
3
Electrical Characteristics
(V
CC
=15V, R
T
=10k
,
C
T
=3.3nF, T
A
= 0
C to +70
C, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
REFERENCE SECTION
Reference Output Voltage
V
REF
T
J
= 25
C, I
REF
= 1mA
4.90
5.00
5.10
V
Line Regulation
V
REF
12V
V
CC
25V
-
6
20
mV
Load Regulation
V
REF
1mA
I
REF
20mA
-
6
25
mV
Short Circuit Output Current
I
SC
T
A
= 25
C
-
-100
-180
mA
OSCILLATOR SECTION
Oscillation Frequency
f
T
J
= 25
C
47
52
57
kHz
Frequency Change with
Voltage
f/
V
CC
12V
V
CC
25V
-
0.05
1
%
Oscillator Amplitude
V
OSC
-
-
1.6
-
V
P-P
ERROR AMPLIFIER SECTION
Input Bias Current
I
BIAS
-
-
-0.1
-2
A
Input Voltage
V
I(E>A)
V
pin1
= 2.5V
2.42
2.50
2.58
V
Open Loop Voltage Gain
G
VO
2V
V
O
4V (Note3)
65
90
-
dB
Power Supply Rejection Ratio
PSRR
12V
V
CC
25V (Note3)
60
70
-
dB
Output Sink Current
I
SINK
V
pin2
= 2.7V, V
pin1
= 1.1V
2
7
-
mA
Output Source Current
I
SOURCE
V
pin2
= 2.3V, V
pin1
= 5V
-0.6
-1.0
-
mA
High Output Voltage
V
OH
V
pin2
= 2.3V, R
L
= 15k
to GND
5
6
-
V
Low Output Voltage
V
OL
V
pin2
= 2.7V, R
L
= 15k
to Pin 8
-
0.8
1.1
V
CURRENT SENSE SECTION
Gain
G
V
(Note 1 & 2)
2.85
3
3.15
V/V
Maximum Input Signal
V
I(MAX)
V
pin1
= 5V(Note 1)
0.9
1
1.1
V
Power Supply Rejection Ratio
PSRR
12V
V
CC
25V (Note 1,3)
-
70
-
dB
Input Bias Current
I
BIAS
-
-
-3
-10
A
OUTPUT SECTION
Low Output Voltage
V
OL
I
SINK
= 20mA
-
0.08
0.4
V
I
SINK
= 200mA
-
1.4
2.2
V
High Output Voltage
V
OH
I
SOURCE
= 20mA
13
13.5
-
V
I
SOURCE
= 200mA
12
13.0
-
V
Rise Time
t
R
T
J
= 25
C, C
L
= 1nF (Note 3)
-
45
150
ns
Fall Time
t
F
T
J
= 25
C, C
L
= 1nF (Note 3)
-
35
150
ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold
V
TH(ST)
UC3842/UC3844
14.5
16.0
17.5
V
UC3843/UC3845
7.8
8.4
9.0
V
Min. Operating Voltage
(After Turn On)
V
OPR(MIN)
UC3842/UC3844
8.5
10.0
11.5
V
UC3843/UC3844
7.0
7.6
8.2
V
UC3842/UC3843/UC3844/UC3845
4
Electrical Characteristics
(Continued)
(V
CC
=15V, R
T
=10k
,
C
T
=3.3nF, T
A
= 0
C to +70
C, unless otherwise specified)
Adjust V
CC
above the start threshould before setting at 15V
Note:
1. Parameter measured at trip point of latch
2. Gain defined as:
3. These parameters, although guaranteed, are not 100 tested in production.
Figure 1. Open Loop Test Circuit
High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors
should be connected close to pin 5 in a single point ground. The transistor and 5k
potentiometer are used to sample the
oscillator waveform and apply an adjustable ramp to pin 3.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
PWM SECTION
Max. Duty Cycle
D
(Max)
UC3842/UC3843
95
97
100
%
D
(Max)
UC3844/UC3845
47
48
50
%
Min. Duty Cycle
D
(MIN)
-
-
-
0
%
TOTAL STANDBY CURRENT
Start-Up Current
I
ST
-
-
0.45
1
mA
Operating Supply Current
I
CC(OPR)
V
pin3
=V
pin2
=ON
-
14
17
mA
Zener Voltage
V
Z
I
CC
= 25mA
30
38
-
V
A
V
pin1
V
pin3
------------------
=
UC3842
,0
V
pin3
0.8V
UC3842/UC3843/UC3844/UC3845
5
Figure 2. Under Voltage Lockout
During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with
a bleeder resistor to prevent activating the power switch with output leakage current.
Figure 3. Error Amp Configuration
Figure 4. Current Sense Circuit
Peak current (I
S
) is determined by the formula:
A small RC filter may be required to suppress switch transients.
UC3842/44 UC3843/45
I
S
MAX
(
)
1.0V
R
S
------------
=
UC3842/UC3843/UC3844/UC3845
6
Figure 5. Oscillator Waveforms and Maximum Duty Cycle
Oscillator timing capacitor, C
T
, is charged by V
REF
through R
T
and discharged by an internal current source. During the
discharge time, the internal clock signal blanks the output to the low state. Selection of R
T
and C
T
therefore determines both
oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:
t
c
= 0.55 R
T
C
T
Frequency, then, is: f=(t
c
+ t
d
)
-1
Figure 8. Shutdown Techniques
Figure 6. Oscillator Dead Time & Frequency
Figure 7. Timing Resistance vs Frequency
t
D
R
T
C
T
I
n
0.0063R
T
2.7
0.0063R
T
4
----------------------------------------
=
ForRT 5K
f
1.8
R
T
C
T
---------------
=
,
>
(Deadtime vs C
T
RT > 5k
)
UC3842/UC3843/UC3844/UC3845
7
Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two
diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The
PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins
1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be
reset by cycling V
CC
below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
Figure 9. Slope Compensation
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for
converters requiring duty cycles over 50%. Note that capacitor, C
T
, forms a filter with R2 to suppress the leading edge switch
spikes.
Temperature (
C)
Figure 10. Temperature Drift (Vref)
Temperature (
C)
Figure 11. Temperature Drift (Ist)
Temperature (
C)
Figure 12. Temperature Drift (Icc)
UC3842/UC3843
UC3842/UC3843/UC3844/UC3845
8
Mechanical Dimensions
Package
6.40
0.20
3.30
0.30
0.130
0.012
3.40
0.20
0.134
0.008
#1
#4
#5
#8
0.252
0.008
9.20
0.20
0.79
2.54
0.100
0.031
()
0.46
0.10
0.018
0.004
0.060
0.004
1.524
0.10
0.362
0.008
9.60
0.378
MAX
5.08
0.200
0.33
0.013
7.62
0~15
0.300
MAX
MIN
0.25
+0.10
0.05
0.010
+0.004
0.002
8-DIP
UC3842/UC3843/UC3844/UC3845
9
Mechanical Dimensions
(Continued)
Package
8-SOP
4.92
0.20
0.194
0.008
0.41
0.10
0.016
0.004
1.27
0.050
5.72
0.225
1.55
0.20
0.061
0.008
0.1~0.25
0.004~0.001
6.00
0.30
0.236
0.012
3.95
0.20
0.156
0.008
0.50
0.20
0.020
0.008
5.13
0.202
MAX
#1
#4
#5
0~8
#8
0.56
0.022
()
1.80
0.071
MAX0.10
MAX0.004
MAX
MIN
+
0.10
-0.05
0.15
+
0.004
-0.002
0.006
UC3842/UC3843/UC3844/UC3845
10
Mechanical Dimensions
(Continued)
Package
8.56
0.20
0.337
0.008
1.27
0.050
5.72
0.225
1.55
0.10
0.061
0.004
0.05
0.002
6.00
0.30
0.236
0.012
3.95
0.20
0.156
0.008
0.60
0.20
0.024
0.008
8.70
0.343
MAX
#1
#7
#8
0~8
#14
0.47
0.019
()
1.80
0.071
MAX0.10
MAX0.004
MAX
MIN
+
0.10
-0.05
0.20
+
0.004
-0.002
0.008
+
0.10
-0.05
0.406
+
0.004
-0.002
0.016
14-SOP
UC3842/UC3843/UC3844/UC3845
11
Ordering Information
Product Number
Package
Operating Temperature
UC3842N
8-DIP
0 ~ + 70
C
UC3843N
UC3844N
UC3845N
UC3842D1
8-SOP
UC3843D1
UC3844D1
UC3845D1
UC3842D
14-SOP
UC3843D
UC3844D
UC3845D
UC3842/UC3843/UC3844/UC3845
2/19/02 0.0m 001
Stock#DSxxxxxxxx
2002 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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