DS04-21368-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Dual S
erial Input
PLL Frequency
Synthesizer
MB15F73UL
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DESCRIPTION
The Fujitsu MB15F73UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250 MHz and
a 600 MHz prescalers. A 64/65 or a 128/129 for the 2250 MHz prescaler, and a 8/9 or a 16/17 for the 600 MHz
prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 3.2 mA at 2.7 V. The supply voltage range
is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The data format is the same as the previous one MB15F03SL, MB15F73SP. Fast locking
is achieved for adopting the new circuit.
The new package (BCC20) decreases a mount area of MB15F73UL more than 30
%
comparing with the former
BCC16 (for dual PLL) .
MB15F73UL is ideally suited for wireless mobile communications, such as GSM and PCS.
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FEATURES
High frequency operation
: RF synthesizer : 2250 MHz Max.
: IF synthesizer : 600 MHz Max.
Low power supply voltage
: V
CC
=
2.4 to 3.6 V
Ultra low power supply current : I
CC
=
3.2 mA Typ.
(V
CC
=
Vp
=
2.7 V, Ta
=
+
25
C, SW
IF
=
SW
RF
=
0 in IF/RF locking state)
(Continued)
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PACKAGES
20-pin plastic TSSOP
20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M05)
MB15F73UL
2
(Continued)
Direct power saving function : Power supply current in power saving mode
Typ. 0.1
A (V
CC
=
Vp
=
2.7 V, Ta
=
+
25
C)
Max.
10
A (V
CC
=
Vp
=
2.7 V)
Software selectable charge pump current : 1.5 mA/6.0 mA Typ.
Dual modulus prescaler : 2250 MHz prescaler (64/65 or128/129) /600 MHz prescaler (8/9 or 16/17)
23 bit shift register
Serial input binary 14-bit programmable reference divider : R
=
3 to 16,383
Serial input programmable divider consisting of:
- Binary 7-bit swallow counter : 0 to 127
- Binary 11-bit programmable counter : 3 to 2,047
Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit
On-chip phase control for phase comparator
On-chip phase comparator for fast lock and low noise
Built-in digital locking detector circuit to detect PLL locking and unlocking
Operating temperature : Ta
=
-
40
C to
+
85
C
Serial data format compatible with MB15F02SL
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PIN ASSIGNMENTS
(TSSOP-20)
TOP VIEW
(FPT-20P-M06)
(BCC-20)
TOP VIEW
(LCC-20P-M05)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Clock
Data
LE
fin
RF
Xfin
RF
GND
RF
V
CCRF
PS
RF
Vp
RF
Do
RF
OSC
IN
GND
fin
IF
Xfin
IF
GND
IF
V
CCIF
PS
IF
Vp
IF
Do
IF
LD/fout
fin
IF
Xfin
IF
GND
IF
V
CCIF
PS
IF
Vp
IF
1
2
3
4
5
6
16
15
14
13
12
11
LE
fin
RF
Xfin
RF
GND
RF
V
CCRF
PS
RF
7
8
9
10
20 19 18 17
Do
IF
Do
RF
LD/fout
Vp
RF
GND
OSC
IN
Data
Clock
MB15F73UL
3
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PIN DESCRIPTION
Pin no.
Pin
name
I/O
Descriptions
TSSOP
BCC
1
19
OSC
IN
I
The programmable reference divider input pin. TCXO should be connected with
an AC coupling capacitor.
2
20
GND
Ground pin for OSC input buffer and the shift register circuit.
3
1
fin
IF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
4
2
Xfin
IF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3
GND
IF
Ground pin for the IF-PLL section.
6
4
V
CCIF
Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit) , the shift register and the oscillator input buffer.
7
5
PS
IF
I
Power saving mode control pin for the IF-PLL section. This pin must be set at "L"
when the power supply is started up. (Open is prohibited.)
PS
IF
=
"H" ; Normal mode/PS
IF
=
"L" ; Power saving mode
8
6
Vp
IF
Power supply voltage input pin for the IF-PLL charge pump.
9
7
Do
IF
O
Charge pump output for the IF-PLL section.
10
8
LD/fout O
Lock detect signal output (LD) /phase comparator monitoring output (fout) pin.
The output signal is selected by LDS bit in a serial data.
LDS bit
=
"H" ; outputs fout signal/LDS bit
=
"L" ; outputs LD signal
11
9
Do
RF
O
Charge pump output for the RF-PLL section.
12
10
Vp
RF
Power supply voltage input pin for the RF-PLL charge pump.
13
11
PS
RF
I
Power saving mode control for the RF-PLL section. This pin must be set at "L"
when the power supply is started up. (Open is prohibited. )
PS
RF
=
"H" ; Normal mode/PS
RF
=
"L" ; Power saving mode
14
12
V
CCRF
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit)
15
13
GND
RF
Ground pin for the RF-PLL section
16
14
Xfin
RF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
fin
RF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
18
16
LE
I
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set "H", data in the shift register is transferred to the corresponding
latch according to the control bit in a serial data.
19
17
Data
I
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.
MB15F73UL
4
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BLOCK DIAGRAM
(9)
Clock
Data
LE
PS
RF
Xfin
RF
fin
RF
OSC
IN
fin
IF
PS
IF
V
CCIF
GND
IF
fp
IF
Do
IF
LD
IF
T1
T2
T1
T2
FC
RF
SW
RF
LDS
Do
RF
OR
LD
/
fout
LD
fr
IF
fr
RF
fp
IF
fp
RF
fr
IF
fr
RF
fp
RF
C
N
1
C
N
2
AND
V
CCRF
GND
RF
Vp
RF
(19)
( )
(11)
(17)
(18)
(12)
(13)
(10)
(8)
(7)
(3)
(4)
(1)
(5)
(15)
6
5
9
10
11
15
12
GND
(20)
2
14
20
19
(16)
18
13
16
14
17
1
3
Xfin
IF
(2)
4
7
Vp
IF
(6)
8
Intermittent
mode control
(IF-PLL)
Prescaler
(IF-PLL)
(8/9, 16/17)
7 bit latch
11 bit latch
Binary 7-bit
swallow counter
(IF-PLL)
Binary 11-bit
programmable
counter (IF-PLL)
Phase
comp.
(IF-PLL)
Charge
pump
(IF-PLL)
Current
Switch
2 bit latch
14 bit latch
1 bit latch
Binary 14-bit pro-
grammable ref.
counter(IF-PLL)
C/P setting
counter
Lock Det.
(IF-PLL)
2 bit latch
14 bit latch
1 bit latch
Binary 14-bit pro-
grammable ref.
counter (RF-PLL))
C/P setting
counter
Selector
Prescaler
(RF-PLL)
(64/65, 128/129)
Lock Det.
(RF-PLL)
Intermittent
mode control
(RF-PLL)
3 bit latch
FC
IF
SW
IF
LDS
3 bit latch
7 bit latch
11 bit latch
Binary 7-bit
swallow counter
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
Phase
comp.
(RF-PLL)
Fast lock
Tuning
Charge
pump
(RF-PLL)
Current
Switch
Schmitt
circuit
Latch selector
Schmitt
circuit
Schmitt
circuit
23-bit shift register
Fast
lock
Tuning
LD
RF
fp
RF
O : TSSOP
( ) : BCC
MB15F73UL
5
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ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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RECOMMENDED OPERATING CONDITIONS
Note :
V
CCRF
, Vp
RF
, V
CCIF
and Vp
IF
must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to V
CCRF
, Vp
RF
, V
CCIF
and Vp
IF
to keep
them equal.
It is recommended that the non-use PLL is controlled by power saving function.
Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the following precautions when handling the device.
When storing and transporting the device, put it in a conductive case.
Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as
well as yourself. Use a conductive sheet on working bench.
Before fitting the device into or removing it from the socket, turn the power supply off.
When handling (such as transporting) the device mounted board, protect the leads with a conductive
sheet.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Rating
Unit
Min.
Max.
Power supply voltage
V
CC
-
0.5
4.0
V
Vp
V
CC
4.0
V
Input voltage
V
I
-
0.5
V
CC
+
0.5
V
Output voltage
LD/fout
V
O
GND
V
CC
V
Do
IF
, Do
RF
V
DO
GND
Vp
V
Storage temperature
Tstg
-
55
+
125
C
Parameter
Symbol
Value
Unit
Remarks
Min.
Typ.
Max.
Power supply voltage
V
CC
2.4
2.7
3.6
V
V
CCRF
=
V
CCIF
Vp
V
CC
2.7
3.6
V
Input voltage
V
I
GND
V
CC
V
Operating temperature
Ta
-
40
+
85
C
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