AE2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
4
2 M
16 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F121642-75/-102/-102L/-10/-10L
CMOS 4-Bank
2,097,152-Word
16 Bit
Synchronous Dynamic Random Access Memory
s
DESCRIPTION
The Fujitsu MB81F121642 is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
134,217,728 memory cells accessible in a 16-bit format. The MB81F121642 features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F121642 SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F121642 is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
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PRODUCT LINE & FEATURES
Parameter
MB81F121642
-75
-102/-102L
-10/-10L
Reference Value
@66MHz(CL=2)
CL - t
RCD
- t
RP
3 - 3 - 3 clk min.
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
2 - 2 - 2 clk min.
Clock Frequency
133 MHz max.
100 MHz max.
100 MHz max.
66 MHz max.
Burst Mode Cycle Time
CL = 2
10 ns min.
10 ns min.
10 ns min.
15ns min.
CL = 3
7.5 ns min.
10 ns min.
10 ns min.
10 ns min.
Access Time From Clock
CL = 2
6 ns max.
6 ns max.
6 ns max.
8 ns max.
CL = 3
5.4 ns max.
6 ns max.
6 ns max.
6 ns max.
Operating Current
115 mA
110 mA
100 mA
70 mA
Power Down Mode Current (I
CC2P
)
1 mA
Self Refresh Current (I
CC6
)
1 mA
1 mA / 0.8 mA
1 mA / 0.8 mA
1 mA
Single +3.3 V Supply 0.3 V tolerance
LVTTL compatible I/O interface
4 K refresh cycles every 64 ms
Four bank operation
Burst read/write operation and burst
read/single write operation capability
Programmable burst type, burst length, and
CAS latency
Auto-and Self-refresh (every 15.6
s)
CKE power down mode
Output Enable and Input Data Mask
2
MB81F121642-75/-102/-102L/-10/-10L
PRELIMINARY (AE2E)
s
PACKAGE
Package and Ordering Information
54-pin plastic (400 mil) TSOP-II, order as MB81F121642-
FN (standard-version) or
MB81F121642-
LFN (L-version)
54-pin plastic TSOP(II) Package
(FPT-54P-M02)
(Normal Bend)
Marking side
3
MB81F121642-75/-102/-102L/-10/-10L
PRELIMINARY (AE2E)
s
PIN ASSIGNMENTS AND DESCRIPTIONS
54-Pin TSOP(II)
(TOP VIEW)
<Normal Bend: FPT-54P-M02>
* : These pins are connected internally in the chip.
Pin Number
Symbol
Function
1, 3, 9, 14, 27, 43, 49
V
CC
, V
CCQ
Supply Voltage
2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47,
48, 50, 51, 53
DQ
0
to DQ
15
Data I/O
Lower Byte : DQ
0
to DQ
7
Upper Byte : DQ
8
to DQ
15
6, 12, 28, 41, 46, 52, 54
V
SS
, V
SSQ
*
Ground
36, 40
N.C.
No Connection
16
WE
Write Enable
17
CAS
Column Address Strobe
18
RAS
Row Address Strobe
19
CS
Chip Select
20, 21
A
13
(BA
0
), A
12
(BA
1
)
Bank Select (Bank Address)
22
AP
Auto Precharge Enable
22, 23, 24, 25, 26, 29, 30, 31, 32, 33,
34, 35
A
0
to A
11
Address Input
Row: A
0
to A
11
Column: A
0
to A
8
37
CKE
Clock Enable
38
CLK
Clock Input
15, 39
DQML, DQMU
DQ MASK
RAS
A
1
A
0
A
10
/AP
A
13
(BA
0
)
CS
CAS
WE
V
CCQ
V
SSQ
V
CCQ
V
SSQ
DQ
6
DQ
2
V
CC
A
6
A
7
A
8
A
9
CKE
CLK
DQMU
V
CCQ
V
SSQ
V
CCQ
V
SSQ
DQ
9
DQ
13
V
SS
V
CC
A
3
A
2
V
SS
A
4
A
5
(Marking side)
42
41
40
39
38
37
36
35
34
54
53
52
51
50
49
48
47
46
45
1
2
3
4
5
9
10
6
7
8
13
14
15
16
17
18
19
20
21
22
44
43
11
12
33
32
31
30
29
28
23
24
25
26
27
DQ
1
DQ
0
DQ
4
DQ
3
DQML
DQ
7
DQ
5
A
12
(BA
1
)
V
CC
DQ
10
DQ
11
DQ
12
DQ
14
DQ
15
DQ
8
V
SS
N.C.
N.C.
A
11
4
MB81F121642-75/-102/-102L/-10/-10L
PRELIMINARY (AE2E)
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BLOCK DIAGRAM
A
12
(BA1)
A
13
(BA0)
Fig. 1 MB81F121642 BLOCK DIAGRAM
BANK-1
V
CC
V
SS
/V
SSQ
CLK
CKE
A
0
to A
11
,
A
10
/AP
DQ
0
to
DQ
15
COMMAND
DECODER
CLOCK
BUFFER
ADDRESS
BUFFER/
REGISTER
I/O DATA
BUFFER/
REGISTER
MODE
REGISTER
RAS
CAS
WE
DRAM
CORE
(4,096
512
16)
COL.
ADDR.
RAS
CAS
WE
CS
BANK-0
I/O
ROW
ADDR.
To each block
CONTROL
SIGNAL
LATCH
V
CCQ
BANK-2
BANK-3
COLUMN
ADDRESS
COUNTER
DQML
DQMU
5
MB81F121642-75/-102/-102L/-10/-10L
PRELIMINARY (AE2E)
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FUNCTIONAL TRUTH TABLE Note *1
COMMAND TRUTH TABLE Note *2, *3, and *4
Notes: *1.
V = Valid, L = Logic Low, H = Logic High, X = either L or H.
*2.
All commands assumes no CSUS command on previous rising edge of clock.
*3.
All commands are assumed to be valid state transitions.
*4.
All inputs are latched on the rising edge of clock.
*5.
NOP and DESL commands have the same effect on the part.
*6.
READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7.
ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
*8.
Required after power up. Refer to POWER-UP INITIALIZATION in page 19.
*9.
MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
Function
Notes Symbol
CKE
CS
RAS CAS WE
A
13
,
A
12
(BA)
A
11
A
10
(AP)
A
9
A
8
to
A
0
n-1
n
Device Deselect
*5
DESL
H
X
H
X
X
X
X
X
X
X
X
No Operation
*5
NOP
H
X
L
H
H
H
X
X
X
X
X
Burst Stop
BST
H
X
L
H
H
L
X
X
X
X
X
Read
*6
READ
H
X
L
H
L
H
V
X
L
X
V
Read with Auto-precharge
*6 READA
H
X
L
H
L
H
V
X
H
X
V
Write
*6
WRIT
H
X
L
H
L
L
V
X
L
X
V
Write with Auto-precharge
*6 WRITA
H
X
L
H
L
L
V
X
H
X
V
Bank Active
*7
ACTV
H
X
L
L
H
H
V
V
V
V
V
Precharge Single Bank
PRE
H
X
L
L
H
L
V
X
L
X
X
Precharge All Banks
PALL
H
X
L
L
H
L
X
X
H
X
X
Mode Register Set
*8, *9
MRS
H
X
L
L
L
L
L
L
L
V
V
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