DS05-50109-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (
16) FLASH MEMORY &
1M (
8) STATIC RAM
MB84VA2106
-10
/MB84VA2107
-10
s
FEATURES
Power supply voltage of 2.7 to 3.6 V
High performance
100 ns maximum access time
Operating Temperature
20 to +85
C
-- FLASH MEMORY
Minimum 100,000 write/erase cycles
Sector erase architecture
One 8 K word, two 4 K words, one 16 K word, and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
MB84VA2106: Top sector
MB84VA2107: Bottom sector
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
Low V
CC
write inhibit
2.5 V
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
Please refer to "MBM29LV160T/B" data sheet in detailed function
-- SRAM
Power dissipation
Operating : 35 mA max.
Standby : 30
A max.
Power down features using CE1s and CE2s
Data retention supply voltage: 2.0 V to 3.6 V
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MB84VA2106
-10
/MB84VA2107
-10
s
PIN ASSIGNMENTS
(Top View)
A
B
C
D
E
F
G
H
6
CE1s
V
SS
DQ
1
A
1
A
2
A
4
CE2s
A
9
5
A
10
DQ
5
DQ
2
A
0
A
3
A
7
RY/BY
A
14
4
OE
DQ
7
DQ
4
DQ
0
A
6
A
18
RESET
A
15
3
A
11
A
8
A
5
DQ
8
DQ
3
DQ
12
A
12
A
19
2
A
13
A
17
SA*
CEf
DQ
10
V
CC
f
DQ
6
DQ
15
/A
-1
1
WE
V
CC
s
A
16
V
SS
DQ
9
DQ
11
DQ
13
DQ
14
Table 1 Pin Configuration
Pin
Function
Input/
Output
A
0
to A
15
Address Inputs (Common)
I
A
16
to A
19
Address Input (Flash)
I
SA
Address Input (SRAM)
I
DQ
0
to DQ
7
Data Inputs/Outputs (Common)
I/O
DQ
8
to DQ
15
Data Inputs/Outputs (Flash)
I/O
CEf
Chip Enable (Flash)
I
CE1s
Chip Enable (SRAM)
I
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
RY/BY
Ready/Busy Outputs (Flash)
O
RESET
Hardware Reset Pin/Sector Protection Unlock (Flash)
I
N.C.
No Internal Connection
--
V
SS
Device Ground (Common)
Power
V
CC
f
Device Power Supply (Flash)
Power
V
CC
s
Device Power Supply (SRAM)
Power
*:
A
16
for SRAM
4
MB84VA2106
-10
/MB84VA2107
-10
s
PRODUCT LINE UP
s
BUS OPERATIONS
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
. See DC Characteristics for voltage levels.
Notes: 1. Other operations except for indicated this column are inhibited.
2. WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
3. Do not apply CEf = V
IL
, CE1s = V
IL
and CE2s = V
IH
at a time.
Flash Memory
SRAM
Ordering Part No.
V
CC
= 3.0 V
MB84VA2106-10/MB84VA2107-10
Max. Address Access Time (ns)
100
100
Max. CE Access Time (ns)
100
100
Max. OE Access Time (ns)
40
50
Table 2 User Bus Operations
Operation (1), (3)
CEf
CE1s
CE2s
OE
WE
DQ
0
to DQ
7
DQ
8
to DQ
15
RESET
Full Standby
H
H
X
X
X
HIGH-Z
HIGH-Z
H
X
L
Output Disable
X
X
X
H
H
HIGH-Z
HIGH-Z
H
Read from Flash (2)
L
H
X
L
H
D
OUT
D
OUT
H
X
L
Write to Flash
L
H
X
H
L
D
IN
D
IN
H
X
L
Read from SRAM
H
L
H
L
H
D
OUT
HIGH-Z
H
Write to SRAM
H
L
H
X
L
D
IN
HIGH-Z
H
Flash Hardware Reset
X
H
X
X
X
HIGH-Z
HIGH-Z
L
X
L
+0.6 V
0.3 V
5
MB84VA2106
-10
/MB84VA2107
-10
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
One 8 K word, two 4 K words, one 16 K word, and thirty one 32 K words.
Individual-sector, multiple-sector, or bulk-erase capability.
Sector
Sector Size
Address Range
Sector
Sector Size
Address Range
SA0
32K Words
00000H to 07FFFH
SA0
8K Words
00000H to 01FFFH
SA1
32K Words
08000H to 0FFFFH
SA1
4K Words
02000H to 02FFFH
SA2
32K Words
10000H to 17FFFH
SA2
4K Words
03000H to 03FFFH
SA3
32K Words
18000H to 1FFFFH
SA3
16K Words
04000H to 07FFFH
SA4
32K Words
20000H to 27FFFH
SA4
32K Words
08000H to 0FFFFH
SA5
32K Words
28000H to 2FFFFH
SA5
32K Words
10000H to 17FFFH
SA6
32K Words
30000H to 37FFFH
SA6
32K Words
18000H to 1FFFFH
SA7
32K Words
38000H to 3FFFFH
SA7
32K Words
20000H to 27FFFH
SA8
32K Words
40000H to 47FFFH
SA8
32K Words
28000H to 2FFFFH
SA9
32K Words
48000H to 4FFFFH
SA9
32K Words
30000H to 37FFFH
SA10
32K Words
50000H to 57FFFH
SA10
32K Words
38000H to 3FFFFH
SA11
32K Words
58000H to 5FFFFH
SA11
32K Words
40000H to 47FFFH
SA12
32K Words
60000H to 67FFFH
SA12
32K Words
48000H to 4FFFFH
SA13
32K Words
68000H to 6FFFFH
SA13
32K Words
50000H to 57FFFH
SA14
32K Words
70000H to 77FFFH
SA14
32K Words
58000H to 5FFFFH
SA15
32K Words
78000H to 7FFFFH
SA15
32K Words
60000H to 67FFFH
SA16
32K Words
80000H to 87FFFH
SA16
32K Words
68000H to 6FFFFH
SA17
32K Words
88000H to 8FFFFH
SA17
32K Words
70000H to 77FFFH
SA18
32K Words
90000H to 97FFFH
SA18
32K Words
78000H to 7FFFFH
SA19
32K Words
98000H to 9FFFFH
SA19
32K Words
80000H to 87FFFH
SA20
32K Words
A0000H to A7FFFH
SA20
32K Words
88000H to 8FFFFH
SA21
32K Words
A8000H to AFFFFH
SA21
32K Words
90000H to 97FFFH
SA22
32K Words
B0000H to B7FFFH
SA22
32K Words
98000H to 9FFFFH
SA23
32K Words
B8000H to BFFFFH
SA23
32K Words
A0000H to A7FFFH
SA24
32K Words
C0000H to C7FFFH
SA24
32K Words
A8000H to AFFFFH
SA25
32K Words
C8000H to CFFFFH
SA25
32K Words
B0000H to B7FFFH
SA26
32K Words
D0000H to D7FFFH
SA26
32K Words
B8000H to BFFFFH
SA27
32K Words
D8000H to DFFFFH
SA27
32K Words
C0000H to C7FFFH
SA28
32K Words
E0000H to E7FFFH
SA28
32K Words
C8000H to CFFFFH
SA29
32K Words
E8000H to EFFFFH
SA29
32K Words
D0000H to D7FFFH
SA30
32K Words
F0000H to F7FFFH
SA30
32K Words
D8000H to DFFFFH
SA31
16K Words
F8000H to FBFFFH
SA31
32K Words
E0000H to E7FFFH
SA32
4K Words
FC000H to FCFFFH
SA32
32K Words
E8000H to EFFFFH
SA33
4K Words
FD000H to FDFFFH
SA33
32K Words
F0000H to F7FFFH
SA34
8K Words
FE000H to FFFFFH
SA34
32K Words
F8000H to FFFFFH
MB84VA2106 Sector Architecture
MB84VA2107 Sector Architecture
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