DS05-50402-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
3 Stacked MCP (Multi-Chip Package) FLASH & FLASH & FCRAM
CMOS
64M (
16) FLASH MEMORY &
64M (
16) FLASH MEMORY &
32M (
16) Mobile FCRAM
TM
MB84VF5F5F4J2
-70
s
FEATURES
Power supply voltage of 2.7 V to 3.1 V
High performance
70 ns maximum access time (Flash_1 or Flash_2)
65 ns maximum access time (FCRAM)
Operating Temperature
30
C to +85
C
Package 107-ball FBGA
(Continued)
s
PRODUCT LINEUP
*: All of V
CC
f_1, V
CC
f_2, and V
CC
r must be the same level when either part is being accessed.
s
PACKAGE
Flash_1 or Flash_2
FCRAM
Supply Voltage (V)
V
CC
f_1*/V
CC
f_2* = 2.7 V to 3.1 V
V
CC
r* = 2.7 V to 3.1 V
Max Address Access Time (ns)
70
65
Max CE Access Time (ns)
70
65
Max OE Access Time (ns)
30
40
107-ball plastic FBGA
BGA-107P-M01
MB84VF5F5F4J2-70
2
1.
FLASH MEMORY_1 and FLASH MEMORY_2
Simultaneous Read/Write Operations (Dual Bank)
FlexBank
TM
*
1
Bank A : 8 Mbit (8 KB
8 and 64 KB
15)
Bank B : 24 Mbit (64 KB
48)
Bank C : 24 Mbit (64 KB
48)
Bank D : 8 Mbit (8 KB
8 and 64 KB
15)
Two virtual Banks are chosen from the combination of four physical banks.
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
Minimum 100,000 Program/Erase Cycles
Sector Erase Architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
HiddenROM (HiddenROM) Region
256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC Input Pin
At V
IL
, allows protection of "outermost" 2
8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
Ready/Busy Output (RY/BY_1 or RY/BY_2)
Hardware method for detection of program or erase cycle completion
Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode.
Low V
CC
f write inhibit
2.5 V
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
Please Refer to "MBM29DL64DF" Datasheet in Detailed Function.
(Continued)
MB84VF5F5F4J2-70
3
(Continued)
2.
FCRAM
TM
*
3
Power Dissipation
Operating : 25 mA Max
Standby : 100
A Max
Power Down Mode
Sleep : 10
A Max
NAP : 60
A Max
8M Partial : 70
A Max
Power Down Control by CE2r
Byte Write Control: LB(DQ
7
-DQ
0
), UB(DQ
15
-DQ
8
)
8 words Address Access Capability
*1: FlexBank
TM
is a trademark of Fujitsu Limited, Japan.
*2: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
*3: FCRAM
TM
is a trademark of Fujitsu Limited, Japan.
MB84VF5F5F4J2-70
5
s
PIN DESCRIPTION
Pin name
Input/
Output
Description
A
20
to A
0
I
Address Inputs (Common)
A
21
I
Address Input (Flash_1 & Flash_2)
DQ
15
to DQ
0
I/O
Data Inputs/Outputs (Common)
CEf_1
I
Chip Enable (Flash_1)
CEf_2
I
Chip Enable (Flash_2)
CE1r
I
Chip Enable (FCRAM)
CE2r
I
Chip Enable (FCRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY_1
O
Ready/Busy Output (Flash_1) Open Drain Output
RY/BY_2
O
Ready/Busy Output (Flash_2) Open Drain Output
UB
I
Upper Byte Control (FCRAM)
LB
I
Lower Byte Control (FCRAM)
RESET_1
I
Hardware Reset Pin/Sector Protection Unlock (Flash_1)
RESET_2
I
Hardware Reset Pin/Sector Protection Unlock (Flash_2)
WP/ACC
I
Write Protect / Acceleration (Flash_1 & Flash_2)
PE
I
Partial Enable (FCRAM)
N.C.
--
No Internal Connection
D.U.
--
Don't Use
V
SS
Power
Device Ground (Common)
V
CC
f_1
Power
Device Power Supply (Flash_1)
V
CC
f_2
Power
Device Power Supply (Flash_2)
V
CC
r
Power
Device Power Supply (FCRAM)
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