DS04-23004-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
CMOS
3 V Single Power Supply Audio
Interface Unit (AIU)
MB86435
s
DESCRIPTION
The FUJITSU MB86435 is an AIU (audio interface unit) LSI for +3 V single-power source digital telephone devices,
manufactured using CMOS process technology. The codec transmission filter characteristics meet G.712 standards,
and can handle input and output in A-Law,
-Law and linear conversion modes. The MB86435 also contains the
necessary DTMF, microphone and receiver amps for telephone devices.
s
FEATURES
+3 V single power supply
Low power consumption: muting settings for each operating mode
Normal operation : 6.0 mA
TYP
(speaker amp mute)
Tone generation
: 1.8 mA
TYP
(speaker amp mute)
Standby mode
: 0.5
A
TYP
On-chip codec filter meets G.712 standards
Selection of codec conversion methods (A-law,
-law, linear)
On-chip low-noise microphone amp (2-channel) (0 to 35 dB amplification)
On-chip receiver speaker amps (32
BTL type: 6.4 mW
MIN
)
On-chip tone speaker amp (25
BTL type: 10 mW
MIN
)
On-chip earphone speaker amps (32
single type: 2 mW
MIN
)
(Continued)
s
PACKAGE
64 pin, Plastic LQFP
(FPT-64P-M03)
2
MB86435
(Continued)
On-chip electronic volume gain adjustments (sending, receiving, tone)
On-chip accessory input/output circuits
DTMF generator function
Service tone generation
CMOS compatible input/output
s
PIN ASSIGNMENT
17
32
33
64
49
48
16
1
Index
(FPT-64P-M03)
(TOP VIEW)
3
MB86435
s
PIN DESCRIPTION
(Continued)
Pin No.
Symbol
I/O
A/D
Description
1
VRH
O
A
Bypass capacitor connector pin for the A/D D/A reference voltage generator
circuit. Place capacitor between VRH and CAG pins.
2
SGC
O
A
Bypass capacitor connector pin for the signal ground potential generator
circuit. Place capacitor between SGC and CAG pins.
3
VDDAC
P
A
Analog power supply pin for codec block. To be set within range 2.7 to 3.6 V.
6
SYNC
I
D
PCM codec send/receive synchronization signal input pin. Operating clock
frequency 8 kHz. CMOS interface. Constant H/L level signal will cause part of
codec block to power-down.
7
CLK
I
D
Send/receive PCM signal series bit rate setting input pin. Data rate for
-law,
A-law modes may be set to any level in the range 64 k to 3.152 MHz, and for
linear mode in the range 256 k to 3.152 MHz. Constant H or L level signal will
cause part of codec block to power-down. CMOS interface.
8
DIN
I
D
PCM signal input pin. This signal is picked up internally at the fall of the CLK
signal. CMOS interface.
9
DOUT
O
D
PCM signal output pin. Data is output in sync with the rise of the CLK signal.
After data output, loses PLL synchronization, and at power-down this signal is
fixed at H level. CMOS interface.
10
VDD
P
D
Digital power supply pin. To be set within range 2.7 to 3.6 V.
11
DG
G
D
Digital ground pin. To be set to 0V.
12
PSC0
I
D
Power-down control signal input pin.
CMOS interface. Used with PSC1,2
pins for power-down settings.
PSC 2 1 0
0 0 0 Full power-down
1 0 0 V
REF
operating
-- 1 0 Tone operating
-- -- 1 All operations available
(--: value not determined)
13
PSC1
I
D
Power-down control signal input pin.
CMOS interface. Used with PSC0,2
pins for power-down settings.
14
PSC2
I
D
Power-down control signal input pin.
CMOS interface. Used with PSC0,1
pins for power-down settings.
15
SRD
I
D
9-bit serial data input pin. CMOS interface. Data is written at the rise of the
signal from this pin.
16
SRC
I
D
Clock input pin for 9-bit serial data writing. CMOS interface. Data is written at
the rise of this pin.
17
STB
I
D
Serial data latch strobe signal. Data is latched by the L level signal. CMOS
interface.
18
XPRST
I
D
Digital reset signal input pin. CMOS interface. L level: internal latch initialization
H level: normal operation
19
LO0
O
D
External control latch output pin. Outputs value D
0
of address 1000. CMOS
interface.
20
LO1
O
D
External control latch output pin. Outputs value D
1
of address 1000. CMOS
interface.
4
MB86435
(Continued)
Pin No.
Symbol
I/O
A/D
Description
21
LO2
O
D
External control latch output pin. Outputs value D
2
of address 1000. CMOS
interface.
22
LO3
O
D
External control latch output pin. Outputs value D
3
of address 1000. CMOS
interface.
23
TCLK
I
D
Tone generator clock input pin. Can be used as a tone CLK signal by using
address 1110 D4D3 to subdivide the internal clock signal by factors of 1/1,
1/2, 1/4. CMOS interface.
24
TONC
I
D
Tone generator cycle control input pin. CMOS interface. Hlevel signal
outputs tone.
25
LED
O
D
Ring LED control output pin. CMOS interface.
26
DSCK
I/O
A
Can be connected to EXSD or TAUD by switching bus.
27
EXSD
I/O
A
Can be connected to DSCK or TAUD by switching bus.
28
TAUD
I/O
A
Can be connected to EXSD or DSCK by switching bus.
29
DSDT
I
A
Can be connected to RAUD by switching bus.
30
TONEO
O
A
Tone signal output pin.
31
RAUD
O
A
Output pin for external speaker, or audio test signal. Can be connected to
DSDT by switching paths.
32
VDDSP1
P
A
Speaker amp power supply pin. To be set within range 2.7 to 3.6 V.
33
JEAR
O
Earphone speaker amp output pin. Capable of 2 mW output at 32
load.
34
XEAR
O
A
Receiver speaker amp output pin. Internally connected to EAR and BTL.
Maximum output of 6.4 mW can be obtained at 32
load by connecting
speaker between EAR and XEAR.
35
EAR
O
A
Receiver speaker amp output pin. Connected to XEAR and BTL.
36
SPG1
G
A
Speaker amp ground pin. To be set to 0 V.
37
SPG2
G
A
Speaker amp ground pin. To be set to 0 V.
38
XTONE
O
A
Speaker amp tone output pin. Internally connected to TONE and BLT.
Maximum output of 10 mW can be obtained at 25
load by connecting
speaker between TONE and XTONE.
39
TONE
O
A
Speaker amp tone output pin. When speaker amp is not used for tone,
TONE should be shorted to IMTON.
40
IMTON
I
A
Speaker drive inverted () signal input pin. Can be used to adjust gain by
connecting resistance to TONE and IMTON.
41
VDDSP2
P
A
Speaker amp power supply pin. To be set within range 2.7 to 3.6 V.
42
BBI
O
A
AMP3 output pin. Should be included in HPF together with IM3, to prevent
DC offset from entering speakers.
43
IM3
I
A
AMP3 inverted () signal input pin.
44
BTO
O
A
Receiving volume adjustment circuit output pin.
5
MB86435
(Continued)
Pin No.
Symbol
I/O
A/D
Description
45
OP2
O
A
AMP2 output pin. If AMP2 is not used, IM2 should be shorted to OP2.
46
IM2
I
A
AMP2 inverted () signal input pin. Can form a circuit with OP2 to add
sidetone or tone. Melody circuits, if used, can alsobe connected here.
47
OP1
O
A
AMP1 output pin. Can form a circuit with IM1 to include LPF or HPF in
receiving block. If AMP1 is not used, IM1 should be shorted to OP1.
48
IM1
I
A
AMP1 inverted () signal input pin.
49
PTBO
O
A
PCM receiver output pin.
50
BAG
G
A
Analog ground pin for sending, receiving blocks. To be set to 0 V.
51
VDDAB
P
A
Analog power supply pin for sending, receiving blocks. To be set within
range 2.7 to 3.6 V.
52
XJMIC
I
A
Microphone amp (2) non-inverted (+) signal input pin.
53
JMIC
I
A
Microphone amp (2) inverted () signal input pin.
54
JMICO
O
A
Microphone amp (2) output pin.
55
XMICI
I
A
Microphone amp (1) non-inverted (+) signal input pin.
56
MIC
I
A
Microphone amp (1) inverted () signal input pin.
57
MICO
O
A
Microphone amp (1) output pin.
58
SGO
O
A
Sending block signal ground potential output pin. Buffers SGC voltage.
59
BBO
O
A
Sending analog signal output pin.
62
BTPI
I
A
PCM ENCODE block input OP amp negative input pin.
63
BTPO
O
A
PCM ENCODE block input OP amp output pin.
64
CAG
G
A
Analog ground pin for codec block. To be set to 0 V.
4, 5,
60, 61
NC
--
--
Not connected. To be left open.
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