DS04-23005-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
CMOS
3 V Single Power Supply Audio
Interface Unit (AIU)
MB86437
s
DESCRIPTION
The FUJITSU MB86437 is an AIU (audio interface unit) LSI for +3 V single-power source digital telephone devices,
manufactured using CMOS process technology. The codec transmission filter characteristics meet G.712 standards,
and can handle input and output in A-Law,
-Law and linear conversion modes. The MB86437 also contains the
necessary DTMF, microphone and receiver amps for telephone devices.
s
FEATURES
+3 V single power supply
Low power consumption: muting settings for each operating mode
Normal operation : 5.0 mA
TYP
Standby mode
: 0.5
A
TYP
On-chip codec filter meets G.712 standards
Selection of codec companding law (A-law,
-law, 14 bit linear)
On-chip low-noise microphone amp (2-channel) (0 to 35 dB amplification)
On-chip receiver speaker amps (32
BTL type: 10 mW
MIN
)
On-chip earphone speaker amps (32
single type: 5 mW
MIN
)
(Continued)
s
PACKAGE
48 pin, Plastic LQFP
(FPT-48P-M05)
2
MB86437
(Continued)
On-chip electronic volume gain adjustments (sending, receiving, tone)
On-chip accessory input/output circuits
DTMF generator function
Service tone generation
CMOS compatible input/output
s
PIN ASSIGNMENT
Index
13
1
24
48
37
36
12
25
(FPT-48P-M05)
(TOP VIEW)
3
MB86437
s
PIN DESCRIPTION
(Continued)
Pin No.
Symbol
I/O
A/D
Description
1
SWI
I/O
A/D
I/O pin for analog switch SW12
The standard on resistance for the analog switch is 500
.
2
SWO
I/O
A/D
I/O pin for analog switch SW12
Connected to pin 1 via switch SW12.
3
RAUD
O
A
Output pin for the received audio signal to the external speaker or for
testing.
4
VD1
P
A
Power supply pin for reception. Supply a voltage between 2.7 V and 3.6 V.
5
JEAR
O
A
Amplifier output pin for the earphone speaker.
Can output 5 mW for a 32
load.
6
EAR
O
A
Amplifier output pin for the receiver speaker. Internal BTL connection to
XEAR. The maximum output for a 32
load between EAR and XEAR is 10
mW.
7
XEAR
O
A
Amplifier output pin for the receiver speaker.
BTL connection to XEAR.
8
VS1
G
A
Ground pin for reception. Set to 0 V.
9
TONE
O
A
Amplifier output pin for the tone speaker. The output can be set to normal
mode, ground, or high impedance.
10
TBO
O
A
AMP4 output pin. Pair high pass filter with TBI so that there is no DC offset
at the speaker.
11
TBI
I
A
AMP4 inverted () input pin
12
PTBO
O
A
PCM reception, tone addition output
13
MDI
I
A
Pin used to add an analog input signal to the tone section or apply an
envelope to the tone. Required functions can be selected by controlling
SW16. Setting SW16 off sets the input impedance to approximately 140 k
and setting SW16 on sets the input impedance to approximately 210 k
.
14
VD2
P
A
Power supply pin for reception. Supply a voltage between 2.7 V and 3.6 V.
15
DSCK
I/O
A
Can be connected to EXSD and TAUD by path switching.
16
EXSD
I/O
A
Can be connected to DSCK and TAUD by path switching.
17
TAUD
I/O
A
Can be connected to EXSD and DSCK by path switching.
18
MICO
O
A
Output pin for mike amplifier [1]
19
MIC
I
A
Inverted input pin () for mike amplifier [1]
20
XMIC
I
A
Non-inverted input pin (+) for mike amplifier [1]
21
JMIC
I
A
Inverted input pin () for mike amplifier [2]
22
JMICO
O
A
Output pin for mike amplifier [2]
23
VS2
G
A
Ground pin for transmission. Set to 0 V.
24
SGC
O
A
Pin for connecting the bypass capacitor for the signal ground potential
generation circuit.
Connect a capacitor between SGC and VS2.
25
VS4
G
A
Ground pin for A/D and D/A. Set to 0 V.
26
SGI
I
A
General-purpose amplifier. To use, connect to SGO.
4
MB86437
(Continued)
Pin No.
Symbol
I/O
A/D
Description
27
SGO
O
A
General-purpose amplifier output pin. The signal can also go to JEAR via
SW15.
28
STA
O
A
Transmission analog signal output via SW1. Connect to AMP4 when
performing sidetone addition for reception. The standard on resistance for
the analog switch is 500
.
29
BBO
O
A
Transmission analog signal output pin
30
BTPI
I
A
Inverted input pin () for the PCM ENCODE section input op-amp
31
BTPO
O
A
Output pin for the PCM ENCODE section input op-amp
32
VD3
P
D
Power supply pin for transmission. Supply a voltage between 2.7 V and 3.6 V.
33
DIN
I
D
PCM signal input pin. The signal is clocked in on the falling edge of CLK.
CMOS interface.
34
DOUT
O
D
PCM signal output pin. The signal is clocked out on the rising edge of CLK.
After data output, becomes fixed at the "H" level if PLL synchronization is
lost or a power-down occurs. CMOS interface.
35
SYNC
I
D
Transmission and reception sync signal input pin for the PCM CODEC
section. The operating clock frequency is 8 kHz. CMOS interface.
Fixing at "H" or "L" causes part of the CODEC section to power-down.
36
CLK
I
D
Input pin for setting the bit rate for the transmission and reception PCM
signals. The data rate can be selected from 64 kHz to 3.152 MHz for
-law
or A-law operation, or from 128 kHz to 3.152 MHz for linear operation. Fixing
at "H" or "L" causes part of the CODEC section to power-down. CMOS
interface.
37
TCLK
I
D
Clock input pin for tone generation. The internal clock divided by one or two
(set by D
4
D
3
of address 01110) can be used as the tone CLK. CMOS
interface.
38
VD4
P
D
Digital power supply pin. Supply a voltage between 2.7 V and 3.6 V.
39
SRD
I
D
10-bit serial data input pin. CMOS interface. This data sets the electronic
volume, path, and tone settings.
40
SRC
I
D
Write clock input pin for the 10-bit serial data. CMOS interface.
SRD is clocked in the rising edge.
41
STB
I
D
Strobe signal for the serial data latch. Latches on "L". CMOS interface.
42
XPRST
I
D
Reset signal input pin for the digital circuits. CMOS interface.
L: Initialize internal latches. H: Normal
43
LO0
O
D
Latch output pin for external control. Outputs D
0
of address 01000. CMOS
interface.
44
LO1
O
D
Latch output pin for external control. Outputs D
1
of address 01000. CMOS
interface.
45
LO2
O
D
Latch output pin for external control. Outputs D
2
of address 01000. CMOS
interface.
46
LO3
O
D
Latch output pin for external control. Outputs D
3
of address 01000. CMOS
interface.
47
PS
I
D
Power-down control signal input pin. CMOS interface. Powers down all
circuits regardless of register settings.
48
VS3
G
D
Digital ground pin. Set to 0 V.
5
MB86437
s
BLOCK DIAGRAM
+
+
+
+
+
+
+
+
+
SGO
(27)
AO
AMP5
SGC
SGC
SGI
(26)
SGC (24) BTPO (31) BTPI (30)
BBO (29)
STA (28)
VS 1 (8)
VS 2 (23)
VS 3 (48)
VS 4 (25)
DOUT
(34)
MDI
(13)
TBO
(10)
TBI
(11)
TCLK
(37)
MICO
(18)
MIC
(19)
XMIC
(20)
JMICO
(22)
TAUD
(17)
EXSD
(16)
DSCK
(15)
PTBO
(12)
SWI
(1)
SWO
(2)
RAUD
(3)
EAR
(6)
XEAR
(7)
JEAR
(5)
TONE
(9)
XPRST
(42)
LO0
(43)
LO1
(44)
LO2
(45)
LO3
(46)
PS
VREF
generator
VREF generator block
A/D
BPF
512 K
7 to 8 dB
1 dB step
AMP4
EV0
(Invert)
4bit
7 to 8 dB
1 dB step
Microphone amp
Earphone speaker drive block
SGC
0 dB (RST)
SGC
0 dB (RST)
0 dB
SW3
SGC
SW4
SW10
SW12
SW13
SW8b
SW8a
SW6a
SW6b
SGC
SGC
PD
0 dB
0 dB
0 dB
PD
0 dB
PD
SGC
SGC
PLL
(1)
JMIC
(21)
SW5
SW11
SGC
0 dB (RST)
+
AMP3
EV5
3bit
18 to 11dB
1 dB step
EV3
(Invert)
4bit
8 to 23 dB
1 dB step
15 dB
15 dB
(RST)
14 dB
(RST)
EV4
3bit
30 to 0 dB
5 dB step
15 dB
(RST)
DUAL
TONE
SINGLE: 14 dBv
DUAL: 14 dBv
ATT
SW16
+
EV2
(Invert)
3bit
D/A
LPF
EV1
4bit
EV6
3bit
14 to 0 dB
2 dB step
8 dB (RST)
+
SW7b
SW15
SW7a
SGC
PD
0 dB
EV7
2bit
9 to 0 dB
3 dB step
3 dB (RST)
+
SW9b
SW14
SW9a
SGC
PD
0 dB
SW9c
0 dB
EV8
1bit
EV9
1bit
6 dB (RST)
0 dB, 6 dB
10 dB (RST)
0 dB, 10 dB
AO
CONTROL
LOGIC
P-
SAVE
VD1
VD2
VD3
VD4
DIN
(33)
SYNC
(35)
CLK
(36)
0 dB
SW 2
Tone generator
block
AMP2
Codec block
SW1
Transmitting block
15 to 15 dB, 5 dB step
Receiver speaker drive block
Receiving
block
Tone speaker drive block
SRD
(39)
SRC
(40)
STB
(41)
AMP1
(47)
(4)
(14)
(32)
(38)
(2)
Microphone amp
Control
block
: Digital input
: Digital output
: Analog input
: Analog output
: Input/output
: V
DD
: GND
Electronic volume:
(RST) indicates the value for reset
(inverting) indicates the inverted phase
between input and output.
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