Product Flyer
December 1996
MB86689A
Version 2.05
Address Translation Controller (ATC)
FML/NPD/ATC/FL/1206
Copyright 1996 Fujitsu Microelectronics Limited
Page 1 of 6
The Fujitsu MB86689A Address Translation Controller
provides an autonomous high speed translation function
of ATM cell header information in real time at 155Mb/s.
It replaces ATM virtual path identifiers (VPI) and virtual
channel identifiers (VCI) and can append a 1-3 byte rout-
ing tag if required.
The device can be used with the MB86683B Network
Termination Controller (NTC) or placed directly in the cell
stream. When used with the NTC, ATM cell headers are
received and transmitted through a dedicated port. When
used in the cell stream, ATM cells are received and trans-
mitted through 8-bit parallel cell stream interfaces.
The ATC is ideally suited to UNI and NNI applications in
ATM hubs, switches and adapter cards.
FEATURES
1024 entry content addressable memory.
Full 28 bit comparison for each entry.
Selectable VPI and VCI mask for each entry.
Supports UNI and NNI cell header formats.
Supports multiple matches (NTC Mode only).
Supports flexible tag sizes.
Supports the provision of translation data suitable for Usage Parameter Control.
Supports CLP and congestion indication and removal for each entry.
Multiple ATCs can be cascaded to support larger translation tables (NTC mode only).
Translation is completed in less than one cell period at 155Mb/s.
Entries can be updated on-the-fly without affecting the translation process.
JTAG pins compliant to IEEE1149.1 are provided.
Fabricated in 0.8 micron CMOS technology with CMOS/TTL compatible I/O and single +5V power
supply.
PLASTIC PACKAGE
QFP-80
December 1996Version 2.05
FML/NPD/ATC/FL/1206
MB86689A Address Translation Controller (ATC)
Copyright 1996 Fujitsu Microelectronics Limited
Page 2 of 6
General
A top level logical block diagram of the ATC is shown in Fig. 1 above. The main
modules are as shown and are described below.
The ATC provides high speed translation (<1 cell period at 155Mbps) of header
information for 1024 entries, each entry being associated with up to 3 bytes
routing tag. The ATC also provides two interface modes; NTC Interface mode
and Cell Stream Interface mode. Fig. 2 on page 4 illustrates how the ATC may
be configured when the NTC Interface mode is selected and the alternative
mode of configuration - Cell Stream Interface mode - enables in-line address
translation.
Data Formatters
The Input Data Formatter is responsible for removing an incoming cell's Virtual
Path and Virtual Channel Identifiers (VPI and VCI) and for providing this data as
a comparend to the ATC's Content Addressable Memory Array (CAM Array).
The Output Data Formatter is responsible for providing the newly-translated
VPI/VCI data and routing tags for the cell awaiting transmission.
Output
Data
Formatter
CAM
Array
Controller
MPU Interface Controller
Cell Stream Interface Controller
Cascade Interface
Processor
Interface
NTC
Interface
Cell Stream Interface
Input
Data
Formatter
Fig. 1 - ATC Block Diagram
Output
RAM
JTAG Interface
JTAG
December 1996Version 2.05
FML/NPD/ATC/FL/1206
MB86689A Address Translation Controller (ATC)
Copyright 1996 Fujitsu Microelectronics Limited
Page 3 of 6
CAM Array
On receiving the 28-bit VPI/VCI comparend, the ATC compares the data against
each active match entry in the CAM Array.
Output RAM
If a match is found between the 28-bit VPI/VCI comparend and an entry within
the CAM Array then the ATC activates both the Output RAM and Output Data
Formatter. The Output RAM will contain the newly-translated VPI/VCI data and
up to 3 bytes of routing tag information.
In NTC mode of operation, if more than one match is detected for the same input
data, then the ATC will sequentially output associated RAM data for each
match. Multiple matches are not supported within Cell Stream Interface mode.
NTC Interface
This interface allows the ATC to communicate directly with the Network
Termination Controller. Transfer of information is across a dedicated bi-
directional databus controlled via a 4-wire handshake mechanism. Only header
information is transferred across this interface.
Cascade Interface
In NTC Mode, this 3-bit interface allows 2 ATCs to be connected together to
form a larger translation table. Each ATC will perform its search in parallel hence
incurring no increase in search time. Larger translation tables can be
implemented with minimal glue logic.
Cell Stream Interface
This interface allows the ATC to buffer and process entire ATM cells received
across a 9-bit cell based interface.
Processor Interface
A 16-bit bi-directional Microprocessor interface allows entries in the CAM Array
and Input RAM to be updated on the fly without affecting the translation process.
UPC Port
On detecting a match, the 4-bit UPC port provides a 2-bit ATC code and a 10-
bit output RAM address.
JTAG
The ATC provides boundary scan test circuitry compliant with IEEE 1149.1
(JTAG). The ATC's JTAG circuitry permits easier board level testing to be
carried out by allowing the signal pins on the device to form a serial scan chain
around the device. JTAG test modes are controlled by accessing an internal test
access port controller, which is in turn controlled by the 4 provided test access
ports.
December 1996Version 2.05
FML/NPD/ATC/FL/1206
MB86689A Address Translation Controller (ATC)
Copyright 1996 Fujitsu Microelectronics Limited
Page 4 of 6
MB86687A
ALC
MB582A/583A
Transceiver
Host CPU
User Network Interface (UNI)
ATM Terminal Equipment
MB86683B
NTC
ATC
Switch
Matrix
UNI
MB582A/583A
Transceiver
ATM Switch - UNI Port
MB86687A
ALC
ATC
Host CPU
ATM Switch - Signalling controller
Switch
Matrix
ATC
MB86683B
NTC
ATC
Fig. 2 - Example Configurations
December 1996Version 2.05
FML/NPD/ATC/FL/1206
MB86689A Address Translation Controller (ATC)
Copyright 1996 Fujitsu Microelectronics Limited
Page 5 of 6
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit.
Microprocessor
Interface
Mode
Select
Inputs
NTC Interface
Cell
Stream
Interface
Clock
Cascade Interface
NTCD0-7
ATC_DAV
ATC_RFD
NTC_RFD
NTC_DAV
CLK
IPSOC
IPD0 - IPD7
OPD0 - OPD7
OPSOC
MB86689A
ATC
RESET
DREQ
RD
WR
CS
D0 - D15
CRFDI
CDAVI
CRFDO
TSIZE0
TSIZE1
HEC
CSMODE
OPCTL
JTAG
TDI
TDO
TMS
TCK
UPC Port
FTM
TAGSEL
UPCO_0-UPCO_3
TEST
Fig. 3 - MB86689A I/O Block Diagram
PDF 
ZIP