FEATURES
High-performance packet buffer architecture pipe-
lines data for highest throughput
20 Mbyte/second data transfer rate to/from the system
bus
on-chip buffer controller manages pointers, reduces
software overhead
Efficient, configurable two bank transmit buffer and
ring receive buffer
Bus-compatible with most popular microprocessors,
including RISC
Complies with international standards for Ethernet,
ISO/ANSI/IEEE 8802-3
High-speed burst and single transfer DMA
64-element hash table for multicast address filtering
High-speed, low-power CMOS technology
Power down mode reduces power dissipation for
battery-powered equipment
Available in 100-pin plastic quad flat package
GENERAL DESCRIPTION
The MB86960 Network Interface Controller with
Encoder/Decoder (NICE
TM
) is a high-performance,
highly integrated monolithic device which incorporates
both network controller, complete with buffer manage-
ment, and Manchester encoder/decoder. It allows
implementation of a 7-chip solution for an Ethernet
interface when used with either of Fujitsu's bus interface
chips, the MB86953 for PC/XT/AT or the MB86954 for
Micro Channel
TM
, and either of Fujitsu's transceiver
chips, the MBL8392A coaxial transceiver or MB86962
10BASE-T twisted-pair transceiver.
The unique buffer management architecture of the
MB86960 allows packet data to access a buffer memory
area from the host and from the network media
simultaneously, with virtually no interaction. The
network controller updates all receive and transmit
pointers internally, thus reducing the software overhead
required to control these operations, resulting in superior
benchmark speed and application performance. The
NICE device has a partitionable 2, 4, 8, or 16 kilobyte,
two-bank, transmit buffer which allows multiple data
packets to be "chained" together and transmitted to the
network from a single transmit command, thus allowing
greater design flexibility and throughput. Receive
packets are captured in a ring buffer which can be
configured in various sizes from 4 to 62 kilobytes,
depending on memory equipped and amount used for the
transmit buffer.
Possible configurations for the system bus interface
include I/O mapping, memory mapping and DMA
access, or a combination of these. With a 20 Mbyte/sec
bandwidth, the NICE system bus interface allows you to
use the full throughput capacity of its unique packet
buffering architecture. The NICE controller's selectable
bus modes provide both big- and little-endian byte
ordering, permitting an efficient data interface with most
microprocessors and higher-level protocols.
Implemented in Fujitsu's high-speed, low-power CMOS
process, the MB86960 is supplied in a 100-pin plastic
quad flat package for surface mounting.
PIN CONFIGURATION
31
50
80
51
100
81
1
30
100PIN
PLASTIC QUAD
FLAT PACK
(PQFP)
TOP VIEW
APRIL1993
DATA SHEET
MB86960
NETWORK INTERFACE CONTROLLER
with ENCODER/DECODER (NICE)
MB86960
PIN ASSIGNMENTS AND DESCRIPTIONS
Supplied in a 100-pin plastic quad flat pack, the NICE
controller presents a small foot-print to the board design,
and is surface-mountable with its gull-wing leads. See Pin
Configuration and Pin Assignments for the pin
numbering.
26 DREQ
O
27 DACK
I
28 V
CC
--
29 RD
I
30 WE
I
31 RESET
I
32 BD0
B
33 BD1
B
34 BD2
B
35 BD3
B
36 BD4
B
37 BD5
B
38 BD6
B
39 BD7
B
40 GND
--
41 BD8
B
42 BD9
B
43 BD10
B
44 BD11
B
45 BD12
B
46 BD13
B
47 BD14
B
48 BD15
B
49 BOE
O
50 BWE
O
1 SD11
B
2 SD10
B
3 V
CC
--
4 GND
--
5 SD9
B
6 SD8
B
7 CS
I
8 BHE
I
9 SW/SB
O
10 SA0
I
11 SA1
I
12 SA2
I
13 SA3
I
14 RDY(RDY)
O
15 GND
--
16 SD0
B
17 SD1
B
18 SD2
B
19 SD3
B
20 SD4
B
21 SD5
B
22 SD6
B
23 SD7
B
24 EOP(EOP)
I
25 INT
O
PIN
NO. PIN NAME
TYPE
51 BCS0
O
52 BCS1
O
53 V
CC
--
54 BA0
O
55 BA1
O
56 BA2
O
57 BA3
O
58 BA4
O
59 BA5
O
60 BA6
O
61 BA7
O
62 BA8
O
63 BA9
O
64 BA10
O
65 GND
--
66 BA11
O
67 BA12
O
68 BA13
O
69 BA14
O
70 BA15
O
71 TEN
B
72 TXD
B
73 GND
--
74 TXDATA
O
75 TXDATA+
O
Note:
Dual function pins have two
names with the second in
parentheses ( ).
B = Bidirectional I/O
I
= Standard Input
O = Totem Pole Output
PIN
NO. PIN NAME
TYPE
PIN
NO. PIN NAME
TYPE
76 X1
I
77 X2
O
78 V
CC
--
79 GND
--
80 TCK
B
81 RXDATA
I
82 RXDATA+
I
83 COL
I
84 COL+
I
85 V
CC
--
86 LBC
B
87 AC/DC
I
88 RCK
B
89 CKOUT
O
90 GND
--
91 RXD
B
92 COL
B
93 CRS
B
94 RDYPOL
I
95 CNTRL
O
96 RMT
O
97 SD15
B
98 SD14
B
99 SD13
B
100 SD12
B
PIN
NO. PIN NAME
TYPE
PIN ASSIGNMENTS
MB86960
BLOCK DIAGRAM
BUFFER
PORT
REGISTERS
STATUS &
CONTROL
REGISTERS
HASH
TABLE
READ/WRITE
DMA
SYSTEM
INTERFACE
SW/SB
RMT
CNTRL
RESET
RDYPOL
RDY (RDY)
INT
EOP (EOP)
DREQ
DACK
CS
WE
RD
BHE
SD00
SA0
COL
CRS
RCK
RXD
LBC
TEN
TCK
TXD
X1
X2
AC/DC
COL+
COL
RXDATA+
BUFFER
CONTROLLLER
RECEIVER
MANCHESTER
ENCODER/
DECODER
TRANSMITTER
NETWORK
CONTROLLER
BSC1
BCS0
BD0 BD15
BA0 BA15
BWE
BOE
CONTROL
SA3
SD15
CONTROL
INTERNAL
ADDRESS
BUS
INTERNAL DATA BUS
RXDATA
TXDATA+
TXDATA
Rx
DATA
Tx
DATA
CKOUT
MB86960
PIN DESCRIPTIONS
System Bus Interface Pins
SYMBOL
TYPE
DESCRIPTION
RESET
I
HARDWARE RESET: Active high. A minimum pulse of 300 nanoseconds in duration is required.
This pin resets NICE's internal pointers and registers to the appropriate state.
Note: NICE must be reset after power start before using.
RDY (RDY)
O
READY: This output is asserted to indicate to the host that NICE is ready to complete the requested
read of write operation. It will also be asserted if the device is unable to respond to the request for a
read or write within 2.4 microsecond, In that case, NICE will also assert INT and the bus read error
status bit, DLCR1<6>, or bus write error status bit DLCR<0>. RDY(RDY) may be an active low or
active high signal as determined by RDYPOL, pin 94. If RDYPOL is a "1", RDY(RDY) will be active
high. If RDYPOL is tied to a "0" RDY(RDY) will be an active low signal.
RDYPOL
I
READY POLARITY SELECT: Control input to select the polarity of RDY(RDY), pin 14. When this
pin is tied high, RDY(RDY) will be active high. If RDYPOL is tied low, RDY(RDY) will be an active
low signal.
WE
I
WRITE: The WE pin is an active low input that enables a write operation form the host system to the
buffer memory port or to internal registers selected by system address inputs SA0-3.
RD
I
READ: Active low input specifies that the current transfer between NICE and the host system is a
read from one of NICE's internal registers or its data port as selected by SA0-3.
CS
I
CHIP SELECT: This active low input signal is the chip select for NICE.
BHE
I
BYTE HIGH ENABLE: Active Low. This is the byte/word control line. It is used only when NICE is
configured for a 16-bit data bus by the SB/SW bit of DLCR6. It allows word, upper byte only or lower
byte only transfers. The address select pin SA0 is used with BHE for byte or word transfers. as
follows.
SB/SW
BHE
SA0
FUNCTION
0
0
0
Word transfer
0
0
1
Byte transfer on upper half of data bus (SD15-8)
0
1
0
Byte transfer on lower half of data bus (SD7-0)
0
1
1
Reserved
1
X
X
Byte transfer (SD7-0)
INT
O
INTERRUPT: Active low. Indicates that NICE requires host system attention after successful
transmission or reception of a packet, or if any error condition occur, if an EOP (end of process)
signal from the host occurs after the completion of the DMA cycle. The Interrupt signal is maskable
and can be disabled by writing a 0 to the appropriate mask bit.
EOP(EOP)
I
END OF PROCESS: Indicates to NICE that the DMA transfer is finished. When the host DMA
controller asserts EOP(EOP), further assertion of NICE's bus request output. DREQ, will be
discontinued.
Note:
Dual function pins have two
names with the second in
parentheses ( ).
B = Bidirectional I/O
I
= Standard Input
O = Totem Pole Output
MB86960
PIN DESCRIPTIONS
System Bus Interface Pins (continued)
SYMBOL
TYPE
DESCRIPTION
CNTRL
O
CONTROL: This pin is the complement of the register bit CNTRL, DLCR4<2>. It is used to control
external functions.
RMT
O
REMOTE CONTROL PACKET: When DLCR5<2> is set high, this pin follows the RMT 0900H bit
(DCLR1<4>) which indicates that a complete special packet with type field= 0900H has been
received. This is intended for use as a remotely-controlled hardware function from other nodes in
the network.
DREQ
O
DMA REQUEST: Issued to the DMA controller to indicate that NICE has data available to be read in
its receive buffer, of is ready to accept data into its transmit buffer.
DACK
I
DMA ACKNOWLEDGE: Active low, indicate that the DMA controller is ready to transfer data
between the host system and NICE's buffer memory through BMPR8.
SA<3:0>
I
SYSTEM ADDRESS LINES: Specify which of the internal registers of ports of NICE is selected for
read/write operations.
SD<15:0>
B
SYSTEM DATA BUS: All data, command and status transfers between the host system and NICE
take place over the bidirectional, 3-state, bus. The direction of the transfer is controlled by RD and
WE. The register or buffer port being accessed is selected by a combination of DACK (if active,
selecting the Buffer Port), of the address pins SA3-0 and register bank select bits REG BANK 1 and
REG BANK 0, DLCR7<3:2>. The portion of the data bus over which the transaction occurs is
controlled by SB/SW, BHE, and SA0.
SW/SB
O
SYSTEM WORD/SYSTEM BYTE CONFIGURATION: This signal output reflects the inverse of
DCLR6<5>, SB/SW. If SW/SB=1, the system interface is configured for word transfers, If
SW/SB=0, the system interface is configured for byte-wide transfer on SD7-0, the lower byte.
Note:
Dual function pins have two
names with the second in
parentheses ( ).
B = Bidirectional I/O
I
= Standard Input
O = Totem Pole Output
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