DS05-20873-4E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
32M (4M
8/2M
16) BIT
Dual Operation
MBM29DL32XTD/BD
-80/90/12
s
FEATURES
0.33
m Process Technology
Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
Single 3.0 V read, program, and erase
Minimizes system level power requirements
(Continued)
s
PRODUCT LINE UP
s
PACKAGES
Part No.
MBM29DL32XTD/MBM29DL32XBD
Ordering Part No.
V
CC
= 3.3 V
+0.3 V
0.3 V
80
--
--
V
CC
= 3.0 V
+0.6 V
0.3 V
--
90
12
Max. Address Access Time (ns)
80
90
120
Max. CE Access Time (ns)
80
90
120
Max. OE Access Time (ns)
30
35
50
48-pin plastic TSOP (I)
(FPT-48P-M19)
48-pin plastic TSOP (I)
(FPT-48P-M20)
57-ball plastic FBGA
(BGA-57P-M01)
Marking Side
Marking Side
Em\edded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MBM29DL32XTD/BD
-80/90/12
2
(Continued)
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)
57-ball FBGA (Package suffix: PBT)
Minimum 100,000 program/erase cycles
High performance
80 ns maximum access time
Sector erase architecture
Eight 4K word and sixty-three 32K word sectors in word mode
Eight 8K byte and sixty-three 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
Low V
CC
write inhibit
2.5 V
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
Sector Group Protection Set function by Extended sector group protection command
Fast Programming Function by Extended Command
Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
In accordance with CFI (Common Flash Memory Interface)
MBM29DL32XTD/BD
-80/90/12
3
s
GENERAL DESCRIPTION
The MBM29DL32XTD/BD are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M
words of 16 bits each. The MBM29DL32XTD/BD are offered in a 48-pin TSOP(I) and FBGA Package. These
devices are designed to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and
5.0 V V
CC
are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
MBM29DL32XTD/BD are organized into two banks, Bank 1 and Bank 2, which can be considered to be two
separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu's
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is
simultaneously taking place on the other bank.
In the MBM29DL32XTD/BD, a new design concept is implemented, so called "Sliding Bank Architecture". Under
this concept, the MBM29DL32XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
The standard MBM29DL32XTD/BD offer access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29DL32XTD/BD are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29DL32XTD/BD are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL32XTD/BD are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu's Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29DL32XTD/BD memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
MBM29DL32XTD/BD
-80/90/12
4
Table 1 MBM29DL32XTD/BD Device Bank Divisions
Device
Part Number
Organization
Bank 1
Bank 2
Megabits
Sector sizes
Megabits
Sector sizes
MBM29DL321TD/BD
8/
16
0.5 Mbit
Eight 8K byte/4K word
31.5 Mbit
Sixty-three
64K byte/32K word
MBM29DL322TD/BD
4 Mbit
Eight 8K byte/4K word,
seven 64K byte/32K word
28 Mbit
Fifty-six
64K byte/32K word
MBM29DL323TD/BD
8 Mbit
Eight 8K byte/4K word,
fifteen 64K byte/32K word
24 Mbit
Forty-eight
64K byte/32K word
MBM29DL324TD/BD
16 Mbit
Eight 8K byte/4K word,
thirty-one 64K byte/
32K word
16 Mbit
Thirty-two
64K byte/32K word
MBM29DL32XTD/BD
-80/90/12
5
s
PIN ASSIGNMENTS
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
19
A
20
WE
RESET
N.C.
WP/ACC
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard Pinout
Reverse Pinout
TSOP(I)
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
WP/ACC
N.C.
RESET
WE
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
(Marking Side)
(Marking Side)
FPT-48P-M19
FPT-48P-M20
MBM29DL32XTD/BD
-80/90/12
6
(Continued)
Regarding additional No Internal Connection balls, please contact a Fujitsu representative for more
information.
A1
A
3
A2
A
7
A3
RY/BY
A4
WE
A5
A
9
A6
A
13
B1
A
4
B2
A
17
B3
WP/ACC B4
RESET
B5
A
8
B6
A
12
C1
A
2
C2
A
6
C3
A
18
C4
N.C.
C5
A
10
C6
A
14
D1
A
1
D2
A
5
D3
A
20
D4
A
19
D5
A
11
D6
A
15
E1
A
0
E2
DQ
0
E3
DQ
2
E4
DQ
5
E5
DQ
7
E6
A
16
F1
CE
F2
DQ
8
F3
DQ
10
F4
DQ
12
F5
DQ
14
F6
BYTE
G1
OE
G2
DQ
9
G3
DQ
11
G4
V
CC
G5
DQ
13
G6
DQ
15
/A
-1
H1
V
SS
H2
DQ
1
H3
DQ
3
H4
DQ
4
H5
DQ
6
H6
V
SS
A3
A1
A2
A4
A6
A5
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
(TOP VIEW)
Marking side
(BGA-57P-M01)
FBGA
MBM29DL32XTD/BD
-80/90/12
7
s
BLOCK DIAGRAM
V
SS
V
CC
Bank 2 Address
Bank 1 Address
WE
CE
A
0
to A
20
(A
-1
)
OE
BYTE
WP/ACC
RESET
DQ
0
to DQ
15
RY/BY
State
Control
&
Command
Register
X-Decoder
X-Decoder
Cell Matrix
(Bank 2)
Cell Matrix
(Bank 1)
Y-Gating & Data Latch
Y-Gating &
Data Latch
DQ
0
to DQ
15
Status
Control
MBM29DL32XTD/BD
-80/90/12
8
s
LOGIC SYMBOL
Table 2 MBM29DL32XTD/BD Pin Configuration
Pin
Function
A
-1
, A
0
to A
20
Address Inputs
DQ
0
to DQ
15
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector
Group Unprotection
BYTE
Selects 8-bit or 16-bit mode
WP/ACC
Hardware Write Protection/Program
Acceleration
N.C.
No Internal Connection
V
SS
Device Ground
V
CC
Device Power Supply
21
A
0
to A
20
WE
OE
CE
DQ
0
to DQ
15
16 or 8
BYTE
WP/ACC
RESET
A
-1
RY/BY
MBM29DL32XTD/BD
-80/90/12
9
s
DEVICE BUS OPERATION
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 12.
2. Refer to the section on Sector Group Protection.
3. WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
4. V
CC
= 3.3 V 10%
5. It is also used for the extended sector group protection.
Table 3 MBM29DL32XTD/BD User Bus Operations (BYTE = V
IH
)
Operation
CE
OE WE
A
0
A
1
A
6
A
9
DQ
0
to DQ
15
RESET WP/ACC
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
V
ID
Code
H
X
Auto-Select Device Code (1)
L
L
H
H
L
L
V
ID
Code
H
X
Read (3)
L
L
H
A
0
A
1
A
6
A
9
D
OUT
H
X
Standby
H
X
X
X
X
X
X
HIGH-Z
H
X
Output Disable
L
H
H
X
X
X
X
HIGH-Z
H
X
Write (Program/Erase)
L
H
L
A
0
A
1
A
6
A
9
D
IN
H
X
Enable Sector Group Protection (2), (4)
L
V
ID
L
H
L
V
ID
X
H
X
Verify Sector Group Protection (2), (4)
L
L
H
L
H
L
V
ID
Code
H
X
Temporary Sector Group Unprotection (5)
X
X
X
X
X
X
X
X
V
ID
X
Reset (Hardware)/Standby
X
X
X
X
X
X
X
HIGH-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
L
Table 4 MBM29DL32XTD/BD User Bus Operations (BYTE = V
IL
)
Operation
CE
OE WE DQ
15
/
A
-1
A
0
A
1
A
6
A
9
DQ
0
to DQ
7
RESET WP/ACC
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
L
V
ID
Code
H
X
Auto-Select Device code (1)
L
L
H
L
H
L
L
V
ID
Code
H
X
Read (3)
L
L
H
A
-1
A
0
A
1
A
6
A
9
D
OUT
H
X
Standby
H
X
X
X
X
X
X
X
HIGH-Z
H
X
Output Disable
L
H
H
X
X
X
X
X
HIGH-Z
H
X
Write (Program/Erase)
L
H
L
A
-1
A
0
A
1
A
6
A
9
D
IN
H
X
Enable Sector Group Protection
(2), (4)
L
V
ID
L
L
H
L
V
ID
X
H
X
Verify Sector Group Protection
(2), (4)
L
L
H
L
L
H
L
V
ID
Code
H
X
Temporary Sector Group
Unprotection (5)
X
X
X
X
X
X
X
X
X
V
ID
X
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
HIGH-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
X
L
MBM29DL32XTD/BD
-80/90/12
10
s
ABSOLUTE MAXIMUM RATINGS(See WARNING)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Notes: 1. Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, inputs may negative
overshoot V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V
CC
+0.5 V. During voltage transitions, outputs may positive overshoot to V
CC
+2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A
9
, OE and RESET pins are 0.5 V. During voltage transitions, A
9
, OE
and RESET pins may negative overshoot V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A
9
, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of
up to 20 ns. when V
CC
is applied.
3. Minimum DC input voltage on WP/ACC pin is 0.5 V. During voltage transitions, WP/ACC pin may
negative overshoot V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin
iis +10.5V which may positive overshoot to +10.5V for periods of up to 20ns when Vcc is applied.
s
RECOMMENDED OPERATING CONDITIONS
Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Conditions
Rating
Unit
Min.
Max.
Storage Temperature
Tstg
55
+125
C
Ambient Temperature with
Power Applied
T
A
40
+85
C
Voltage with Respect to
Ground All pins except A
9
,
OE, RESET (Note 1)
V
IN
, V
OUT
0.5
V
CC
+0.5
V
Power Supply Voltage
(Note 1)
V
CC
0.5
+4.0
V
A
9
, OE, and RESET
(Note 2)
V
IN
0.5
+13.0
V
WP/ACC (Note 3)
V
IN
0.5
+10.5
V
Parameter
Symbol
Conditions
Value
Unit
Min.
Max.
Ambient Temperature
T
A
MBM29DL32XTD/BD-80
20
+70
C
MBM29DL32XTD/BD-90/12
40
+85
C
Power Supply Voltage
V
CC
MBM29DL32XTD/BD-80
+3.0
+3.6
V
MBM29DL32XTD/BD-90/12
+2.7
+3.6
V
MBM29DL32XTD/BD
-80/90/12
11
s
MAXIMUM OVERSHOOT
+0.6 V
0.5 V
20 ns
2.0 V
20 ns
20 ns
Figure 1 Maximum Negative Overshoot Waveform
V
CC
+0.5 V
+2.0 V
V
CC
+2.0 V
20 ns
20 ns
20 ns
Figure 2 Maximum Positive Overshoot Waveform 1
+13.0 V
V
CC
+0.5 V
+14.0 V
20 ns
20 ns
20 ns
*: This waveform is applied for A
9
, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform 2
MBM29DL32XTD/BD
-80/90/12
12
s
ELECTRICAL CHARACTERISTICS
1.
DC Characteristics
(Continued)
Notes: 1. The I
CC
current listed includes both the DC operating current and the frequency dependent component.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. Applicable for only V
CC
applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
Parameter
Symbol
Conditions
Value
Unit
Min.
Max.
Input Leakage Current
I
LI
V
IN
= V
SS
to V
CC
, V
CC
= V
CC
Max.
1.0
+1.0
A
Output Leakage Current
I
LO
V
OUT
= V
SS
to V
CC
, V
CC
= V
CC
Max.
1.0
+1.0
A
A
9
, OE, RESET Inputs Leakage
Current
I
LIT
V
CC
= V
CC
Max.
A
9
, OE, RESET = 12.5 V
--
35
A
V
CC
Active Current (Note 1)
I
CC1
CE = V
IL
, OE = V
IH
,
f = 5 MHz
Byte
--
16
mA
Word
18
CE = V
IL
, OE = V
IH
,
f = 1 MHz
Byte
--
7
mA
Word
7
V
CC
Active Current (Note 2)
I
CC2
CE = V
IL
, OE = V
IH
--
35
mA
V
CC
Current (Standby)
I
CC3
V
CC
= V
CC
Max., CE = V
CC
0.3 V,
RESET = V
CC
0.3 V
--
5
A
V
CC
Current (Standby, Reset)
I
CC4
V
CC
= V
CC
Max.,WE/ACC = V
CC
0.3 V, RESET = V
SS
0.3 V
--
5
A
V
CC
Current
(Automatic Sleep Mode) (Note 3)
I
CC5
V
CC
= V
CC
Max., CE = V
SS
0.3 V,
RESET = V
CC
0.3 V
V
IN
= V
CC
0.3 V or V
SS
0.3 V
--
5
A
V
CC
Active Current (Note 5)
(Read-While-Program)
I
CC6
CE = V
IL
, OE = V
IH
Byte
--
51
mA
Word
--
53
V
CC
Active Current (Note 5)
(Read-While-Erase)
I
CC7
CE = V
IL
, OE = V
IH
Byte
--
51
mA
Word
--
53
V
CC
Active Current
(Erase-Suspend-Program)
I
CC8
CE = V
IL
, OE = V
IH
--
35
mA
ACC Accelerated Program
Current
I
ACC
V
CC
= V
CC
Max.
WP/ACC = V
ACC
Max.
--
20
mA
Input Low Level
V
IL
--
0.5
0.6
V
Input High Level
V
IH
--
2.0
V
CC
+0.3
V
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration
V
ACC
--
8.5
9.5
V
Voltage for Autoselect and Sector
Protection (A
9
, OE, RESET)
(Note 4)
V
ID
--
11.5
12.5
V
MBM29DL32XTD/BD
-80/90/12
13
(Continued)
Notes: 1. The I
CC
current listed includes both the DC operating current and the frequency dependent component.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. Applicable for only V
CC
applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
Parameter
Symbol
Conditions
Value
Unit
Min.
Max.
Output Low Voltage Level
V
OL
I
OL
= 4.0 mA, V
CC
= V
CC
Min.
--
0.45
V
Output High Voltage Level
V
OH1
I
OH
= 2.0 mA, V
CC
= V
CC
Min.
2.4
--
V
V
OH2
I
OH
= 100
A
V
CC
0.4
--
V
Low V
CC
Lock-Out Voltage
V
LKO
--
2.3
2.5
V
MBM29DL32XTD/BD
-80/90/12
14
2.
AC Characteristics
Read Only Operations Characteristics
Note: Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29DL32XTD/BD 80)
1 TTL gate and 100 pF (MBM29DL32XTD/BD 90/12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
Parameter
symbols
Description
Test setup
80
(Note)
90
(Note)
12
(Note)
Unit
JEDEC
Standard
t
AVAV
t
RC
Read Cycle Time
--
Min.
80
90
120
ns
t
AVQV
t
ACC
Address to Output Delay
CE = V
IL
OE = V
IL
Max.
80
90
120
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE = V
IL
Max.
80
90
120
ns
t
GLQV
t
OE
Output Enable to Output Delay
--
Max.
30
35
50
ns
t
EHQZ
t
DF
Chip Enable to Output High-Z
--
Max.
25
30
30
ns
t
GHQZ
t
DF
Output Enable to Output High-Z
--
Max.
25
30
30
ns
t
AXQX
t
OH
Output Hold Time from Addresses,
CE or OE, Whichever Occurs First
--
Min.
0
0
0
ns
--
t
READY
RESET Pin Low to Read Mode
--
Max.
20
20
20
s
--
t
ELFL
t
ELFH
CE or BYTE Switching Low or High
--
Max.
5
5
5
ns
C
L
3.3 V
Diodes = IN3064
or Equivalent
2.7 k
Device
Under
Test
IN3064
or Equivalent
6.2 k
Figure 4 Test Conditions
MBM29DL32XTD/BD
-80/90/12
15
Write/Erase/Program Operations
(Continued)
Parameter symbols
Description
80
90
12
Unit
JEDEC
Standard
t
AVAV
t
WC
Write Cycle Time
Min.
80
90
120
ns
t
AVWL
t
AS
Address Setup Time
Min.
0
0
0
ns
--
t
ASO
Address Setup Time to OE Low During
Toggle Bit Polling
Min.
12
15
15
ns
t
WLAX
t
AH
Address Hold Time
Min.
45
45
50
ns
--
t
AHT
Address Hold Time from CE or OE High
During Toggle Bit Polling
Min.
0
0
0
ns
t
DVWH
t
DS
Data Setup Time
Min.
30
35
50
ns
t
WHDX
t
DH
Data Hold Time
Min.
0
0
0
ns
--
t
OEH
Output Enable
Hold Time
Read
Min.
0
0
0
ns
Toggle and Data Polling
Min.
10
10
10
ns
--
t
CEPH
CE High During Toggle Bit Polling
Min.
20
20
20
ns
--
t
OEPH
OE High During Toggle Bit Polling
Min.
20
20
20
ns
t
GHWL
t
GHWL
Read Recover Time Before Write
Min.
0
0
0
ns
t
GHEL
t
GHEL
Read Recover Time Before Write
Min.
0
0
0
ns
t
ELWL
t
CS
CE Setup Time
Min.
0
0
0
ns
t
WLEL
t
WS
WE Setup Time
Min.
0
0
0
ns
t
WHEH
t
CH
CE Hold Time
Min.
0
0
0
ns
t
EHWH
t
WH
WE Hold Time
Min.
0
0
0
ns
t
WLWH
t
WP
Write Pulse Width
Min.
35
35
50
ns
t
ELEH
t
CP
CE Pulse Width
Min.
35
35
50
ns
t
WHWL
t
WPH
Write Pulse Width High
Min.
25
30
30
ns
t
EHEL
t
CPH
CE Pulse Width High
Min.
25
30
30
ns
t
WHWH1
t
WHWH1
Byte Programming Operation
Typ.
8
8
8
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 1)
Typ.
1
1
1
sec
--
t
VCS
V
CC
Setup Time
Min.
50
50
50
s
--
t
VIDR
Rise Time to V
ID
(Note 2)
Min.
500
500
500
ns
--
t
VACCR
Rise Time to V
ID
(Note 2)
Min.
500
500
500
ns
--
t
VLHT
Voltage Transition Time (Note 2)
Min.
4
4
4
s
--
t
WPP
Write Pulse Width (Note 2)
Min.
100
100
100
s
--
t
OESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
4
s
MBM29DL32XTD/BD
-80/90/12
16
(Continued)
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Group Protection operation.
Parameter symbols
Description
80
90
12
Unit
JEDEC
Standard
--
t
CSP
CE Setup Time to WE Active (Note 2)
Min.
4
4
4
s
--
t
RB
Recover Time from RY/BY
Min.
0
0
0
ns
--
t
RP
RESET Pulse Width
Min.
500
500
500
ns
--
t
RH
RESET High Level Period before Read
Min.
200
200
200
ns
--
t
FLQZ
BYTE Switching Low to Output High-Z
Max.
30
30
40
ns
--
t
FHQV
BYTE Switching High to Output Active
Max.
80
90
120
ns
--
t
BUSY
Program/Erase Valid to RY/BY Delay
Max.
90
90
90
ns
--
t
EOE
Delay Time from Embedded Output Enable
Max.
80
90
120
ns
--
t
TOW
Erase Time-Out Time
Min.
50
50
50
s
--
t
SPD
Erase Suspend Transition Time
Max.
20
20
20
s
MBM29DL32XTD/BD
-80/90/12
17
s
ERASE AND PROGRAMMING PERFORMANCE
s
PIN CAPACITANCE
Note: Test conditions T
A
= 25C, f = 1.0 MHzs
Parameter
Limits
Unit
Comments
Min.
Typ.
Max.
Sector Erase Time
--
1
10
sec
Excludes programming time
prior to erasure
Word Programming Time
--
16
360
s
Excludes system-level
overhead
Byte Programming Time
--
8
300
s
Chip Programming Time
--
--
100
sec
Excludes system-level
overhead
Program/Erase Cycle
100,000
--
--
cycles
--
Parameter
symbol
Parameter description
Test setup
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
8
11
pF
C
IN3
WP/ACC Pin Capacitance
V
IN
= 0
21.5
22.5
pF
MBM29DL32XTD/BD
-80/90/12
18
s
TIMING DIAGRAM
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
"H" or "L"
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center Line is
High-
Impedance
"Off" State
WE
OE
CE
t
ACC
t
DF
t
CE
t
OE
Outputs
t
RC
Addresses
Addresses Stable
High-Z
Output Valid
High-Z
t
OEH
t
OH
Figure 5.1 AC Waveforms for Read Operations
MBM29DL32XTD/BD
-80/90/12
19
RESET
t
ACC
t
OH
Outputs
t
RC
Addresses
Addresses Stable
High-Z
Output Valid
t
RH
CE
t
RP
t
RH
t
CE
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
MBM29DL32XTD/BD
-80/90/12
20
t
CH
t
WP
t
WHWH1
t
WC
t
AH
CE
OE
t
RC
Addresses
Data
t
AS
t
OE
t
WPH
t
GHWL
t
DH
DQ
7
PD
A0H
D
OUT
WE
555H
PA
PA
t
OH
Data Polling
3rd Bus Cycle
t
CS
t
CE
t
DS
D
OUT
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ
7
is the output of the complement of the data written to the device.
4. D
OUT
is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the
16 mode. (The addresses differ from
8 mode.)
MBM29DL32XTD/BD
-80/90/12
21
t
CP
t
DS
t
WHWH1
t
WC
t
AH
WE
OE
Addresses
Data
t
AS
t
CPH
t
DH
DQ
7
A0H
D
OUT
CE
555H
PA
PA
Data Polling
3rd Bus Cycle
t
WS
t
WH
t
GHEL
PD
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ
7
is the output of the complement of the data written to the device.
4. D
OUT
is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the
16 mode. (The addresses differ from
8 mode.)
MBM29DL32XTD/BD
-80/90/12
22
V
CC
CE
OE
Addresses
Data
t
WP
WE
555H
2AAH
555H
555H
2AAH
SA *
t
DS
t
CH
t
AS
t
AH
t
CS
t
WPH
t
DH
t
GHWL
t
VCS
t
WC
55H
55H
80H
AAH
AAH
10H/
30H
Figure 8 AC Waveforms for Chip/Sector Erase Operations
*: SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase.
Note: These waveforms are for the
16 mode. (The addresses differ from
8 mode.)
MBM29DL32XTD/BD
-80/90/12
23
t
OEH
t
OE
t
WHWH1 or 2
CE
OE
t
EOE
t
BUSY
WE
Data
t
DF
t
CH
t
CE
High-Z
High-Z
DQ
7
=
Valid Data
DQ
0
to DQ
6
Valid Data
DQ
7
*
DQ
7
DQ
0
to DQ
6
RY/BY
Data
DQ
0
to DQ
6
= Output Flag
Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations
* : DQ
7
= Valid Data (The device has completed the Embedded operation).
MBM29DL32XTD/BD
-80/90/12
24
t
DH
t
OE
t
CE
CE
WE
OE
DQ
6
/DQ
2
Address
RY/BY
Data
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggling
Output
Valid
*
t
BUSY
t
OEH
t
OEH
t
OEPH
t
AHT
t
AHT
t
ASO
t
AS
t
CEPH
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
* : DQ
6
stops toggling (The device has completed the Embedded operation).
MBM29DL32XTD/BD
-80/90/12
25
Figure 11 Bank-to-bank Read/Write Timing Diagram
CE
DQ
WE
Address
BA1
BA1
BA1
BA2
(555H)
BA2
(PA)
BA2
(PA)
OE
Valid
Output
Valid
Output
Valid
Output
Status
Valid
Intput
Valid
Intput
t
RC
t
RC
t
RC
t
RC
t
WC
t
WC
t
AHT
t
AS
t
AS
t
AH
t
ACC
t
CE
t
OE
t
OEH
t
WP
t
GHWL
t
DS
t
DF
t
DH
t
DF
t
CEPH
Read
Command
Command
Read
Read
Read
(A0H)
(PD)
Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
DQ
2
DQ
6
WE
Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase
Erase
Complete
Toggle
DQ
2
and DQ
6
with OE or CE
Figure 12 DQ
2
vs. DQ
6
Note: DQ
2
is read from the erase-suspended sector.
MBM29DL32XTD/BD
-80/90/12
26
The rising edge of the last write pulse
CE
RY/BY
WE
t
BUSY
Entire programming
or erase operations
Figure 13 RY/BY Timing Diagram during Program/Erase Operations
t
RP
RESET
t
READY
RY/BY
WE
t
RB
Figure 14 RESET, RY/BY Timing Diagram
MBM29DL32XTD/BD
-80/90/12
27
CE
BYTE
t
ELFH
t
FHQV
A
-1
Data Output
(DQ
0
to DQ
7
)
DQ
15
DQ
15
/A
-1
DQ
0
to DQ
14
(DQ
0
to DQ
14
)
Data Output
t
CE
Figure 15 Timing Diagram for Word Mode Configuration
Figure 16 Timing Diagram for Byte Mode Configuration
CE
BYTE
DQ
15
/A
-1
DQ
0
to DQ
14
t
ELFL
DQ
15
A
-1
t
FLQZ
Data Output
(DQ
0
to DQ
7
)
(DQ
0
to DQ
14
)
Data Output
t
ACC
The falling edge of the last write signal
t
HOLD
CE or WE
(t
AH
)
t
SET
(t
AS
)
Input
Valid
BYTE
Figure 17 BYTE Timing Diagram for Write Operations
MBM29DL32XTD/BD
-80/90/12
28
Figure 18 AC Waveforms for Sector Group Protection
SGAX : Sector Group Address for initial sector
SGAY : Sector Group Address for next sector
Note: A
-1
is V
IL
on byte mode.
t
VLHT
SGAX
A
20
, A
19
, A
18
A
17
, A
16
, A
15
A
14
, A
13
, A
12
SGAY
A
0
A
6
A
9
V
ID
3 V
t
VLHT
OE
V
ID
3 V
t
VLHT
t
VLHT
t
OESP
t
WPP
t
CSP
WE
CE
t
OE
01H
Data
V
CC
A
1
t
VCS
MBM29DL32XTD/BD
-80/90/12
29
3 V
RESET
V
CC
CE
WE
RY/BY
t
VLHT
Program or Erase Command Sequence
3 V
t
VLHT
t
VCS
t
VIDR
V
ID
t
VLHT
Unprotection period
Figure 19 Temporary Sector Group Unprotection Timing Diagram
MBM29DL32XTD/BD
-80/90/12
30
SGAY
RESET
A
6
OE
WE
CE
Data
A
1
V
CC
A
0
Add
SGAX
SGAX
60H
01H
40H
60H
60H
TIME-OUT
t
VCS
t
VLHT
t
VIDR
t
OE
t
WP
t
WC
t
WC
Figure 20 Extended Sector Group Protection Timing Diagram
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250
s (min)
MBM29DL32XTD/BD
-80/90/12
31
3 V
WP/ACC
V
CC
CE
WE
RY/BY
t
VLHT
Program or Erase Command Sequence
3 V
t
VLHT
t
VCS
t
VACCR
V
ACC
t
VLHT
Acceleration period
Figure 21 Accelerated Program Timing Diagram
MBM29DL32XTD/BD
-80/90/12
32
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
(Continued)
Table 5.1 Sector Address Tables (MBM29DL321TD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA0
0
0
0
0
0
0
X
X
X
X
64/32
00000H to 0FFFFH
000000H to 007FFFH
SA1
0
0
0
0
0
1
X
X
X
X
64/32
10000H to 1FFFFH
008000H to 00FFFFH
SA2
0
0
0
0
1
0
X
X
X
X
64/32
20000H to 2FFFFH
010000H to 017FFFH
SA3
0
0
0
0
1
1
X
X
X
X
64/32
30000H to 3FFFFH
018000H to 01FFFFH
SA4
0
0
0
1
0
0
X
X
X
X
64/32
40000H to 4FFFFH
020000H to 027FFFH
SA5
0
0
0
1
0
1
X
X
X
X
64/32
50000H to 5FFFFH
028000H to 02FFFFH
SA6
0
0
0
1
1
0
X
X
X
X
64/32
60000H to 6FFFFH
030000H to 037FFFH
SA7
0
0
0
1
1
1
X
X
X
X
64/32
70000H to 7FFFFH
038000H to 03FFFFH
SA8
0
0
1
0
0
0
X
X
X
X
64/32
80000H to 8FFFFH
040000H to 047FFFH
SA9
0
0
1
0
0
1
X
X
X
X
64/32
90000H to 9FFFFH
048000H to 04FFFFH
SA10
0
0
1
0
1
0
X
X
X
X
64/32
A0000H to AFFFFH
050000H to 057FFFH
SA11
0
0
1
0
1
1
X
X
X
X
64/32
B0000H to BFFFFH
058000H to 05FFFFH
SA12
0
0
1
1
0
0
X
X
X
X
64/32
C0000H to CFFFFH
060000H to 067FFFH
SA13
0
0
1
1
0
1
X
X
X
X
64/32
D0000H to DFFFFH
068000H to 06FFFFH
SA14
0
0
1
1
1
0
X
X
X
X
64/32
E0000H to EFFFFH
070000H to 077FFFH
SA15
0
0
1
1
1
1
X
X
X
X
64/32
F0000H to FFFFFH
078000H to 07FFFFH
SA16
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
SA17
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA18
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA19
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA20
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA21
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA22
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA23
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA24
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
SA32
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
SA33
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA34
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
MBM29DL32XTD/BD
-80/90/12
33
(Continued)
MBM29DL321TD Top Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA35
1
X
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA36
1
X
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA37
1
X
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA38
1
X
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA39
1
X
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA40
1
X
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA41
1
X
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA42
1
X
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA43
1
X
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA44
1
X
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA45
1
X
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA46
1
X
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA47
1
X
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
SA48
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA49
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA50
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA51
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA52
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA53
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA54
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA55
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
SA56
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA59
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
Bank 1
SA63
1
1
1
1
1
1
0
0
0
X
8/4
3F0000H to 3F1FFFH
1F8000H to 1F8FFFH
SA64
1
1
1
1
1
1
0
0
1
X
8/4
3F2000H to 3F3FFFH
1F9000H to 1F9FFFH
SA65
1
1
1
1
1
1
0
1
0
X
8/4
3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
SA66
1
1
1
1
1
1
0
1
1
X
8/4
3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67
1
1
1
1
1
1
1
0
0
X
8/4
3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68
1
1
1
1
1
1
1
0
1
X
8/4
3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69
1
1
1
1
1
1
1
1
0
X
8/4
3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70
1
1
1
1
1
1
1
1
1
X
8/4
3FE000H to 3FFFFFH 1FF000H to 1FFFFFH
MBM29DL32XTD/BD
-80/90/12
34
(Continued)
Table 5.2 Sector Address Tables (MBM29DL321BD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA70
1
1
1
1
1
1
X
X
X
X
64/32
3F0000H to 3FFFFFH
1F8000H to 1FFFFFH
SA69
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
SA61
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA60
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA59
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA58
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA57
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA56
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA55
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA54
1
0
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
SA53
1
0
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA52
1
0
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA51
1
0
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA50
1
0
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA49
1
0
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA48
1
0
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA47
1
0
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA46
1
0
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA45
1
0
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA44
1
0
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA43
1
0
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA42
1
0
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA41
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
SA40
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA39
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
SA38
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
SA37
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
MBM29DL32XTD/BD
-80/90/12
35
(Continued)
MBM29DL321BD Bottom Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA34
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA29
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA28
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA27
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA26
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA25
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA24
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA23
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
SA22
0
0
1
1
1
1
X
X
X
X
64/32
0F0000H to 0FFFFFH
078000H to 07FFFFH
SA21
0
0
1
1
1
0
X
X
X
X
64/32
0E0000H to 0EFFFFH
070000H to 077FFFH
SA20
0
0
1
1
0
1
X
X
X
X
64/32
0D0000H to 0DFFFFH 068000H to 06FFFFH
SA19
0
0
1
1
0
0
X
X
X
X
64/32
0C0000H to 0CFFFFH 060000H to 067FFFH
SA18
0
0
1
0
1
1
X
X
X
X
64/32
0B0000H to 0BFFFFH
058000H to 05FFFFH
SA17
0
0
1
0
1
0
X
X
X
X
64/32
0A0000H to 0AFFFFH
050000H to 057FFFH
SA16
0
0
1
0
0
1
X
X
X
X
64/32
090000H to 09FFFFH
048000H to 04FFFFH
SA15
0
0
1
0
0
0
X
X
X
X
64/32
080000H to 08FFFFH
040000H to 047FFFH
SA14
0
0
0
1
1
1
X
X
X
X
64/32
070000H to 07FFFFH
038000H to 03FFFFH
SA13
0
0
0
1
1
0
X
X
X
X
64/32
060000H to 06FFFFH
030000H to 037FFFH
SA12
0
0
0
1
0
1
X
X
X
X
64/32
050000H to 05FFFFH
028000H to 02FFFFH
SA11
0
0
0
1
0
0
X
X
X
X
64/32
040000H to 04FFFFH
020000H to 027FFFH
SA10
0
0
0
0
1
1
X
X
X
X
64/32
030000H to 03FFFFH
018000H to 01FFFFH
SA9
0
0
0
0
1
0
X
X
X
X
64/32
020000H to 02FFFFH
010000H to 017FFFH
SA8
0
0
0
0
0
1
X
X
X
X
64/32
010000H to 01FFFFH
008000H to 00FFFFH
Bank 1
SA7
0
0
0
0
0
0
1
1
1
X
8/4
00E000H to 00FFFFH
007000H to 007FFFH
SA6
0
0
0
0
0
0
1
1
0
X
8/4
00C000H to 00DFFFH
006000H to 006FFFH
SA5
0
0
0
0
0
0
1
0
1
X
8/4
00A000H to 00BFFFH
005000H to 005FFFH
SA4
0
0
0
0
0
0
1
0
0
X
8/4
008000H to 009FFFH
004000H to 004FFFH
SA3
0
0
0
0
0
0
0
1
1
X
8/4
006000H to 007FFFH
003000H to 003FFFH
SA2
0
0
0
0
0
0
0
1
0
X
8/4
004000H to 005FFFH
002000H to 002FFFH
SA1
0
0
0
0
0
0
0
0
1
X
8/4
002000H to 003FFFH
001000H to 001FFFH
SA0
0
0
0
0
0
0
0
0
0
X
8/4
000000H to 001FFFH
000000H to 000FFFH
MBM29DL32XTD/BD
-80/90/12
36
(Continued)
Table 6.1 Sector Address Tables (MBM29DL322TD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA0
0
0
0
0
0
0
X
X
X
X
64/32
000000H to 00FFFFH
000000H to 007FFFH
SA1
0
0
0
0
0
1
X
X
X
X
64/32
010000H to 01FFFFH
008000H to 00FFFFH
SA2
0
0
0
0
1
0
X
X
X
X
64/32
020000H to 02FFFFH
010000H to 017FFFH
SA3
0
0
0
0
1
1
X
X
X
X
64/32
030000H to 03FFFFH
018000H to 01FFFFH
SA4
0
0
0
1
0
0
X
X
X
X
64/32
040000H to 04FFFFH
020000H to 027FFFH
SA5
0
0
0
1
0
1
X
X
X
X
64/32
050000H to 05FFFFH
028000H to 02FFFFH
SA6
0
0
0
1
1
0
X
X
X
X
64/32
060000H to 06FFFFH
030000H to 037FFFH
SA7
0
0
0
1
1
1
X
X
X
X
64/32
070000H to 07FFFFH
038000H to 03FFFFH
SA8
0
0
1
0
0
0
X
X
X
X
64/32
080000H to 08FFFFH
040000H to 047FFFH
SA9
0
0
1
0
0
1
X
X
X
X
64/32
090000H to 09FFFFH
048000H to 04FFFFH
SA10
0
0
1
0
1
0
X
X
X
X
64/32
0A0000H to 0AFFFFH
050000H to 057FFFH
SA11
0
0
1
0
1
1
X
X
X
X
64/32
0B0000H to 0BFFFFH
058000H to 05FFFFH
SA12
0
0
1
1
0
0
X
X
X
X
64/32
0C0000H to 0CFFFFH 060000H to 067FFFH
SA13
0
0
1
1
0
1
X
X
X
X
64/32
0D0000H to 0DFFFFH 068000H to 06FFFFH
SA14
0
0
1
1
1
0
X
X
X
X
64/32
0E0000H to 0EFFFFH
070000H to 077FFFH
SA15
0
0
1
1
1
1
X
X
X
X
64/32
0F0000H to 0FFFFFH
078000H to 07FFFFH
SA16
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
SA17
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA18
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA19
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA20
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA21
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA22
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA23
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA24
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
SA32
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
SA33
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA34
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
MBM29DL32XTD/BD
-80/90/12
37
(Continued)
MBM29DL322TD Top Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA35
1
0
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA36
1
0
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA37
1
0
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA38
1
0
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA39
1
0
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA40
1
0
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA41
1
0
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA42
1
0
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA43
1
0
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA44
1
0
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA45
1
0
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA46
1
0
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA47
1
0
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
SA48
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA49
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA50
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA51
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA52
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA53
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA54
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA55
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
Bank 1
SA56
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA59
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA63
1
1
1
1
1
1
0
0
0
X
8/4
3F0000H to 3F1FFFH
1F8000H to 1F8FFFH
SA64
1
1
1
1
1
1
0
0
1
X
8/4
3F2000H to 3F3FFFH
1F9000H to 1F9FFFH
SA65
1
1
1
1
1
1
0
1
0
X
8/4
3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
SA66
1
1
1
1
1
1
0
1
1
X
8/4
3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67
1
1
1
1
1
1
1
0
0
X
8/4
3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68
1
1
1
1
1
1
1
0
1
X
8/4
3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69
1
1
1
1
1
1
1
1
0
X
8/4
3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70
1
1
1
1
1
1
1
1
1
X
8/4
3FE000H to 3FFFFFH 1FF000H to 1FFFFFH
MBM29DL32XTD/BD
-80/90/12
38
(Continued)
Table 6.2 Sector Address Tables (MBM29DL322BD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA70
1
1
1
1
1
1
X
X
X
X
64/32
3F0000H to 3FFFFFH
1F8000H to 1FFFFFH
SA69
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
SA61
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA60
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA59
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA58
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA57
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA56
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA55
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA54
1
0
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
SA53
1
0
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA52
1
0
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA51
1
0
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA50
1
0
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA49
1
0
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA48
1
0
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA47
1
0
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA46
1
0
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA45
1
0
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA44
1
0
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA43
1
0
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA42
1
0
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA41
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
SA40
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA39
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
SA38
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
SA37
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
MBM29DL32XTD/BD
-80/90/12
39
(Continued)
MBM29DL322BD Bottom Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA34
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA29
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA28
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA27
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA26
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA25
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA24
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA23
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
SA22
0
0
1
1
1
1
X
X
X
X
64/32
0F0000H to 0FFFFFH
078000H to 07FFFFH
SA21
0
0
1
1
1
0
X
X
X
X
64/32
0E0000H to 0EFFFFH
070000H to 077FFFH
SA20
0
0
1
1
0
1
X
X
X
X
64/32
0D0000H to 0DFFFFH 068000H to 06FFFFH
SA19
0
0
1
1
0
0
X
X
X
X
64/32
0C0000H to 0CFFFFH 060000H to 067FFFH
SA18
0
0
1
0
1
1
X
X
X
X
64/32
0B0000H to 0BFFFFH
058000H to 05FFFFH
SA17
0
0
1
0
1
0
X
X
X
X
64/32
0A0000H to 0AFFFFH
050000H to 057FFFH
SA16
0
0
1
0
0
1
X
X
X
X
64/32
090000H to 09FFFFH
048000H to 04FFFFH
SA15
0
0
1
0
0
0
X
X
X
X
64/32
080000H to 08FFFFH
040000H to 047FFFH
Bank 1
SA14
0
0
0
1
1
1
X
X
X
X
64/32
070000H to 07FFFFH
038000H to 03FFFFH
SA13
0
0
0
1
1
0
X
X
X
X
64/32
060000H to 06FFFFH
030000H to 037FFFH
SA12
0
0
0
1
0
1
X
X
X
X
64/32
050000H to 05FFFFH
028000H to 02FFFFH
SA11
0
0
0
1
0
0
X
X
X
X
64/32
040000H to 04FFFFH
020000H to 027FFFH
SA10
0
0
0
0
1
1
X
X
X
X
64/32
030000H to 03FFFFH
018000H to 01FFFFH
SA9
0
0
0
0
1
0
X
X
X
X
64/32
020000H to 02FFFFH
010000H to 017FFFH
SA8
0
0
0
0
0
1
X
X
X
X
64/32
010000H to 01FFFFH
008000H to 00FFFFH
SA7
0
0
0
0
0
0
1
1
1
X
8/4
00E000H to 00FFFFH
007000H to 007FFFH
SA6
0
0
0
0
0
0
1
1
0
X
8/4
00C000H to 00DFFFH
006000H to 006FFFH
SA5
0
0
0
0
0
0
1
0
1
X
8/4
00A000H to 00BFFFH
005000H to 005FFFH
SA4
0
0
0
0
0
0
1
0
0
X
8/4
008000H to 009FFFH
004000H to 004FFFH
SA3
0
0
0
0
0
0
0
1
1
X
8/4
006000H to 007FFFH
003000H to 003FFFH
SA2
0
0
0
0
0
0
0
1
0
X
8/4
004000H to 005FFFH
002000H to 002FFFH
SA1
0
0
0
0
0
0
0
0
1
X
8/4
002000H to 003FFFH
001000H to 001FFFH
SA0
0
0
0
0
0
0
0
0
0
X
8/4
000000H to 001FFFH
000000H to 000FFFH
MBM29DL32XTD/BD
-80/90/12
40
(Continued)
Table 7.1 Sector Address Tables (MBM29DL323TD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA0
0
0
0
0
0
0
X
X
X
X
64/32
000000H to 00FFFFH
000000H to 007FFFH
SA1
0
0
0
0
0
1
X
X
X
X
64/32
010000H to 01FFFFH
008000H to 00FFFFH
SA2
0
0
0
0
1
0
X
X
X
X
64/32
020000H to 02FFFFH
010000H to 017FFFH
SA3
0
0
0
0
1
1
X
X
X
X
64/32
030000H to 03FFFFH
018000H to 01FFFFH
SA4
0
0
0
1
0
0
X
X
X
X
64/32
040000H to 04FFFFH
020000H to 027FFFH
SA5
0
0
0
1
0
1
X
X
X
X
64/32
050000H to 05FFFFH
028000H to 02FFFFH
SA6
0
0
0
1
1
0
X
X
X
X
64/32
060000H to 06FFFFH
030000H to 037FFFH
SA7
0
0
0
1
1
1
X
X
X
X
64/32
070000H to 07FFFFH
038000H to 03FFFFH
SA8
0
0
1
0
0
0
X
X
X
X
64/32
080000H to 08FFFFH
040000H to 047FFFH
SA9
0
0
1
0
0
1
X
X
X
X
64/32
090000H to 09FFFFH
048000H to 04FFFFH
SA10
0
0
1
0
1
0
X
X
X
X
64/32
0A0000H to 0AFFFFH
050000H to 057FFFH
SA11
0
0
1
0
1
1
X
X
X
X
64/32
0B0000H to 0BFFFFH
058000H to 05FFFFH
SA12
0
0
1
1
0
0
X
X
X
X
64/32
0C0000H to 0CFFFFH 060000H to 067FFFH
SA13
0
0
1
1
0
1
X
X
X
X
64/32
0D0000H to 0DFFFFH 068000H to 06FFFFH
SA14
0
0
1
1
1
0
X
X
X
X
64/32
0E0000H to 0EFFFFH
070000H to 077FFFH
SA15
0
0
1
1
1
1
X
X
X
X
64/32
0F0000H to 0FFFFFH
078000H to 07FFFFH
SA16
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
SA17
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA18
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA19
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA20
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA21
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA22
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA23
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA24
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
SA32
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
SA33
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA34
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
MBM29DL32XTD/BD
-80/90/12
41
(Continued)
MBM29DL323TD Top Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA35
1
0
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA36
1
0
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA37
1
0
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA38
1
0
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA39
1
0
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA40
1
0
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA41
1
0
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA42
1
0
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA43
1
0
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA44
1
0
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA45
1
0
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA46
1
0
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA47
1
0
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
Bank 1
SA48
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA49
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA50
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA51
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA52
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA53
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA54
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA55
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
SA56
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA59
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA63
1
1
1
1
1
1
0
0
0
X
8/4
3F0000H to 3F1FFFH
1F8000H to 1F8FFFH
SA64
1
1
1
1
1
1
0
0
1
X
8/4
3F2000H to 3F3FFFH
1F9000H to 1F9FFFH
SA65
1
1
1
1
1
1
0
1
0
X
8/4
3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
SA66
1
1
1
1
1
1
0
1
1
X
8/4
3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67
1
1
1
1
1
1
1
0
0
X
8/4
3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68
1
1
1
1
1
1
1
0
1
X
8/4
3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69
1
1
1
1
1
1
1
1
0
X
8/4
3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70
1
1
1
1
1
1
1
1
1
X
8/4
3FE000H to 3FFFFFH 1FF000H to 1FFFFFH
MBM29DL32XTD/BD
-80/90/12
42
(Continued)
Table 7.2 Sector Address Tables (MBM29DL323BD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA70
1
1
1
1
1
1
X
X
X
X
64/32
3F0000H to 3FFFFFH
1F8000H to 1FFFFFH
SA69
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
SA61
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA60
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA59
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA58
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA57
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA56
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA55
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA54
1
0
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
SA53
1
0
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA52
1
0
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA51
1
0
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA50
1
0
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA49
1
0
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA48
1
0
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA47
1
0
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA46
1
0
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA45
1
0
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA44
1
0
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA43
1
0
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA42
1
0
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA41
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
SA40
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA39
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
SA38
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
SA37
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
MBM29DL32XTD/BD
-80/90/12
43
(Continued)
MBM29DL323BD Bottom Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA34
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA29
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA28
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA27
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA26
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA25
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA24
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA23
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
Bank 1
SA22
0
0
1
1
1
1
X
X
X
X
64/32
0F0000H to 0FFFFFH
078000H to 07FFFFH
SA21
0
0
1
1
1
0
X
X
X
X
64/32
0E0000H to 0EFFFFH
070000H to 077FFFH
SA20
0
0
1
1
0
1
X
X
X
X
64/32
0D0000H to 0DFFFFH 068000H to 06FFFFH
SA19
0
0
1
1
0
0
X
X
X
X
64/32
0C0000H to 0CFFFFH 060000H to 067FFFH
SA18
0
0
1
0
1
1
X
X
X
X
64/32
0B0000H to 0BFFFFH
058000H to 05FFFFH
SA17
0
0
1
0
1
0
X
X
X
X
64/32
0A0000H to 0AFFFFH
050000H to 057FFFH
SA16
0
0
1
0
0
1
X
X
X
X
64/32
090000H to 09FFFFH
048000H to 04FFFFH
SA15
0
0
1
0
0
0
X
X
X
X
64/32
080000H to 08FFFFH
040000H to 047FFFH
SA14
0
0
0
1
1
1
X
X
X
X
64/32
070000H to 07FFFFH
038000H to 03FFFFH
SA13
0
0
0
1
1
0
X
X
X
X
64/32
060000H to 06FFFFH
030000H to 037FFFH
SA12
0
0
0
1
0
1
X
X
X
X
64/32
050000H to 05FFFFH
028000H to 02FFFFH
SA11
0
0
0
1
0
0
X
X
X
X
64/32
040000H to 04FFFFH
020000H to 027FFFH
SA10
0
0
0
0
1
1
X
X
X
X
64/32
030000H to 03FFFFH
018000H to 01FFFFH
SA9
0
0
0
0
1
0
X
X
X
X
64/32
020000H to 02FFFFH
010000H to 017FFFH
SA8
0
0
0
0
0
1
X
X
X
X
64/32
010000H to 01FFFFH
008000H to 00FFFFH
SA7
0
0
0
0
0
0
1
1
1
X
8/4
00E000H to 00FFFFH
007000H to 007FFFH
SA6
0
0
0
0
0
0
1
1
0
X
8/4
00C000H to 00DFFFH
006000H to 006FFFH
SA5
0
0
0
0
0
0
1
0
1
X
8/4
00A000H to 00BFFFH
005000H to 005FFFH
SA4
0
0
0
0
0
0
1
0
0
X
8/4
008000H to 009FFFH
004000H to 004FFFH
SA3
0
0
0
0
0
0
0
1
1
X
8/4
006000H to 007FFFH
003000H to 003FFFH
SA2
0
0
0
0
0
0
0
1
0
X
8/4
004000H to 005FFFH
002000H to 002FFFH
SA1
0
0
0
0
0
0
0
0
1
X
8/4
002000H to 003FFFH
001000H to 001FFFH
SA0
0
0
0
0
0
0
0
0
0
X
8/4
000000H to 001FFFH
000000H to 000FFFH
MBM29DL32XTD/BD
-80/90/12
44
(Continued)
Table 8.1 Sector Address Tables (MBM29DL324TD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA0
0
0
0
0
0
0
X
X
X
X
64/32
000000H to 00FFFFH
000000H to 007FFFH
SA1
0
0
0
0
0
1
X
X
X
X
64/32
010000H to 01FFFFH
008000H to 00FFFFH
SA2
0
0
0
0
1
0
X
X
X
X
64/32
020000H to 02FFFFH
010000H to 017FFFH
SA3
0
0
0
0
1
1
X
X
X
X
64/32
030000H to 03FFFFH
018000H to 01FFFFH
SA4
0
0
0
1
0
0
X
X
X
X
64/32
040000H to 04FFFFH
020000H to 027FFFH
SA5
0
0
0
1
0
1
X
X
X
X
64/32
050000H to 05FFFFH
028000H to 02FFFFH
SA6
0
0
0
1
1
0
X
X
X
X
64/32
060000H to 06FFFFH
030000H to 037FFFH
SA7
0
0
0
1
1
1
X
X
X
X
64/32
070000H to 07FFFFH
038000H to 03FFFFH
SA8
0
0
1
0
0
0
X
X
X
X
64/32
080000H to 08FFFFH
040000H to 047FFFH
SA9
0
0
1
0
0
1
X
X
X
X
64/32
090000H to 09FFFFH
048000H to 04FFFFH
SA10
0
0
1
0
1
0
X
X
X
X
64/32
0A0000H to 0AFFFFH
050000H to 057FFFH
SA11
0
0
1
0
1
1
X
X
X
X
64/32
0B0000H to 0BFFFFH
058000H to 05FFFFH
SA12
0
0
1
1
0
0
X
X
X
X
64/32
0C0000H to 0CFFFFH 060000H to 067FFFH
SA13
0
0
1
1
0
1
X
X
X
X
64/32
0D0000H to 0DFFFFH 068000H to 06FFFFH
SA14
0
0
1
1
1
0
X
X
X
X
64/32
0E0000H to 0EFFFFH
070000H to 077FFFH
SA15
0
0
1
1
1
1
X
X
X
X
64/32
0F0000H to 0FFFFFH
078000H to 07FFFFH
SA16
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
SA17
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA18
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA19
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA20
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA21
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA22
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA23
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA24
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
Bank 1
SA32
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
SA33
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA34
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
MBM29DL32XTD/BD
-80/90/12
45
(Continued)
MBM29DL324TD Top Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 1
SA35
1
0
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA36
1
0
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA37
1
0
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA38
1
0
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA39
1
0
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA40
1
0
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA41
1
0
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA42
1
0
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA43
1
0
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA44
1
0
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA45
1
0
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA46
1
0
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA47
1
0
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
SA48
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA49
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA50
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA51
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA52
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA53
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA54
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA55
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
SA56
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA59
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA63
1
1
1
1
1
1
0
0
0
X
8/4
3F0000H to 3F1FFFH
1F8000H to 1F8FFFH
SA64
1
1
1
1
1
1
0
0
1
X
8/4
3F2000H to 3F3FFFH
1F9000H to 1F9FFFH
SA65
1
1
1
1
1
1
0
1
0
X
8/4
3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
SA66
1
1
1
1
1
1
0
1
1
X
8/4
3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67
1
1
1
1
1
1
1
0
0
X
8/4
3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68
1
1
1
1
1
1
1
0
1
X
8/4
3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69
1
1
1
1
1
1
1
1
0
X
8/4
3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70
1
1
1
1
1
1
1
1
1
X
8/4
3FE000H to 3FFFFFH 1FF000H to 1FFFFFH
MBM29DL32XTD/BD
-80/90/12
46
(Continued)
Table 8.2 Sector Address Tables (MBM29DL324BD)
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 2
SA70
1
1
1
1
1
1
X
X
X
X
64/32
3F0000H to 3FFFFFH
1F8000H to 1FFFFFH
SA69
1
1
1
1
1
0
X
X
X
X
64/32
3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68
1
1
1
1
0
1
X
X
X
X
64/32
3D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67
1
1
1
1
0
0
X
X
X
X
64/32
3C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66
1
1
1
0
1
1
X
X
X
X
64/32
3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65
1
1
1
0
1
0
X
X
X
X
64/32
3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64
1
1
1
0
0
1
X
X
X
X
64/32
390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63
1
1
1
0
0
0
X
X
X
X
64/32
380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62
1
1
0
1
1
1
X
X
X
X
64/32
370000H to 37FFFFH
1B8000H to 1BFFFFH
SA61
1
1
0
1
1
0
X
X
X
X
64/32
360000H to 36FFFFH
1B0000H to 1B7FFFH
SA60
1
1
0
1
0
1
X
X
X
X
64/32
350000H to 35FFFFH
1A8000H to 1AFFFFH
SA59
1
1
0
1
0
0
X
X
X
X
64/32
340000H to 34FFFFH
1A0000H to 1A7FFFH
SA58
1
1
0
0
1
1
X
X
X
X
64/32
330000H to 33FFFFH
198000H to 19FFFFH
SA57
1
1
0
0
1
0
X
X
X
X
64/32
320000H to 32FFFFH
190000H to 197FFFH
SA56
1
1
0
0
0
1
X
X
X
X
64/32
310000H to 31FFFFH
188000H to 18FFFFH
SA55
1
1
0
0
0
0
X
X
X
X
64/32
300000H to 30FFFFH
180000H to 187FFFH
SA54
1
0
1
1
1
1
X
X
X
X
64/32
2F0000H to 2FFFFFH
178000H to 17FFFFH
SA53
1
0
1
1
1
0
X
X
X
X
64/32
2E0000H to 2EFFFFH
170000H to 177FFFH
SA52
1
0
1
1
0
1
X
X
X
X
64/32
2D0000H to 2DFFFFH 168000H to 16FFFFH
SA51
1
0
1
1
0
0
X
X
X
X
64/32
2C0000H to 2CFFFFH 160000H to 167FFFH
SA50
1
0
1
0
1
1
X
X
X
X
64/32
2B0000H to 2BFFFFH
158000H to 15FFFFH
SA49
1
0
1
0
1
0
X
X
X
X
64/32
2A0000H to 2AFFFFH
150000H to 157FFFH
SA48
1
0
1
0
0
1
X
X
X
X
64/32
290000H to 29FFFFH
148000H to 14FFFFH
SA47
1
0
1
0
0
0
X
X
X
X
64/32
280000H to 28FFFFH
140000H to 147FFFH
SA46
1
0
0
1
1
1
X
X
X
X
64/32
270000H to 27FFFFH
138000H to 13FFFFH
SA45
1
0
0
1
1
0
X
X
X
X
64/32
260000H to 26FFFFH
130000H to 137FFFH
SA44
1
0
0
1
0
1
X
X
X
X
64/32
250000H to 25FFFFH
128000H to 12FFFFH
SA43
1
0
0
1
0
0
X
X
X
X
64/32
240000H to 24FFFFH
120000H to 127FFFH
SA42
1
0
0
0
1
1
X
X
X
X
64/32
230000H to 23FFFFH
118000H to 11FFFFH
SA41
1
0
0
0
1
0
X
X
X
X
64/32
220000H to 22FFFFH
110000H to 117FFFH
SA40
1
0
0
0
0
1
X
X
X
X
64/32
210000H to 21FFFFH
108000H to 10FFFFH
SA39
1
0
0
0
0
0
X
X
X
X
64/32
200000H to 20FFFFH
100000H to 107FFFH
Bank 1
SA38
0
1
1
1
1
1
X
X
X
X
64/32
1F0000H to 1FFFFFH
0F8000H to 0FFFFFH
SA37
0
1
1
1
1
0
X
X
X
X
64/32
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36
0
1
1
1
0
1
X
X
X
X
64/32
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35
0
1
1
1
0
0
X
X
X
X
64/32
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH
MBM29DL32XTD/BD
-80/90/12
47
(Continued)
MBM29DL324BD Bottom Boot Sector Architecture
Note: The address range is A
20
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
20
: A
0
if in word mode (BYTE = V
IH
).
Bank Sector
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
14
A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
Bank 1
SA34
0
1
1
0
1
1
X
X
X
X
64/32
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33
0
1
1
0
1
0
X
X
X
X
64/32
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32
0
1
1
0
0
1
X
X
X
X
64/32
190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31
0
1
1
0
0
0
X
X
X
X
64/32
180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30
0
1
0
1
1
1
X
X
X
X
64/32
170000H to 17FFFFH
0B8000H to 0BFFFFH
SA29
0
1
0
1
1
0
X
X
X
X
64/32
160000H to 16FFFFH
0B0000H to 0B7FFFH
SA28
0
1
0
1
0
1
X
X
X
X
64/32
150000H to 15FFFFH
0A8000H to 0AFFFFH
SA27
0
1
0
1
0
0
X
X
X
X
64/32
140000H to 14FFFFH
0A0000H to 0A7FFFH
SA26
0
1
0
0
1
1
X
X
X
X
64/32
130000H to 13FFFFH
098000H to 09FFFFH
SA25
0
1
0
0
1
0
X
X
X
X
64/32
120000H to 12FFFFH
090000H to 097FFFH
SA24
0
1
0
0
0
1
X
X
X
X
64/32
110000H to 11FFFFH
088000H to 08FFFFH
SA23
0
1
0
0
0
0
X
X
X
X
64/32
100000H to 10FFFFH
080000H to 087FFFH
SA22
0
0
1
1
1
1
X
X
X
X
64/32
0F0000H to 0FFFFFH
078000H to 07FFFFH
SA21
0
0
1
1
1
0
X
X
X
X
64/32
0E0000H to 0EFFFFH
070000H to 077FFFH
SA20
0
0
1
1
0
1
X
X
X
X
64/32
0D0000H to 0DFFFFH 068000H to 06FFFFH
SA19
0
0
1
1
0
0
X
X
X
X
64/32
0C0000H to 0CFFFFH 060000H to 067FFFH
SA18
0
0
1
0
1
1
X
X
X
X
64/32
0B0000H to 0BFFFFH
058000H to 05FFFFH
SA17
0
0
1
0
1
0
X
X
X
X
64/32
0A0000H to 0AFFFFH
050000H to 057FFFH
SA16
0
0
1
0
0
1
X
X
X
X
64/32
090000H to 09FFFFH
048000H to 04FFFFH
SA15
0
0
1
0
0
0
X
X
X
X
64/32
080000H to 08FFFFH
040000H to 047FFFH
SA14
0
0
0
1
1
1
X
X
X
X
64/32
070000H to 07FFFFH
038000H to 03FFFFH
SA13
0
0
0
1
1
0
X
X
X
X
64/32
060000H to 06FFFFH
030000H to 037FFFH
SA12
0
0
0
1
0
1
X
X
X
X
64/32
050000H to 05FFFFH
028000H to 02FFFFH
SA11
0
0
0
1
0
0
X
X
X
X
64/32
040000H to 04FFFFH
020000H to 027FFFH
SA10
0
0
0
0
1
1
X
X
X
X
64/32
030000H to 03FFFFH
018000H to 01FFFFH
SA9
0
0
0
0
1
0
X
X
X
X
64/32
020000H to 02FFFFH
010000H to 017FFFH
SA8
0
0
0
0
0
1
X
X
X
X
64/32
010000H to 01FFFFH
008000H to 00FFFFH
SA7
0
0
0
0
0
0
1
1
1
X
8/4
00E000H to 00FFFFH
007000H to 007FFFH
SA6
0
0
0
0
0
0
1
1
0
X
8/4
00C000H to 00DFFFH
006000H to 006FFFH
SA5
0
0
0
0
0
0
1
0
1
X
8/4
00A000H to 00BFFFH
005000H to 005FFFH
SA4
0
0
0
0
0
0
1
0
0
X
8/4
008000H to 009FFFH
004000H to 004FFFH
SA3
0
0
0
0
0
0
0
1
1
X
8/4
006000H to 007FFFH
003000H to 003FFFH
SA2
0
0
0
0
0
0
0
1
0
X
8/4
004000H to 005FFFH
002000H to 002FFFH
SA1
0
0
0
0
0
0
0
0
1
X
8/4
002000H to 003FFFH
001000H to 001FFFH
SA0
0
0
0
0
0
0
0
0
0
X
8/4
000000H to 001FFFH
000000H to 000FFFH
MBM29DL32XTD/BD
-80/90/12
48
Table 9.1 Sector Group Addresses (MBM29DL32XTD)
(Top Boot Block)
Sector group
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Sectors
SGA0
0
0
0
0
0
0
X
X
X
SA0
SGA1
0
0
0
0
0
1
X
X
X
SA1 to SA3
1
0
1
1
SGA2
0
0
0
1
X
X
X
X
X
SA4 to SA7
SGA3
0
0
1
0
X
X
X
X
X
SA8 to SA11
SGA4
0
0
1
1
X
X
X
X
X
SA12 to SA15
SGA5
0
1
0
0
X
X
X
X
X
SA16 to SA19
SGA6
0
1
0
1
X
X
X
X
X
SA20 to SA23
SGA7
0
1
1
0
X
X
X
X
X
SA24 to SA27
SGA8
0
1
1
1
X
X
X
X
X
SA28 to SA31
SGA9
1
0
0
0
X
X
X
X
X
SA32 to SA35
SGA10
1
0
0
1
X
X
X
X
X
SA36 to SA39
SGA11
1
0
1
0
X
X
X
X
X
SA40 to SA43
SGA12
1
0
1
1
X
X
X
X
X
SA44 to SA47
SGA13
1
1
0
0
X
X
X
X
X
SA48 to SA51
SGA14
1
1
0
1
X
X
X
X
X
SA52 to SA55
SGA15
1
1
1
0
X
X
X
X
X
SA56 to SA59
SGA16
1
1
1
1
0
0
X
X
X
SA60 to SA62
0
1
1
0
SGA17
1
1
1
1
1
1
0
0
0
SA63
SGA18
1
1
1
1
1
1
0
0
1
SA64
SGA19
1
1
1
1
1
1
0
1
0
SA65
SGA20
1
1
1
1
1
1
0
1
1
SA66
SGA21
1
1
1
1
1
1
1
0
0
SA67
SGA22
1
1
1
1
1
1
1
0
1
SA68
SGA23
1
1
1
1
1
1
1
1
0
SA69
SGA24
1
1
1
1
1
1
1
1
1
SA70
MBM29DL32XTD/BD
-80/90/12
49
Table 9.2 Sector Group Addresses (MBM29DL32XBD)
(Bottom Boot Block)
Sector group
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Sectors
SGA0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
1
1
1
SA7
SGA8
0
0
0
0
0
1
X
X
X
SA8 to SA10
1
0
1
1
SGA9
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA15
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA16
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA17
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA18
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA19
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA20
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA21
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA22
1
1
1
0
X
X
X
X
X
SA63 to SA66
SGA23
1
1
1
1
0
0
X
X
X
SA67 to SA69
0
1
1
0
SGA24
1
1
1
1
1
1
X
X
X
SA70
MBM29DL32XTD/BD
-80/90/12
50
s
FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL32XTD/BD have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A
15
to A
20
) with zero latency.
The MBM29DL321TD/BD have two banks which contain
Bank 1 (8KB
eight sectors) and Bank 2 (64KB
sixty-three sectors).
The MBM29DL322TD/BD have two banks which contain
Bank 1 (8KB
eight sectors, 64KB
seven sectors) and Bank 2 (64KB
fifty-six sectors).
The MBM29DL323TD/BD have two banks which contain
Bank 1 (8KB
eight sectors, 64KB
fifteen sectors) and Bank 2 (64KB
forty-eight sectors).
The MBM29DL324TD/BD have two banks which contain
Bank 1 (8KB
eight sectors, 64KB
thirty-one sectors) and Bank 2 (64KB
thirty-two sectors).
The simultaneous operation can not execute multi-function mode in the same bank. Table 10 shows combination
to be possible for simultaneous operation. (Refer to the Figure 11 Back-to-back Read/Write Timing Diagram.)
*: An erase operation may also be supended to read from or program to a sector not being erased.
Read Mode
The MBM29DL32XTD/BD have two control functions which must be satisfied in order to obtain data at the
outputs. CE is the power control and should be used for a device selection. OE is the output control and should
be used to gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t
ACC
-t
OE
time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from "H" or "L"
Table 10 Simultaneous Operation
Case
Bank 1 status
Bank 2 status
1
Read Mode
Read Mode
2
Read Mode
Autoselect Mode
3
Read Mode
Program Mode
4
Read Mode
Erase Mode *
5
Autoselect Mode
Read Mode
6
Program Mode
Read Mode
7
Erase Mode *
Read Mode
MBM29DL32XTD/BD
-80/90/12
51
Standby Mode
There are two ways to implement the standby mode on the MBM29DL32XTD/BD devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
0.3 V.
Under this condition the current consumed is less than 5
A max. During Embedded Algorithm operation, V
CC
active current (I
CC2
) is required even CE = "H". The device can be read with standard access time (t
CE
) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
0.3 V (CE
= "H" or "L"). Under this condition the current is consumed is less than 5
A max. Once the RESET pin is taken
high, the device requires t
RH
of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL32XTD/BD data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29DL32XTD/BD automatically switch themselves to low power mode when
MBM29DL32XTD/BD addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1
A (CMOS Level).
During simultaneous operation, V
CC
active current (I
CC2
) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL32XTD/BD read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (V
IH
), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force V
ID
(11.5 V to 12.5 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are DON'T CARES except A
0
, A
1
, and A
6
(A
-1
). (See Tables 3 and 4.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL32XTD/BD are erased or programmed in a system without access to high voltage on the A
9
pin. The
command sequence is illustrated in Table 12. (Refer to Autoselect Command section.)
MBM29DL32XTD/BD
-80/90/12
52
Byte 0 (A
0
= V
IL
) represents the manufacturer's code (Fujitsu = 04H) and word 1 (A
0
= V
IH
) represents the device
identifier code (MBM29DL321TD = 59H and MBM29DL321BD = 5AH for
8 mode; MBM29DL321TD = 2259H
and MBM29DL321BD = 225AH for
16 mode). (MBM29DL322TD = 55H and MBM29DL322BD = 56H for
8
mode; MBM29DL322TD = 2255H and MBM29DL322BD = 2256H for
16 mode). (MBM29DL323TD = 50H and
MBM29DL323BD = 53H for
8 mode; MBM29DL323TD = 2250H and MBM29DL323BD = 2253H for
16 mode).
(MBM29DL324TD = 5CH and MBM29DL324BD = 5FH for
8 mode; MBM29DL324TD = 225CH and
MBM29DL324BD = 225FH for
16 mode). These two bytes/words are given in the tables 11.1 to 11.8. All
identifiers for manufactures and device will exhibit odd parity with DQ
7
defined as the parity bit. In order to read
the proper device codes when executing the autoselect, A
1
must be V
IL
. (See Tables 11.1 to 11.8.)
In case of applying V
ID
on A
9
, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation
can not be executed.
*1: A
-1
is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
(B): Byte mode
(W): Word mode
Table 11.1 MBM29DL321TD/BD Sector Group Protection Verify Autoselect Codes
Type
A
12
to A
20
A
6
A
1
A
0
A
-1
*1
Code (HEX)
Manufacture's Code
X
V
IL
V
IL
V
IL
V
IL
04H
Device
Code
MBM29DL321TD
Byte
X
V
IL
V
IL
V
IH
V
IL
59H
Word
X
2259H
MBM29DL321BD
Byte
X
V
IL
V
IL
V
IH
V
IL
5AH
Word
X
225AH
Sector Group Protection
Sector Group
Addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
Table 11.2 Expanded Autoselect Code Table
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL321TD
(B)
59H A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
1
0
0
1
(W) 2259H
0
0
1
0
0
0
1
0
0
1
0
1
1
0
0
1
MBM29DL321BD
(B)
5AH A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
1
0
1
0
(W) 225AH
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
Sector Group Protection
01H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL32XTD/BD
-80/90/12
53
*1: A
-1
is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
(B): Byte mode
(W): Word mode
Table 11.3 MBM29DL322TD/BD Sector Group Protection Verify Autoselect Codes
Type
A
12
to A
20
A
6
A
1
A
0
A
-1
*1
Code (HEX)
Manufacture's Code
X
V
IL
V
IL
V
IL
V
IL
04H
Device
Code
MBM29DL322TD
Byte
X
V
IL
V
IL
V
IH
V
IL
55H
Word
X
2255H
MBM29DL322BD
Byte
X
V
IL
V
IL
V
IH
V
IL
56H
Word
X
2256H
Sector Group Protection
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
Table 11.4 Expanded Autoselect Code Table
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL322TD
(B)
55H A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
0
1
0
1
(W) 2255H
0
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
MBM29DL322BD
(B)
56H A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
0
1
1
0
(W) 2256H
0
0
1
0
0
0
1
0
0
1
0
1
0
1
1
0
Sector Group Protection
01H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL32XTD/BD
-80/90/12
54
*1: A
-1
is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
(B): Byte mode
(W): Word mode
Table 11.5 MBM29DL323TD/BD Sector Group Protection Verify Autoselect Codes
Type
A
12
to A
20
A
6
A
1
A
0
A
-1
*1
Code (HEX)
Manufacture's Code
X
V
IL
V
IL
V
IL
V
IL
04H
Device
Code
MBM29DL323TD
Byte
X
V
IL
V
IL
V
IH
V
IL
50H
Word
X
2250H
MBM29DL323BD
Byte
X
V
IL
V
IL
V
IH
V
IL
53H
Word
X
2253H
Sector Group Protection
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
Table 11.6 Expanded Autoselect Code Table
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL323TD
(B)
50H A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
0
0
0
0
(W) 2250H
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
MBM29DL323BD
(B)
53H A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
0
0
1
1
(W) 2253H
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
Sector Group Protection
01H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL32XTD/BD
-80/90/12
55
*1: A
-1
is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
(B): Byte mode
(W): Word mode
Table 11.7 MBM29DL324TD/BD Sector Group Protection Verify Autoselect Codes
Type
A
12
to A
20
A
6
A
1
A
0
A
-1
*1
Code (HEX)
Manufacture's Code
X
V
IL
V
IL
V
IL
V
IL
04H
Device
Code
MBM29DL324TD
Byte
X
V
IL
V
IL
V
IH
V
IL
5CH
Word
X
225CH
MBM29DL324BD
Byte
X
V
IL
V
IL
V
IH
V
IL
5FH
Word
X
225FH
Sector Group Protection
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
Table 11.8 Expanded Autoselect Code Table
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL324TD
(B)
5CH A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
1
1
0
0
(W) 225CH
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
0
MBM29DL324BD
(B)
5FH A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
1
1
1
1
1
(W) 225FH
0
0
1
0
0
0
1
0
0
1
0
1
1
1
1
1
Sector Group Protection
01H
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL32XTD/BD
-80/90/12
56
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The MBM29DL32XTD/BD feature hardware sector group protection. This feature will disable both program and
erase operations in any combination of twenty five sector groups of memory. (See Tables 9.1 and 9.2). The
sector group protection feature is enabled using programming equipment at the user's site. The device is shipped
with all sector groups unprotected.
To activate this mode, the programming equipment must force V
ID
on address pin A
9
and control pin OE, (suggest
V
ID
= 11.5 V), CE = V
IL
and A
0
= A
6
= V
IL
, A
1
= V
IH
. The sector group addresses (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
,
A
13
, and A
12
) should be set to the sector to be protected. Tables 5.1 to 8.2 define the sector address for each of
the seventy one (71) individual sectors, and tables 9.1 and 9.2 define the sector group address for each of the
twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of
the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant
during the WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector group addresses (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
,
and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical "1" code at device output DQ
0
for a protected sector.
Otherwise the device will produce "0" for unprotected sector. In this mode, the lower order addresses, except
for A
0
, A
1
, and A
6
are DON'T CARES. Address locations with A
1
= V
IL
are reserved for Autoselect manufacturer
and device codes. A
-1
requires to apply to V
IL
on byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A
20
, A
19
, A
18
,
A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
) are the desired sector group address will produce a logical "1" at DQ
0
for a protected
sector group. See Tables 11.1 to 11.8 for Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32XTD/BD
devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to
high voltage (V
ID
). During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the V
ID
is taken away from the RESET pin, all the previously protected sector
groups will be protected again. Refer to Figures 19 and 27.
MBM29DL32XTD/BD
-80/90/12
57
RESET
Hardware Reset
The MBM29DL32XTD/BD devices may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least "t
RP
" in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode "t
READY
" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional "t
RH
" before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 14 for the timing
diagram. Refer to Temporary Sector Group Unprotection for additional functionality.
Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using V
ID
.
This function is one of two provided by the WP/ACC pin.
If the system asserts V
IL
on the WP/ACC pin, the device disables program and erase functions in the two
"outermost" 8K byte boot sectors independently of whether those sectors were protected or unprotected using
the method described in "Sector Protection/Unprotection". The two outermost 8K byte boot sectors are the two
sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the
highest addresses in a top-boot-congfigured device.
(MBM29DL32XTD: SA69 and SA70, MBM29DL32XBD: SA0 and SA1)
If the system asserts V
IH
on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot
sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two
sectors depends on whether they were last protected or unprotected using the method described in "Sector
protection/unprotection".
Accelerated Program Operation
MBM29DL32XTD/BD offers accelerated program operation which enables the programming in high speed.
If the system asserts V
ACC
to the WP/ACC pin, the device automatically enters the acceleration mode and the
time required for program operation will reduce to about 60%. This function is primarily intended to allow high
speed program, so caution is needed as the sector group will temporarily be unprotected.
The system would use a fact program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be
used for programming and detection of completion during acceleration mode.
Removing V
ACC
from the WP/ACC pin returns the device to normal operation. Do not remove V
ACC
from WP/
ACC pin while programming. See Figure 21.
MBM29DL32XTD/BD
-80/90/12
58
Table 12 MBM29DL32XTD/BD Command Definitions
Command
sequence
Bus
write
cycles
req'd
First bus
write cycle
Second bus
write cycle
Third bus
write cycle
Fourth bus
read/write
cycle
Fifth bus
write cycle
Sixth bus
write cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset
Word
1
XXXH F0H
--
--
--
--
--
--
--
--
--
--
Byte
Read/Reset
Word
3
555H
AAH
2AAH
55H
555H
F0H
RA
RD
--
--
--
--
Byte
AAAH
555H
AAAH
Autoselect
Word
3
555H
AAH
2AAH
55H
(BA)
555H
90H
--
--
--
--
--
--
Byte
AAAH
555H
(BA)
AAAH
Program
Word
4
555H
AAH
2AAH
55H
555H
A0H
PA
PD
--
--
--
--
Byte
AAAH
555H
AAAH
Program Suspend
1
BA
B0H
--
--
--
--
--
--
--
--
--
--
Program Resume
1
BA
30H
--
--
--
--
--
--
--
--
--
--
Chip Erase
Word
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
10H
Byte
AAAH
555H
AAAH
AAAH
555H
AAAH
Sector Erase
Word
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
SA
30H
Byte
AAAH
555H
AAAH
AAAH
555H
Erase Suspend
1
BA
B0H
--
--
--
--
--
--
--
--
--
--
Erase Resume
1
BA
30H
--
--
--
--
--
--
--
--
--
--
Set to
Fast Mode
Word
3
555H
AAH
2AAH
55H
555H
20H
--
--
--
--
--
--
Byte
AAAH
555H
AAAH
Fast
Program *1
Word
2
XXXH
A0H
PA
PD
--
--
--
--
--
--
--
--
Byte
XXXH
Reset from
Fast Mode *1
Word
2
BA
90H
XXXH
F0H
--
--
--
--
--
--
--
--
Byte
BA
XXXH
Extended
Sector Group
Protection *2
Word
4
XXXH 60H
SPA
60H
SPA
40H
SPA
SD
--
--
--
--
Byte
Query *3
Word
1
55H
98H
--
--
--
--
--
--
--
--
--
--
Byte
AAH
Hi-ROM
Entry
Word
3
555H
AAH
2AAH
55H
555H
88H
--
--
--
--
--
--
Byte
AAAH
555H
AAAH
Hi-ROM
Program *4
Word
4
555H
AAH
2AAH
55H
555H
A0H
PA
PD
--
--
--
--
Byte
AAAH
555H
AAAH
Hi-ROM
Erase *4
Word
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
HRA
30H
Byte
AAAH
555H
AAAH
AAAH
555H
Hi-ROM
Exit *4
Word
4
555H
AAH
2AAH
55H
(HRBA
)
555H
90H XXXH 00H
--
--
--
--
Byte
AAAH
555H
(HRBA
)
AAAH
MBM29DL32XTD/BD
-80/90/12
59
Notes: 1. Address bits A
11
to A
20
= X = "H" or "L" for all address commands except or Program Address (PA), Sector
Address (SA), and Bank Address (BA).
2. Bus operations are defined in Tables 3 and 4.
3. RA =
Address of the memory location to be read
PA =
Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA =
Address of the sector to be erased. The combination of A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and
A
12
will uniquely select any sector.
BA =
Bank Address (A
15
to A
20
)
4. RD =
Data read from location RA during read operation.
PD =
Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A
6
, A
1
, A
0
) = (0, 1, 0).
SD =
Sector group protection verify data. Output 01H at protected sector group addresses and output
00H at unprotected sector group addresses.
6. HRA = Address of the Hi-ROM area
29DL32XTD (Top Boot Type)
Word Mode: 1F8000H to 1FFFFFH
Byte Mode: 3F0000H to 3FFFFFH
29DL32XBD (Bottom Boot Type) Word Mode: 000000H to 007FFFH
Byte Mode: 000000H to 00FFFFH
7. HRBA =Bank Address of the Hi-ROM area
29DL32XTD (Top Boot Type)
:A
15
= A
16
= A
17
= A
18
= A
19
= A
20
= 1
29DL32XBD (Bottom Boot Type) :A
15
= A
16
= A
17
= A
18
= A
19
= A
20
= 0
8. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A
0
to A
10
Byte Mode: AAAH or 555H to addresses A
1
and A
0
to A
10
9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*1:This command is valid while Fast Mode.
*2:This command is valid while RESET = V
ID
.
*3:The valid addresses are A
6
to A
0
.
*4:This command is valid while Hi-ROM mode.
MBM29DL32XTD/BD
-80/90/12
60
s
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed
to bank being read, the commands have priority than reading. Table 12 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Also the Program Suspend (B0H) and Program Resume (30H) commands
are valid only while the Program operation is in progress. Moreover both Read/Reset commands are functionally
equivalent, resetting the device to the read mode. Please note that commands are always written at DQ
0
to DQ
7
and DQ
8
to DQ
15
bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
5
= 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and an actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA)00H retrieves the manufacture code of 04H. A
read cycle from address (BA)01H for
16((BA)02H for
8) returns the device code (MBM29DL321TD = 59H and
MBM29DL321BD = 5AH for
8 mode; MBM29DL321TD = 2259H and MBM29DL321BD = 225AH for
16 mode).
(MBM29DL322TD = 55H and MBM29DL322BD = 56H for
8 mode; MBM29DL322TD = 2255H and
MBM29DL322BD = 2256H for
16 mode). (MBM29DL323TD = 50H and MBM29DL323BD = 53H for
8 mode;
MBM29DL323TD = 2250H and MBM29DL323BD = 2253H for
16 mode). (MBM29DL324TD = 5CH and
MBM29DL324BD = 5FH for
8 mode; MBM29DL324TD = 225CH and MBM29DL324BD = 225FH for
16 mode).
(See Tables 11.1 to 11.8.)
All manufacturer and device codes will exhibit odd parity with DQ
7
defined as the parity bit. Sector state (protection
or unprotection) will be informed by address (BA)02H for
16 ((BA)04H for
8). Scanning the sector group
addresses (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical "1" at
device output DQ
0
for a protected sector group. The programming verification should be performed by verify
sector group protection on the protected sector. (See Tables 8 and 9.)
MBM29DL32XTD/BD
-80/90/12
61
The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and
device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command
sequence into the register and then Autoselect command should be written into the bank to be read.
If the software (program code) for Autoselect command is stored into the Flash memory, the device and
manufacture codes should be read from the other bank where is not contain the software.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two "unlock" write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit),
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 13,
Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by
the system at this particular instance of time. Hence, Data Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only
erase operations can convert "0"s to "1"s.
Figure 22 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit), or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ
7
is "1" (See Write Operation Status section.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time
All sectors + Chip Program Time (Preprogramming)
Figure 23 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
MBM29DL32XTD/BD
-80/90/12
62
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data = 30H) is latched on the rising edge of CE or WE which happens first.
After time-out of "t
TOW
" from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 12. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than "t
TOW
" otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "t
TOW
"
from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase
command(s). If another falling edge of CE or WE, whichever happens first occurs within the "t
TOW
" time-out
window the timer is reset. (Monitor DQ
3
to determine if the sector erase timer window is still open, see section
DQ
3
, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period
will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once
execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow
them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the
sector erase buffer may be done in any sequence and with any number of sectors (0 to 38).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit), or
RY/BY.
The sector erase begins after the "t
TOW
" time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ
7
is "1" (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)]
Number of Sector
Erase
In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe.
Figure 23 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
(B0H) during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Writing the Erase Resume command (30H) resumes the erase operation. The bank addresses of sector being
erasing or suspending should be set when writting the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of "t
SPD
" to suspend the erase operation. When the devices have entered the erase-suspended mode, the
MBM29DL32XTD/BD
-80/90/12
63
RY/BY output pin will be at Hi-Z and the DQ
7
bit will be at logic "1", and DQ
6
will stop toggling. The user must
use the address of the erasing sector for reading DQ
6
and DQ
7
to determine if the erase operation has been
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ
2
to toggle. (See the section on DQ
2
.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ
2
to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ
7
or by the Toggle Bit I
(DQ
6
) which is the same as the regular Program operation. Note that DQ
7
must be read from the Program address
while DQ
6
can be read from any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30H) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
MBM29DL32XTD/BD
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64
Extended Command
(1) Fast Mode
MBM29DL32XTD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also executed
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. The first cycle must contain the bank address. (Refer to the Figure 28.) The V
CC
active current is
required even CE = V
IH
during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 28.)
(3) Extended Sector Group Protection
In addition to normal sector group protection, the MBM29DL32XTD/BD has Extended Sector Group
Protection as extended function. This function enable to protect sector group by forcing V
ID
on RESET pin
and write a command sequence. Unlike conventional procedure, it is not necessary to force V
ID
and control
timing for control pins. The only RESET pin requires V
ID
for sector group protection in this mode. The extended
sector group protection requires V
ID
on RESET pin. With this condition, the operation is initiated by writing
the set-up command (60H) into the command register. Then, the sector group addresses pins (A
20
, A
19
, A
18
,
A
17
, A
16
, A
15
, A
14
, A
13
and A
12
) and (A
6
, A
1
, A
0
) = (0, 1, 0) should be set to the sector group to be protected
(recommend to set V
IL
for the other addresses pins), and write extended sector group protection command
(60H). A sector group is typically protected in 250
s. To verify programming of the protection circuitry, the
sector group addresses pins (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and A
12
) and (A
6
, A
1
, A
0
) = (0, 1, 0) should
be set and write a command (40H). Following the command write, a logical "1" at device output DQ
0
will
produce for protected sector in the read operation. If the output data is logical "0", please repeat to write
extended sector group protection command (60H) again. To terminate the operation, it is necessary to set
RESET pin to V
IH
. (Refer to the Figures 20 and 29.)
(4) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-
compatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98H) into the command register. The bank address
should be set when writing this command. Then the device information can be read from the bank, and an
actual data of memory cell be read from the another bank. Following the command write, a read cycle from
specific address retrives device information. Please note that output data of upper byte (DQ
8
to DQ
15
) is "0"
in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the
read/reset command sequence into the register. (See Table 15.)
MBM29DL32XTD/BD
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65
Hidden ROM (Hi-ROM) Region
The Hi-ROM feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the Hi-ROM region is protected, any further
modification of that region is impossible. This ensures the security of the ESN once the product is shipped to
the field.
The Hi-ROM region is 64K bytes in length and is stored at the same address of the 8KB
8 sectors. The
MBM29DL32XTD occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode 1F8000H to
1FFFFFH) and the MBM29DL32XBD type occupies the address of the byte mode 000000H to 00FFFFH (word
mode 000000H to 007FFFH). After the system has written the Enter Hi-ROM command sequence, the system
may read the Hi-ROM region by using the addresses normally occupied by the boot sectors. That is, the device
sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation
continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the
device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.
Hidden ROM (Hi-ROM) Entry Command
MBM29DL32XTD/BD has a Hidden ROM area with One Time Protect function. This area is to enter the security
code and to unable the change of the code once set. Program/erase is possible in this area until it is protected.
However, once it is protected, it is impossible to unprotect, so please use this with caution.
Hidden ROM area is 64K Byte and in the same address area of 8KB sector. The address of top boot is 3F0000H
to 3FFFFFH at byte mode (1F8000H to 1FFFFFH at word mode) and the bottom boot is 000000H to 00FFFFH
at byte mode (000000H to 007FFFH at word mode). These areas are normally the boot block area (8KB
8
sector). Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called
as Hidden ROM mode when the Hidden ROM area appears.
Sector other than the boot block area could be read during Hidden ROM mode. Read/program/earse of the
Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to
exit the Hidden ROM mode. The bank address of the Hidden ROM should be set on the third cycle of this reset
command sequence.
In case of MBM29DL321TD/BD, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute
multi-function mode between the Hidden ROM area and Bank 2 Region.
Hidden ROM (Hi-ROM) Program Command
To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden
ROM mode. This command is same as the program command in the past except to write the command during
Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ
7
data poling, DQ
6
toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address
other than the Hidden ROM area is selected to program, the data of the address will be changed.
Hidden ROM (Hi-ROM) Erase Command
To erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode.
This command is same as the sector erase command in the past except to write the command during Hidden
ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ
7
data poling,
DQ
6
toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address
other than the Hidden ROM area is selected, the data of the sector will be changed.
MBM29DL32XTD/BD
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66
Hidden ROM (Hi-ROM) Protect Command
There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup
command(60H), set the sector address in the Hidden ROM area and (A
6
, A
1
, A
0
) = (0,1,0), and write the sector
group protect command(60H) during the Hidden ROM mode. The same command sequence could be used
because except that it is in the Hidden ROM mode and that it does not apply high voltage to RESET pin, it is
the same as the extension sector group protect in the past. Please refer to "Function Explanation Extended
Command (3) Extentended Sector Group Protection" for details of extention sector group protect setting.
The other is to apply high voltage (V
ID
) to A
9
and OE, set the sector address in the Hidden ROM area and (A
6
,
A
1
, A
0
) = (0,1,0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high
voltage (V
ID
) to A
9
, specify (A
6
, A
1
, A
0
) = (0,1,0) and the sector address in the Hidden ROM area, and read.
When "1" appears to DQ
0
, the protect setting is completed. "0" will appear to DQ
0
if it is not protected. Please
apply write pulse agian. The same command sequence could be used for the above method because other than
the Hidden ROM mode, it is the same as the sector group protect in the past. Please refer to "Function Explanation
Secor Group Protection" for details of sector group protect setting
Other sector group will be effected if the address other than the Hidden ROM area is selected for the sectoer
group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay closest
attention.
Write Operation Status
Detailed in Table 13 are all the status flags that can determine the status of the bank for the current mode
operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory
cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The
information on DQ
2
is address sensitive. This means that if an address from an erasing sector is consectively
read, then the DQ
2
bit will toggle. However, DQ
2
will not toggle if an address from a non-erasing sector is
consectively read. This allows the user to determine which sectors are erasing and which are not.
The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there
is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>,
[2] <non-busy bank>, [3] <busy bank>, the DQ
6
is toggling in the case of [1] and [3]. In case of [2], the data of
memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ
6
will not be toggled
in the [1] and [3].
In the erase suspend read mode, DQ
2
is toggled in the [1] and [3]. In case of [2], the data of memory cell is
outputted.
MBM29DL32XTD/BD
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67
*: Successive reads from the erasing or erase-suspend sector will cause DQ
2
to toggle. Reading from non-erase
suspend sector address will indicate logic "1" at the DQ
2
bit.
Note: 1.DQ
0
and DQ
1
are reserve pins for future use.
2.DQ
4
is Fujitsu internal use only.
Table 13 Hardware Sequence Flags
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle*
Program
Suspended
Mode
Program Suspend Read
(Program Suspended Sector)
Data
Data
Data Data
Data
Program Suspend Read
(Non-Program Suspended Sector)
Data
Data
Data Data
Data
Erase
Suspended
Mode
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
0
0
1*
Exceeded
Time Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A
MBM29DL32XTD/BD
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68
DQ
7
Data Polling
The MBM29DL32XTD/BD devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ
7
. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded
Erase Algorithm, an attempt to read the device will produce a "0" at the DQ
7
output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ
7
output. The flowchart
for Data Polling (DQ
7
) is shown in Figure 24.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ
7
is active for approximately 1
s, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
7
is active for approximately 400
s, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTD/BD data pins (DQ
7
)
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ
7
at one instant of time and then that byte's valid data at the next instant of time.
Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 13.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The MBM29DL32XTD/BD also feature the "Toggle Bit I" as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1
s and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ
6
to toggle.
MBM29DL32XTD/BD
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69
The system can use DQ
6
to determine whether a sector is actively erasing or is erase-suspended. When a bank
is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ
6
toggles. When a bank enters the
Erase Suspend mode, DQ
6
stops toggling. Successive read cycles during the erase-suspend-program cause
DQ
6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a "1". This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 3 and 4.
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the devices have exceeded timing limits, the
DQ
5
bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low ("0"), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
3
prior to and following each subsequent Sector Erase command. If DQ
3
were high on
the second status check, the command may not have been accepted.
See Table 13: Hardware Sequence Flags.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic "1" at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
MBM29DL32XTD/BD
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70
For example, DQ
2
and DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
(DQ
2
toggles while DQ
6
does not.) See also Table 14 and Figure 12.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Table 14 Toggle Bit Status
Note: Successive reads from the erasing or erase-suspend sector will cause DQ
2
to toggle. Reading from non-
erase suspend sector address will indicate logic "1" at the DQ
2
bit.
RY/BY
Ready/Busy
The MBM29DL32XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL32XTD/BD are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to Figures 15, 16 and 17 for the timing diagram.
Data Protection
The MBM29DL32XTD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle (Note)
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle
1 (Note)
MBM29DL32XTD/BD
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71
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(min). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the V
CC
level
is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when V
CC
is above V
LKO
(min).
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
MBM29DL32XTD/BD
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72
Description
A
0
to A
6
DQ
0
to DQ
15
Query-unique ASCII string
"QRY"
10h
11h
12h
0051h
0052h
0059h
Primary OEM Command Set
2h: AMD/FJ standard type
13h
14h
0002h
0000h
Address for Primary
Extended Table
15h
16h
0040h
0000h
Alternate OEM Command
Set (00h = not applicable)
17h
18h
0000h
0000h
Address for Alternate OEM
Extended Table
19h
1Ah
0000h
0000h
V
CC
Min. (write/erase)
D7-4: volt, D3-0: 100 mvolt
1Bh
0027h
V
CC
Max. (write/erase)
D7-4: volt, D3-0: 100 mvolt
1Ch
0036h
V
PP
Min. voltage
1Dh
0000h
V
PP
Max. voltage
1Eh
0000h
Typical timeout per single
byte/word write 2
N
s
1Fh
0004h
Typical timeout for Min. size
buffer write 2
N
s
20h
0000h
Typical timeout per individual
block erase 2
N
ms
21h
000Ah
Typical timeout for full chip
erase 2
N
ms
22h
0000h
Max. timeout for byte/word
write 2
N
times typical
23h
0005h
Max. timeout for buffer write
2
N
times typical
24h
0000h
Max. timeout per individual
block erase 2
N
times typical
25h
0004h
Max. timeout for full chip
erase 2
N
times typical
26h
0000h
Device Size = 2
N
byte
27h
0016h
Flash Device Interface
description
28h
29h
0002h
0000h
Max. number of byte in
multi-byte write = 2
N
2Ah
2Bh
0000h
0000h
Number of Erase Block
Regions within device
2Ch
0002h
Erase Block Region 1
Information
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 2
Information
31h
32h
33h
34h
003Eh
0000h
0000h
0001h
Table 15 Common Flash Memory Interface Code
Description
A
0
to A
6
DQ
0
to DQ
15
Query-unique ASCII string
"PRI"
40h
41h
42h
0050h
0052h
0049h
Major version number, ASCII
43h
0031h
Minor version number, ASCII
44h
0031h
Address Sensitive Unlock
0h = Required
1h = Not Required
45h
0000h
Erase Suspend
0h = Not Supported
1h = To Read Only
2h = To Read & Write
46h
0002h
Sector Protection
0h = Not Supported
X = Number of sectors in per
group
47h
0001h
Sector Temporary
Unprotection
00h = Not Supported
01h = Supported
48h
0001h
Sector Protection Algorithm
49h
0004h
Number of Sector for Bank 2
00h = Not Supported
3Fh = MBM29DL321TD
38h = MBM29DL322TD
30h = MBM29DL323TD
20h = MBM29DL324TD
3Fh = MBM29DL321BD
38h = MBM29DL322BD
30h = MBM29DL323BD
20h = MBM29DL324BD
4Ah
00XXh
Burst Mode Type
00h = Not Supported
4Bh
0000h
Page Mode Type
00h = Not Supported
4Ch
0000h
ACC (Acceleration) Supply
Minimum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
4Dh
0085h
ACC (Acceleration) Supply
Maximum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
4Eh
0095h
Boot Type
02h = MBM29DL32XBD
03h = MBM29DL32XTD
4Fh
00XXh
MBM29DL32XTD/BD
-80/90/12
73
s
FLOW CHART
No
Yes
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Write Program Command
Sequence
(See below)
Data Polling Device
Increment Address
Last Address
?
Program Address/Program Data
Start
Programming Completed
Figure 22 Embedded Program
TM
Algorithm
EMBEDDED ALGORITHMS
* : The sequence is applied for
16 mode.
The addresses differ from
8 mode.
MBM29DL32XTD/BD
-80/90/12
74
555H/AAH
2AAH/55H
555H/AAH
555H/80H
555H/10H
2AAH/55H
555H/AAH
2AAH/55H
555H/AAH
555H/80H
2AAH/55H
Additional sector
erase commands
are optional.
Write Erase Command
Sequence
(See below)
Data Polling or Toggle Bit
Successfully Completed
Chip Erase Command Sequence*
(Address/Command):
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
Sector Address/30H
Sector Address/30H
Sector Address/30H
Erasure Completed
Start
Figure 23 Embedded Erase
TM
Algorithm
EMBEDDED ALGORITHMS
* : The sequence is applied for
16 mode.
The addresses differ from
8 mode.
MBM29DL32XTD/BD
-80/90/12
75
DQ
7
= Data?
No
No
DQ
7
= Data?
DQ
5
= 1?
Yes
Yes
No
Read
(DQ
0
to DQ
7
)
Addr. = VA
Read
(DQ
0
to DQ
7
)
Addr. = VA
Yes
Start
Fail
Pass
Figure 24 Data Polling Algorithm
Note: DQ
7
is rechecked even if DQ
5
= "1" because DQ
7
may change simultaneously with DQ
5
.
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase
MBM29DL32XTD/BD
-80/90/12
76
DQ
6
= Toggle
?
Yes
No
DQ
6
= Toggle
?
DQ
5
= 1?
Yes
No
No
Yes
Read
(DQ
0
to DQ
7
)
Addr. = VA
Read
(DQ
0
to DQ
7
)
Addr. = VA
Start
Pass
Fail
Figure 25 Toggle Bit Algorithm
Note: DQ
6
is rechecked even if DQ
5
= "1" because DQ
6
may stop toggling at the same time as
DQ
5
changing to "1" .
VA = Bank address being executed
Embedded Algorithm.
MBM29DL32XTD/BD
-80/90/12
77
Setup Sector Group Addr.
(A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, A
12
)
Activate WE Pulse
WE = V
IH
, CE = OE = V
IL
(A
9
should remain V
ID
)
Yes
Yes
No
No
OE = V
ID
, A
9
= V
ID
,
A
6
= CE = V
IL
, RESET = V
IH
A
0
= V
IL
, A
1
= V
IH
PLSCNT = 1
Time out 100
s
Read from Sector Group
(Addr. = SGA, A
0
= V
IL
,
A
1
= V
IH
, A
6
= V
IL
)*
Remove V
ID
from A
9
Write Reset Command
Increment PLSCNT
No
Yes
Protect Another Sector
Group ?
Data = 01H?
PLSCNT = 25?
Device Failed
Remove V
ID
from A
9
Write Reset Command
Start
Sector Group Protection
Completed
Figure 26 Sector Group Protection Algorithm
* : A
-1
is V
IL
on byte mode.
MBM29DL32XTD/BD
-80/90/12
78
RESET = V
ID
(Note 1)
Perform Erase or
Program Operations
RESET = V
IH
Start
Temporary Sector Group
Unprotection Completed
(Note 2)
Figure 27 Temporary Sector Group Unprotection Algorithm
Notes: 1. All protected sector groups are unprotected.
2. All previously protected sector groups are protected once again.
MBM29DL32XTD/BD
-80/90/12
79
Figure 28 Embedded Program
TM
Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555H/AAH
2AAH/55H
XXXH/A0H
555H/20H
Verify Byte?
No
Program Address/Program Data
Data Polling Device
Last Address
?
Programming Completed
(BA)
XXXH/90H
XXXH/F0H
Increment Address
No
Yes
Yes
Set Fast Mode
In Fast Program
Reset Fast Mode
Note: The sequence is applied for
16 mode.
The addresses differ from
8 mode.
MBM29DL32XTD/BD
-80/90/12
80
Figure 29 Extended Sector Group Protection Algorithm
To Sector Group Protection
Yes
No
No
PLSCNT = 1
Protection Other Sector
Start
Sector Group Protection
Extended Sector Group
Completed
Remove
V
ID
from RESET
Write Reset Command
RESET = V
ID
Wait to 4
s
Protection Entry?
To Setup Sector Group
Protection Write XXXH/60H
Write SGA/60H
(A
0
= V
IL
, A
1
= V
IH
, A
6
= V
IL
)
Time Out 250
s
To Verify Sector Group
Protection Write SGA/40H
(A
0
= V
IL
, A
1
= V
IH
, A
6
= V
IL
)
Data = 01H?
Group ?
Device is Operating in
Temporary Sector Group
Read from Sector Group
(A
0
= V
IL
, A
1
= V
IH
, A
6
= V
IL
)
Increment PLSCNT
No
Yes
Yes
Unprotection Mode
Address
Setup Next Sector Group
Address
No
Yes
PLSCNT = 25?
Device Failed
Remove V
ID
from RESET
Write Reset Command
MBM29DL32XTD/BD
-80/90/12
81
s
ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29DL32X
T
D
80
PFTN
DEVICE NUMBER/DESCRIPTION
MBM29DL32X
32Mega-bit (4M
8-Bit or 2M
16-Bit) CMOS Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PBT = Fine pitch Ball Grid Array
Package (FBGA)
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
Valid Combinations
MBM29DL321TD/BD
80
90
12
PFTN
PFTR
PBT
MBM29DL322TD/BD
MBM29DL323TD/BD
MBM29DL324TD/BD
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Fujitsu sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.
MBM29DL32XTD/BD
-80/90/12
82
s
PACKAGE DIMENSIONS
C
1996 FUJITSU LIMITED F48029S-2C-2
Details of "A" part
0.15(.006)
MAX
0.35(.014)
MAX
0.15(.006)
0.25(.010)
INDEX
"A"
18.400.20
(.724.008)
20.000.20
(.787.008)
19.000.20
(.748.008)
0.10(.004)
0.500.10
(.020.004)
0.150.05
(.006.002)
11.50REF
(.460)
0.50(.0197)
TYP
0.200.10
(.008.004)
0.05(0.02)MIN
.043
.002
+.004
0.05
+0.10
1.10
M
0.10(.004)
(STAND OFF)
1
24
25
48
LEAD No.
*
*
12.000.20
(.472.008)
(Mounting height)
48-pin plastic TSOP(I)
(FPT-48P-M19)
Dimensions in mm (inches)
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
(Continued)
C
1996 FUJITSU LIMITED F48030S-2C-2
Details of "A" part
0.15(.006)
MAX
0.35(.014)
MAX
0.15(.006)
0.25(.010)
INDEX
"A"
18.400.20
(.724.008)
20.000.20
(.787.008)
19.000.20
(.748.008)
0.10(.004)
0.500.10
(.020.004)
0.150.10
(.006.002)
11.50(.460)REF
0.50(.0197)
TYP
0.200.10
(.008.004)
0.05(0.02)MIN
.043
.002
+.004
0.05
+0.10
1.10
M
0.10(.004)
(STAND OFF)
1
24
25
48
LEAD No.
*
*
12.000.20(.472.008)
(Mounting height)
48-pin plastic TSOP(I)
(FPT-48P-M20)
Dimensions in mm (inches)
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
MBM29DL32XTD/BD
-80/90/12
83
(Continued)
57-pin plastic FBGA
(BGA-57P-M01)
C
1998 FUJITSU LIMITED B57001S-1C-1
13.950.05(.549.002)
.041
.004
+.006
0.10
+0.15
1.05
(Mounting height)
0.360.10
(.014.004)
(Stand off)
7.950.05
(.313.002)
0.10(.004)
C0.25(.010)
INDEX
0.80(.031)
TYP
(4.00(.157))
(5.60(.220))
0.80(.031)
TYP
(5.60(.220))
(7.20(.283))
(8.80(.346))
M L K J H G F E D C B A
8
7
6
5
4
3
2
1
INDEX BALL
57-0.450.05
(57-.018.002)
M
0.08(.003)
Dimensions in mm (inches)
MBM29DL32XTD/BD
-80/90/12
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9909
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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