DS05-20881-6E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
32 M (4 M
8/2 M
16) BIT Dual Operation
MBM29DL32XTE/BE
80
/
90
s
DESCRIPTION
The MBM29DL32XTE/BE are a 32 M-bit, 3.0 V-only Flash memory organized as 4 Mbytes of 8 bits each or
2 Mwords of 16 bits each. These devices are designed to be programmed in-system with the standard system
3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations. The devices can also
be reprogrammed in standard EPROM programmers.
MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate
memory arrays for operations. It is the Fujitsu's standard 3 V only Flash memories, with the additional capability
of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either
a program or an erase) operation is simultaneously taking place on the other bank.
(Continued)
s
PRODUCT LINE UP
s
PACKAGES
Part No.
MBM29DL32XTE/BE
80
90
Power Supply Voltage V
CC
(V)
3.3
3.0
Max Address Access Time (ns)
80
90
Max CE Access Time (ns)
80
90
Max OE Access Time (ns)
30
35
+
0.3
-
0.3
+
0.6
-
0.3
48-pin plastic TSOP (1)
48-pin plastic TSOP (1)
63-ball plastic FBGA
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-63P-M01)
Marking Side
Marking Side
MBM29DL32XTE/BE
80
/90
2
(Continued)
In the MBM29DL32XTE/BE, a new design concept is implemented, so called "Sliding Bank Architecture". Under
this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable
(OE) controls.
The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
Typically, each sector can be programmed and verified in about 0.5 seconds.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the
factory.
Internally generated and regulated voltages are provided for the program and erase operations. A low V
CC
detector
automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ
7
, by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase
cycle has been completed, the devices internally reset to the read mode.
The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously
via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
MBM29DL32XTE/BE
80
/90
3
s
FEATURES
0.23
m Process Technology
Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to "MBM29DL32XTE/BE Device Bank Divisions" in
"
s
FEATURES")
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
Single 3.0 V read, program, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (1) (Package suffix : TN
-
Normal Bend Type, TR
-
Reversed Bend Type)
63-ball FBGA (Package suffix : PBT)
Minimum 100,000 program/erase cycles
High performance
80 ns maximum access time
Sector erase architecture
Eight 4 Kword and sixty-three 32 Kword sectors in word mode
Eight 8 Kbyte and sixty-three 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T
=
Top sector
B
=
Bottom sector
HiddenROM region
64 Kbyte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector group protection/unprotection status
At V
ACC
, increases program performance
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
Low V
CC
write inhibit
2.5 V
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
(Continued)
MBM29DL32XTE/BE
80
/90
4
(Continued)
Sector Group Protection Set function by Extended sector group protection command
Fast Programming Function by Extended Command
Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
In accordance with CFI (Common Flash Memory Interface)
MBM29DL32XTE/BE Device Bank Divisions
Device
Part Number
Organiza-
tion
Bank 1
Bank 2
Mega-
bits
Sector sizes
Mega-
bits
Sector sizes
MBM29DL322TE/BE
8/
16
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
28 Mbit
Fifty-six
64 Kbyte/32 Kword
MBM29DL323TE/BE
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
24 Mbit
Forty-eight
64 Kbyte/32 Kword
MBM29DL324TE/BE
16 Mbit
Eight 8 Kbyte/4 Kword,
thirty-one 64 Kbyte/
32 Kword
16 Mbit
Thirty-two
64 Kbyte/32 Kword
MBM29DL32XTE/BE
80
/90
5
s
PIN ASSIGNMENTS
(Continued)
TSOP (1)
(FPT-48P-M19)
(FPT-48P-M20)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
19
A
20
WE
RESET
N.C.
WP/ACC
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Normal Bend
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
(Marking Side)
Reverse Bend
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
WP/ACC
N.C.
RESET
WE
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
(Marking Side)
MBM29DL32XTE/BE
80
/90
6
(Continued)
FBGA
(TOP VIEW)
(Marking Side)
(BGA-63P-M01)
* : Peripheral Balls on each corner are shorted together via substrate but not connected to the die.
E7
A
14
E6
A
10
E5
N.C.
E4
A
18
E3
A
6
E2
A
2
G7
A
16
G4
DQ
2
G3
DQ
0
G2
A
0
H7
BYTE
H6
DQ
14
H5
DQ
12
H4
DQ
10
H3
DQ
8
H2
CE
F7
A
15
F6
A
11
F3
A
5
F2
A
1
J7
DQ
15
/A
-1
J6
DQ
13
J5
V
CC
J4
DQ
11
J3
DQ
9
J2
OE
K7
V
SS
K6
DQ
6
K5
DQ
4
K4
DQ
3
K3
DQ
1
K2
V
SS
L7
N.C.
L2
N.C.
L1
N.C.
L8
N.C.
D7
A
12
D6
A
8
D5
RESET
D4
WP/ACC
D3
A
17
D2
A
4
M7
N.C.
M2
N.C.
M1
N.C.
M8
N.C.
C7
A
13
C6
A
9
C5
WE
C4
RY/BY
C3
A
7
C2
A
3
B7
N.C.
B1
N.C.
B8
N.C.
A7
N.C.
A2
N.C.
A1
N.C.
A8
N.C.
F5
A
19
G5
DQ
5
F4
A
20
G6
DQ
7
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
MBM29DL32XTE/BE
80
/90
7
s
PIN DESCRIPTIONS
MBM29DL32XTE/BE Pin Configuration
Pin Name
Function
A
20
to A
0
, A
-1
Address Input
DQ
15
to DQ
0
Data Input/Output
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector Group Unprotection
BYTE
Selects 8-bit or 16-bit mode
WP/ACC
Hardware Write Protection/Program Acceleration
N.C.
No Internal Connection
V
SS
Device Ground
V
CC
Device Power Supply
MBM29DL32XTE/BE
80
/90
8
s
BLOCK DIAGRAM
s
LOGIC SYMBOL
V
SS
V
CC
Bank 2 Address
Bank 1 Address
WE
CE
A
20
to A
0
(A
-1
)
OE
BYTE
WP/ACC
RESET
DQ
15
to DQ
0
RY/BY
State
Control
&
Command
Register
X-Decoder
X-Decoder
Cell Matrix
(Bank 2)
Cell Matrix
(Bank 1)
Y-Gating & Data Latch
Y-Gating &
Data Latch
DQ
15
to DQ
0
Status
Control
21
A
20
to A
0
WE
OE
CE
DQ
15
to DQ
0
16 or 8
BYTE
WP/ACC
RESET
A
-1
RY/BY
MBM29DL32XTE/BE
80
/90
9
s
DEVICE BUS OPERATION
MBM29DL32XTE/BE User Bus Operations (BYTE
=
=
=
=
V
IH
)
Legend : L
=
V
IL
, H
=
V
IH
, X
=
V
IL
or V
IH
,
=
Pulse input. See DC Characteristics for voltage levels.
*1 : Manufacturer and device codes are accessed via a command register write sequence. See "MBM29DL32XTE/
BE Command Definitions".
*2 : Refer to the section on Sector Group Protection.
*3 : WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
*4 : V
CC
=
3.3 V
10
%
*5 : Also used for the extended sector group protection.
Operation
CE
OE WE
A
0
A
1
A
6
A
9
DQ
15
to
DQ
0
RESET
WP/ACC
Auto-Select Manufacturer Code*
1
L
L
H
L
L
L
V
ID
Code
H
X
Auto-Select Device Code*
1
L
L
H
H
L
L
V
ID
Code
H
X
Read*
3
L
L
H
A
0
A
1
A
6
A
9
D
OUT
H
X
Standby
H
X
X
X
X
X
X
High-Z
H
X
Output Disable
L
H
H
X
X
X
X
High-Z
H
X
Write (Program/Erase)
L
H
L
A
0
A
1
A
6
A
9
D
IN
H
X
Enable Sector Group Protection*
2,
*
4
L
V
ID
L
H
L
V
ID
X
H
X
Verify Sector Group Protection*
2,
*
4
L
L
H
L
H
L
V
ID
Code
H
X
Temporary Sector Group Unprotection*
5
X
X
X
X
X
X
X
X
V
ID
X
Reset (Hardware) /Standby
X
X
X
X
X
X
X
High-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
L
MBM29DL32XTE/BE
80
/90
10
MBM29DL32XTE/BE User Bus Operations (BYTE
=
=
=
=
V
IL
)
Legend : L
=
V
IL
, H
=
V
IH
, X
=
V
IL
or V
IH
,
=
Pulse input. See DC Characteristics for voltage levels.
*1 : Manufacturer and device codes are accessed via a command register write sequence. See "MBM29DL32XTE/
BE Command Definitions".
*2 : Refer to the section on Sector Group Protection.
*3 : WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
*4 : V
CC
=
3.3 V
10
%
*5 : Also used for the extended sector group protection.
Operation
CE
OE WE
DQ
15
/A-
1
A
0
A
1
A
6
A
9
DQ
7
to
DQ
0
RESET
WP/ACC
Auto-Select Manufacturer Code*
1
L
L
H
L
L
L
L
V
ID
Code
H
X
Auto-Select Device code*
1
L
L
H
L
H
L
L
V
ID
Code
H
X
Read*
3
L
L
H
A-
1
A
0
A
1
A
6
A
9
D
OUT
H
X
Standby
H
X
X
X
X
X
X
X
High-Z
H
X
Output Disable
L
H
H
X
X
X
X
X
High-Z
H
X
Write (Program/Erase)
L
H
L
A-
1
A
0
A
1
A
6
A
9
D
IN
H
X
Enable Sector Group Protection
*
2,
*
4
L
V
ID
L
L
H
L
V
ID
X
H
X
Verify Sector Group Protection*
2,
*
4
L
L
H
L
L
H
L
V
ID
Code
H
X
Temporary Sector Group
Unprotection*
5
X
X
X
X
X
X
X
X
X
V
ID
X
Reset (Hardware) /Standby
X
X
X
X
X
X
X
X
High-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
X
L
MBM29DL32XTE/BE
80
/90
11
MBM29DL32XTE/BE Command Definitions
(Continued)
Command
sequence
Bus
write
cy-
cles
req'd
First bus
write cycle
Second bus
write cycle
Third bus
write cycle
Fourth bus
read/write
cycle
Fifth bus
write cycle
Sixth bus
write cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/
Reset*
1
Word
1
XXXh
F0h
Byte
Read/
Reset*
1
Word
3
555h
AAh
2AAh
55h
555h
F0h
RA*
7
RD*
7
Byte
AAAh
555h
AAAh
Autoselect
Word
3
555h
AAh
2AAh
55h
(BA)
555h
90h
IA*
7
ID*
7
Byte
AAAh
555h
(BA)
AAAh
Program
Word
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
Byte
AAAh
555h
AAAh
Program
Suspend
1
BA
B0h
Program
Resume
1
BA
30h
Chip Erase
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Byte
AAAh
555h
AAAh
AAAh
555h
AAAh
Sector
Erase
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
SA
30h
Byte
AAAh
555h
AAAh
AAAh
555h
Erase Suspend
1
BA
B0h
Erase Resume
1
BA
30h
Set to
Fast Mode
Word
3
555h
AAh
2AAh
55h
555h
20h
Byte
AAAh
555h
AAAh
Fast
Program *
2
Word
2
XXXh
A0h
PA
PD
Byte
Reset from
Fast Mode
*
2
Word
2
BA
90h
XXXh
*
6
F0h
Byte
Extended
Sector
Group
Protection
*
3
Word
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
Byte
Query*
4
Word
1
(BA)
55h
98h
Byte
(BA)
AAh
MBM29DL32XTE/BE
80
/90
12
(Continued)
*1 : Both of these reset commands are equivalent.
*2 : This command is valid during Fast Mode.
*3 : This command is valid while RESET
=
V
ID
(except during HiddenROM MODE).
*4 : The valid address are A
6
to A
0
.
*5 : This command is valid during HiddenROM mode.
*6 : The data "00h" is also acceptable.
*7 : The fourth bus cycle is only for read.
Notes :
Address bits A
20
to A
11
=
X
=
"H" or "L" for all address commands except or Program Address (PA) , Sector
Address (SA) , Bank Address (BA) and Sector Group Address (SPA) .
Bus operations are defined in "MBM29DL32XTE/BE User Bus Operations (BYTE
=
V
IH
) " and
"MBM29DL32XTE/BE User Bus Operations (BYTE
=
V
IL
) ".
RA
=
Address of the memory location to be read
IA
=
Autoselect read address sets both the bank address specified at (A
19
, A
18
, A
17
, A
16
, A
15
) and all the
other A
6
, A
1
, A
0
, (A
-
1
) .
PA
=
Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA
=
Address of the sector to be erased. The combination of A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and
A
12
will uniquely select any sector.
BA
=
Bank Address (A
20
to A
15
)
RD
=
Data read from location RA during read operation.
ID
=
Device code/manufacture code for the address located by IA.
PD
=
Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
SPA
=
Sector group address to be protected. Set sector group address and (A
6
, A
1
, A
0
)
=
(0, 1, 0) .
SD
=
Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
HRA
=
Address of the HiddenROM area
29DL32XTE (Top Boot Type)
Word Mode : 1F8000h to 1FFFFFh
Byte Mode : 3F0000h to 3FFFFFh
29DL32XBE (Bottom Boot Type) Word Mode : 000000h to 007FFFh
Byte Mode : 000000h to 00FFFFh
HRBA
=
Bank Address of the HiddenROM area
29DL32XTE (Top Boot Type) : A
20
=
A
19
=
A
18
=
A
17
=
A
16
=
A
15
=
V
IH
29DL32XBE (Bottom Boot Type) : A
20
=
A
19
=
A
18
=
A
17
=
A
16
=
A
15
=
V
IL
The system should generate the following address patterns :
Word Mode : 555h or 2AAh to addresses A
10
to A
0
Byte Mode : AAAh or 555h to addresses A
10
to A
0
, and A-
1
Command
sequence
Bus
write
cy-
cles
req'd
First bus
write cycle
Second bus
write cycle
Third bus
write cycle
Fourth bus
read/write
cycle
Fifth bus
write cycle
Sixth bus
write cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
HiddenROM
Entry
Word
3
555h
AAh
2AAh
55h
555h
88h
Byte
AAAh
555h
AAAh
HiddenROM
Program *
5
Word
4
555h
AAh
2AAh
55h
555h
A0h
(
HRA
)
PA
PD
Byte
AAAh
555h
AAAh
HiddenROM
Erase *
5
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
HRA
30h
Byte
AAAh
555h
AAAh
AAAh
555h
HiddenROM
Exit *
5
Word
4
555h
AAh
2AAh
55h
(HRBA)
555h
90h
XXXh
00h
Byte
AAAh
555h
(HRBA)
AAAh
MBM29DL32XTE/BE
80
/90
13
MBM29DL322TE/BE Sector Group Protection Verify Autoselect Codes
*1 : A-
1
is for Byte mode. At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A-
1
, the lowest address.
*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*3 : When V
ID
is applied to A
9
, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous
operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank
address needs to be indicated when Autoselect mode is read out at command mode, because then it enables
to activate simultaneous operation.
Extended Autoselect Code Table
* : At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A-
1
, the lowest address.
(B) : Byte mode
(W) : Word mode
HI-Z : High-Z
Type
A
20
to A
12
A
6
A
1
A
0
A-
1
*1
Code (HEX)
Manufacture's Code
BA*
3
V
IL
V
IL
V
IL
V
IL
04h
Device
Code
MBM29DL322TE
Byte
BA*
3
V
IL
V
IL
V
IH
V
IL
55h
Word
X
2255h
MBM29DL322BE
Byte
BA*
3
V
IL
V
IL
V
IH
V
IL
56h
Word
X
2256h
Sector Group Protection
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01h
*2
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04h
A-
1
/
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL322
TE
(B) *
55h A-
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
1
0
1
0
1
(W) 2255h
0
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
MBM29DL322
BE
(B) *
56h A-
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
1
0
1
1
0
(W) 2256h
0
0
1
0
0
0
1
0
0
1
0
1
0
1
1
0
Sector Group Protection
01h
A-
1
/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL32XTE/BE
80
/90
14
MBM29DL323TE/BE Sector Group Protection Verify Autoselect Codes
*1 : A-
1
is for Byte mode. At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A-
1
, the lowest address.
*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*3 : When V
ID
is applied to A
9
, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous
operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank
address needs to be indicated when Autoselect mode is read out at command mode, because then it enables
to activate simultaneous operation.
Extended Autoselect Code Table
* : At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A-
1
, the lowest address.
(B) : Byte mode
(W) : Word mode
HI-Z : High-Z
Type
A
20
to A
12
A
6
A
1
A
0
A-
1
*1
Code (HEX)
Manufacture's Code
BA*
3
V
IL
V
IL
V
IL
V
IL
04h
Device
Code
MBM29DL323TE
Byte
BA*
3
V
IL
V
IL
V
IH
V
IL
50h
Word
X
2250h
MBM29DL323BE
Byte
BA*
3
V
IL
V
IL
V
IH
V
IL
53h
Word
X
2253h
Sector Group Protection
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01h
*2
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04h
A-
1
/
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL323
TE
(B) *
50h
A-
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
1
0
0
0
0
(W)
2250h
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
MBM29DL323
BE
(B) *
53h
A-
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
1
0
0
1
1
(W)
2253h
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
Sector Group Protection
01h
A-
1
/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL32XTE/BE
80
/90
15
MBM29DL324TE/BE Sector Group Protection Verify Autoselect Codes
*1 : A-
1
is for Byte mode. At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A-
1
, the lowest address.
*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*3 : When V
ID
is applied to A
9
, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous
operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank
address needs to be indicated when Autoselect mode is read out at command mode, because then it enables
to activate simultaneous operation.
Extended Autoselect Code Table
* : At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A-
1
, the lowest address.
(B) : Byte mode
(W) : Word mode
HI-Z : High-Z
Type
A
20
to A
12
A
6
A
1
A
0
A-
1
*1
Code (HEX)
Manufacture's Code
BA*
3
V
IL
V
IL
V
IL
V
IL
04h
Device
Code
MBM29DL324TE
Byte
BA*
3
V
IL
V
IL
V
IH
V
IL
5Ch
Word
X
225Ch
MBM29DL324BE
Byte
BA*
3
V
IL
V
IL
V
IH
V
IL
5Fh
Word
X
225Fh
Sector Group Protection
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01h
*2
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04h
A-
1
/
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL324
TE
(B) *
5Ch
A-
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
1
1
1
0
0
(W)
225Ch
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
0
MBM29DL324
BE
(B) *
5Fh
A-
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
1
1
1
1
1
(W)
225Fh
0
0
1
0
0
0
1
0
0
1
0
1
1
1
1
1
Sector Group Protection
01h
A-
1
/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29DL32XTE/BE
80
/90
16
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
Sector Address Table (MBM29DL322TE)
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA0
0
0
0
0
0
0
X
X
X
X
64/32
000000h to 00FFFFh
000000h to 007FFFh
SA1
0
0
0
0
0
1
X
X
X
X
64/32
010000h to 01FFFFh
008000h to 00FFFFh
SA2
0
0
0
0
1
0
X
X
X
X
64/32
020000h to 02FFFFh
010000h to 017FFFh
SA3
0
0
0
0
1
1
X
X
X
X
64/32
030000h to 03FFFFh
018000h to 01FFFFh
SA4
0
0
0
1
0
0
X
X
X
X
64/32
040000h to 04FFFFh
020000h to 027FFFh
SA5
0
0
0
1
0
1
X
X
X
X
64/32
050000h to 05FFFFh
028000h to 02FFFFh
SA6
0
0
0
1
1
0
X
X
X
X
64/32
060000h to 06FFFFh
030000h to 037FFFh
SA7
0
0
0
1
1
1
X
X
X
X
64/32
070000h to 07FFFFh
038000h to 03FFFFh
SA8
0
0
1
0
0
0
X
X
X
X
64/32
080000h to 08FFFFh
040000h to 047FFFh
SA9
0
0
1
0
0
1
X
X
X
X
64/32
090000h to 09FFFFh
048000h to 04FFFFh
SA10
0
0
1
0
1
0
X
X
X
X
64/32
0A0000h to 0AFFFFh 050000h to 057FFFh
SA11
0
0
1
0
1
1
X
X
X
X
64/32
0B0000h to 0BFFFFh 058000h to 05FFFFh
SA12
0
0
1
1
0
0
X
X
X
X
64/32
0C0000h to 0CFFFFh 060000h to 067FFFh
SA13
0
0
1
1
0
1
X
X
X
X
64/32
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA14
0
0
1
1
1
0
X
X
X
X
64/32
0E0000h to 0EFFFFh 070000h to 077FFFh
SA15
0
0
1
1
1
1
X
X
X
X
64/32
0F0000h to 0FFFFFh 078000h to 07FFFFh
SA16
0
1
0
0
0
0
X
X
X
X
64/32
100000h to 10FFFFh
080000h to 087FFFh
SA17
0
1
0
0
0
1
X
X
X
X
64/32
110000h to 11FFFFh
088000h to 08FFFFh
SA18
0
1
0
0
1
0
X
X
X
X
64/32
120000h to 12FFFFh
090000h to 097FFFh
SA19
0
1
0
0
1
1
X
X
X
X
64/32
130000h to 13FFFFh
098000h to 09FFFFh
SA20
0
1
0
1
0
0
X
X
X
X
64/32
140000h to 14FFFFh 0A0000h to 0A7FFFh
SA21
0
1
0
1
0
1
X
X
X
X
64/32
150000h to 15FFFFh 0A8000h to 0AFFFFh
SA22
0
1
0
1
1
0
X
X
X
X
64/32
160000h to 16FFFFh 0B0000h to 0B7FFFh
SA23
0
1
0
1
1
1
X
X
X
X
64/32
170000h to 17FFFFh 0B8000h to 0BFFFFh
SA24
0
1
1
0
0
0
X
X
X
X
64/32
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA25
0
1
1
0
0
1
X
X
X
X
64/32
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26
0
1
1
0
1
0
X
X
X
X
64/32
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA27
0
1
1
0
1
1
X
X
X
X
64/32
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA28
0
1
1
1
0
0
X
X
X
X
64/32
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA29
0
1
1
1
0
1
X
X
X
X
64/32
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA30
0
1
1
1
1
0
X
X
X
X
64/32
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31
0
1
1
1
1
1
X
X
X
X
64/32
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA32
1
0
0
0
0
0
X
X
X
X
64/32
200000h to 20FFFFh
100000h to 107FFFh
MBM29DL32XTE/BE
80
/90
17
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA33
1
0
0
0
0
1
X
X
X
X
64/32
210000h to 21FFFFh
108000h to 10FFFFh
SA34
1
0
0
0
1
0
X
X
X
X
64/32
220000h to 22FFFFh
110000h to 117FFFh
SA35
1
0
0
0
1
1
X
X
X
X
64/32
230000h to 23FFFFh
118000h to 11FFFFh
SA36
1
0
0
1
0
0
X
X
X
X
64/32
240000h to 24FFFFh
120000h to 127FFFh
SA37
1
0
0
1
0
1
X
X
X
X
64/32
250000h to 25FFFFh
128000h to 12FFFFh
SA38
1
0
0
1
1
0
X
X
X
X
64/32
260000h to 26FFFFh
130000h to 137FFFh
SA39
1
0
0
1
1
1
X
X
X
X
64/32
270000h to 27FFFFh
138000h to 13FFFFh
SA40
1
0
1
0
0
0
X
X
X
X
64/32
280000h to 28FFFFh
140000h to 147FFFh
SA41
1
0
1
0
0
1
X
X
X
X
64/32
290000h to 29FFFFh
148000h to 14FFFFh
SA42
1
0
1
0
1
0
X
X
X
X
64/32
2A0000h to 2AFFFFh 150000h to 157FFFh
SA43
1
0
1
0
1
1
X
X
X
X
64/32
2B0000h to 2BFFFFh 158000h to 15FFFFh
SA44
1
0
1
1
0
0
X
X
X
X
64/32
2C0000h to 2CFFFFh 160000h to 167FFFh
SA45
1
0
1
1
0
1
X
X
X
X
64/32
2D0000h to 2DFFFFh 168000h to 16FFFFh
SA46
1
0
1
1
1
0
X
X
X
X
64/32
2E0000h to 2EFFFFh 170000h to 177FFFh
SA47
1
0
1
1
1
1
X
X
X
X
64/32
2F0000h to 2FFFFFh 178000h to 17FFFFh
SA48
1
1
0
0
0
0
X
X
X
X
64/32
300000h to 30FFFFh
180000h to 187FFFh
SA49
1
1
0
0
0
1
X
X
X
X
64/32
310000h to 31FFFFh
188000h to 18FFFFh
SA50
1
1
0
0
1
0
X
X
X
X
64/32
320000h to 32FFFFh
190000h to 197FFFh
SA51
1
1
0
0
1
1
X
X
X
X
64/32
330000h to 33FFFFh
198000h to 19FFFFh
SA52
1
1
0
1
0
0
X
X
X
X
64/32
340000h to 34FFFFh 1A0000h to 1A7FFFh
SA53
1
1
0
1
0
1
X
X
X
X
64/32
350000h to 35FFFFh 1A8000h to 1AFFFFh
SA54
1
1
0
1
1
0
X
X
X
X
64/32
360000h to 36FFFFh 1B0000h to 1B7FFFh
SA55
1
1
0
1
1
1
X
X
X
X
64/32
370000h to 37FFFFh 1B8000h to 1BFFFFh
Bank
1
SA56
1
1
1
0
0
0
X
X
X
X
64/32
380000h to 38FFFFh 1C0000h to 1C7FFFh
SA57
1
1
1
0
0
1
X
X
X
X
64/32
390000h to 39FFFFh 1C8000h to 1CFFFFh
SA58
1
1
1
0
1
0
X
X
X
X
64/32
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA59
1
1
1
0
1
1
X
X
X
X
64/32
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA60
1
1
1
1
0
0
X
X
X
X
64/32
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA61
1
1
1
1
0
1
X
X
X
X
64/32
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA62
1
1
1
1
1
0
X
X
X
X
64/32
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA63
1
1
1
1
1
1
0
0
0
X
8/4
3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
SA64
1
1
1
1
1
1
0
0
1
X
8/4
3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
SA65
1
1
1
1
1
1
0
1
0
X
8/4
3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
SA66
1
1
1
1
1
1
0
1
1
X
8/4
3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
MBM29DL32XTE/BE
80
/90
18
(Continued)
Note : The address range is A
20
: A-
1
if in byte mode (BYTE
=
V
IL
) .
The address range is A
20
: A
0
if in word mode (BYTE
=
V
IH
) .
Sector Address Table (MBM29DL322BE)
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
1
SA67
1
1
1
1
1
1
1
0
0
X
8/4
3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
SA68
1
1
1
1
1
1
1
0
1
X
8/4
3FA000h to 3FBFFFh 1FD000h to 1FDFFFh
SA69
1
1
1
1
1
1
1
1
0
X
8/4
3FC000h to 3FDFFFh 1FE000h to 1FEFFFh
SA70
1
1
1
1
1
1
1
1
1
X
8/4
3FE000h to 3FFFFFh 1FF000h to 1FFFFFh
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA70
1
1
1
1
1
1
X
X
X
X
64/32
3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
SA69
1
1
1
1
1
0
X
X
X
X
64/32
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA68
1
1
1
1
0
1
X
X
X
X
64/32
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA67
1
1
1
1
0
0
X
X
X
X
64/32
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA66
1
1
1
0
1
1
X
X
X
X
64/32
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA65
1
1
1
0
1
0
X
X
X
X
64/32
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA64
1
1
1
0
0
1
X
X
X
X
64/32
390000h to 39FFFFh 1C8000h to 1CFFFFh
SA63
1
1
1
0
0
0
X
X
X
X
64/32
380000h to 38FFFFh 1C0000h to 1C7FFFh
SA62
1
1
0
1
1
1
X
X
X
X
64/32
370000h to 37FFFFh 1B8000h to 1BFFFFh
SA61
1
1
0
1
1
0
X
X
X
X
64/32
360000h to 36FFFFh 1B0000h to 1B7FFFh
SA60
1
1
0
1
0
1
X
X
X
X
64/32
350000h to 35FFFFh 1A8000h to 1AFFFFh
SA59
1
1
0
1
0
0
X
X
X
X
64/32
340000h to 34FFFFh 1A0000h to 1A7FFFh
SA58
1
1
0
0
1
1
X
X
X
X
64/32
330000h to 33FFFFh
198000h to 19FFFFh
SA57
1
1
0
0
1
0
X
X
X
X
64/32
320000h to 32FFFFh
190000h to 197FFFh
SA56
1
1
0
0
0
1
X
X
X
X
64/32
310000h to 31FFFFh
188000h to 18FFFFh
SA55
1
1
0
0
0
0
X
X
X
X
64/32
300000h to 30FFFFh
180000h to 187FFFh
SA54
1
0
1
1
1
1
X
X
X
X
64/32
2F0000h to 2FFFFFh 178000h to 17FFFFh
SA53
1
0
1
1
1
0
X
X
X
X
64/32
2E0000h to 2EFFFFh 170000h to 177FFFh
SA52
1
0
1
1
0
1
X
X
X
X
64/32
2D0000h to 2DFFFFh 168000h to 16FFFFh
SA51
1
0
1
1
0
0
X
X
X
X
64/32
2C0000h to 2CFFFFh 160000h to 167FFFh
SA50
1
0
1
0
1
1
X
X
X
X
64/32
2B0000h to 2BFFFFh 158000h to 15FFFFh
SA49
1
0
1
0
1
0
X
X
X
X
64/32
2A0000h to 2AFFFFh 150000h to 157FFFh
MBM29DL32XTE/BE
80
/90
19
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA48
1
0
1
0
0
1
X
X
X
X
64/32
290000h to 29FFFFh
148000h to 14FFFFh
SA47
1
0
1
0
0
0
X
X
X
X
64/32
280000h to 28FFFFh
140000h to 147FFFh
SA46
1
0
0
1
1
1
X
X
X
X
64/32
270000h to 27FFFFh
138000h to 13FFFFh
SA45
1
0
0
1
1
0
X
X
X
X
64/32
260000h to 26FFFFh
130000h to 137FFFh
SA44
1
0
0
1
0
1
X
X
X
X
64/32
250000h to 25FFFFh
128000h to 12FFFFh
SA43
1
0
0
1
0
0
X
X
X
X
64/32
240000h to 24FFFFh
120000h to 127FFFh
SA42
1
0
0
0
1
1
X
X
X
X
64/32
230000h to 23FFFFh
118000h to 11FFFFh
SA41
1
0
0
0
1
0
X
X
X
X
64/32
220000h to 22FFFFh
110000h to 117FFFh
SA40
1
0
0
0
0
1
X
X
X
X
64/32
210000h to 21FFFFh
108000h to 10FFFFh
SA39
1
0
0
0
0
0
X
X
X
X
64/32
200000h to 20FFFFh
100000h to 107FFFh
SA38
0
1
1
1
1
1
X
X
X
X
64/32
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA37
0
1
1
1
1
0
X
X
X
X
64/32
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA36
0
1
1
1
0
1
X
X
X
X
64/32
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA35
0
1
1
1
0
0
X
X
X
X
64/32
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA34
0
1
1
0
1
1
X
X
X
X
64/32
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA33
0
1
1
0
1
0
X
X
X
X
64/32
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA32
0
1
1
0
0
1
X
X
X
X
64/32
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA31
0
1
1
0
0
0
X
X
X
X
64/32
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA30
0
1
0
1
1
1
X
X
X
X
64/32
170000h to 17FFFFh 0B8000h to 0BFFFFh
SA29
0
1
0
1
1
0
X
X
X
X
64/32
160000h to 16FFFFh 0B0000h to 0B7FFFh
SA28
0
1
0
1
0
1
X
X
X
X
64/32
150000h to 15FFFFh 0A8000h to 0AFFFFh
SA27
0
1
0
1
0
0
X
X
X
X
64/32
140000h to 14FFFFh 0A0000h to 0A7FFFh
SA26
0
1
0
0
1
1
X
X
X
X
64/32
130000h to 13FFFFh
098000h to 09FFFFh
SA25
0
1
0
0
1
0
X
X
X
X
64/32
120000h to 12FFFFh
090000h to 097FFFh
SA24
0
1
0
0
0
1
X
X
X
X
64/32
110000h to 11FFFFh
088000h to 08FFFFh
SA23
0
1
0
0
0
0
X
X
X
X
64/32
100000h to 10FFFFh
080000h to 087FFFh
SA22
0
0
1
1
1
1
X
X
X
X
64/32
0F0000h to 0FFFFFh 078000h to 07FFFFh
SA21
0
0
1
1
1
0
X
X
X
X
64/32
0E0000h to 0EFFFFh 070000h to 077FFFh
SA20
0
0
1
1
0
1
X
X
X
X
64/32
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA19
0
0
1
1
0
0
X
X
X
X
64/32
0C0000h to 0CFFFFh 060000h to 067FFFh
SA18
0
0
1
0
1
1
X
X
X
X
64/32
0B0000h to 0BFFFFh 058000h to 05FFFFh
SA17
0
0
1
0
1
0
X
X
X
X
64/32
0A0000h to 0AFFFFh 050000h to 057FFFh
SA16
0
0
1
0
0
1
X
X
X
X
64/32
090000h to 09FFFFh
048000h to 04FFFFh
SA15
0
0
1
0
0
0
X
X
X
X
64/32
080000h to 08FFFFh
040000h to 047FFFh
MBM29DL32XTE/BE
80
/90
20
(Continued)
Note : The address range is A
20
: A-
1
if in byte mode (BYTE
=
V
IL
) .
The address range is A
20
: A
0
if in word mode (BYTE
=
V
IH
) .
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
1
SA14
0
0
0
1
1
1
X
X
X
X
64/32
070000h to 07FFFFh
038000h to 03FFFFh
SA13
0
0
0
1
1
0
X
X
X
X
64/32
060000h to 06FFFFh
030000h to 037FFFh
SA12
0
0
0
1
0
1
X
X
X
X
64/32
050000h to 05FFFFh
028000h to 02FFFFh
SA11
0
0
0
1
0
0
X
X
X
X
64/32
040000h to 04FFFFh
020000h to 027FFFh
SA10
0
0
0
0
1
1
X
X
X
X
64/32
030000h to 03FFFFh
018000h to 01FFFFh
SA9
0
0
0
0
1
0
X
X
X
X
64/32
020000h to 02FFFFh
010000h to 017FFFh
SA8
0
0
0
0
0
1
X
X
X
X
64/32
010000h to 01FFFFh
008000h to 00FFFFh
SA7
0
0
0
0
0
0
1
1
1
X
8/4
00E000h to 00FFFFh
007000h to 007FFFh
SA6
0
0
0
0
0
0
1
1
0
X
8/4
00C000h to 00DFFFh 006000h to 006FFFh
SA5
0
0
0
0
0
0
1
0
1
X
8/4
00A000h to 00BFFFh 005000h to 005FFFh
SA4
0
0
0
0
0
0
1
0
0
X
8/4
008000h to 009FFFh
004000h to 004FFFh
SA3
0
0
0
0
0
0
0
1
1
X
8/4
006000h to 007FFFh
003000h to 003FFFh
SA2
0
0
0
0
0
0
0
1
0
X
8/4
004000h to 005FFFh
002000h to 002FFFh
SA1
0
0
0
0
0
0
0
0
1
X
8/4
002000h to 003FFFh
001000h to 001FFFh
SA0
0
0
0
0
0
0
0
0
0
X
8/4
000000h to 001FFFh
000000h to 000FFFh
MBM29DL32XTE/BE
80
/90
21
Sector Address Table (MBM29DL323TE)
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA0
0
0
0
0
0
0
X
X
X
X
64/32
000000h to 00FFFFh
000000h to 007FFFh
SA1
0
0
0
0
0
1
X
X
X
X
64/32
010000h to 01FFFFh
008000h to 00FFFFh
SA2
0
0
0
0
1
0
X
X
X
X
64/32
020000h to 02FFFFh
010000h to 017FFFh
SA3
0
0
0
0
1
1
X
X
X
X
64/32
030000h to 03FFFFh
018000h to 01FFFFh
SA4
0
0
0
1
0
0
X
X
X
X
64/32
040000h to 04FFFFh
020000h to 027FFFh
SA5
0
0
0
1
0
1
X
X
X
X
64/32
050000h to 05FFFFh
028000h to 02FFFFh
SA6
0
0
0
1
1
0
X
X
X
X
64/32
060000h to 06FFFFh
030000h to 037FFFh
SA7
0
0
0
1
1
1
X
X
X
X
64/32
070000h to 07FFFFh
038000h to 03FFFFh
SA8
0
0
1
0
0
0
X
X
X
X
64/32
080000h to 08FFFFh
040000h to 047FFFh
SA9
0
0
1
0
0
1
X
X
X
X
64/32
090000h to 09FFFFh
048000h to 04FFFFh
SA10
0
0
1
0
1
0
X
X
X
X
64/32
0A0000h to 0AFFFFh 050000h to 057FFFh
SA11
0
0
1
0
1
1
X
X
X
X
64/32
0B0000h to 0BFFFFh 058000h to 05FFFFh
SA12
0
0
1
1
0
0
X
X
X
X
64/32
0C0000h to 0CFFFFh 060000h to 067FFFh
SA13
0
0
1
1
0
1
X
X
X
X
64/32
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA14
0
0
1
1
1
0
X
X
X
X
64/32
0E0000h to 0EFFFFh 070000h to 077FFFh
SA15
0
0
1
1
1
1
X
X
X
X
64/32
0F0000h to 0FFFFFh 078000h to 07FFFFh
SA16
0
1
0
0
0
0
X
X
X
X
64/32
100000h to 10FFFFh
080000h to 087FFFh
SA17
0
1
0
0
0
1
X
X
X
X
64/32
110000h to 11FFFFh
088000h to 08FFFFh
SA18
0
1
0
0
1
0
X
X
X
X
64/32
120000h to 12FFFFh
090000h to 097FFFh
SA19
0
1
0
0
1
1
X
X
X
X
64/32
130000h to 13FFFFh
098000h to 09FFFFh
SA20
0
1
0
1
0
0
X
X
X
X
64/32
140000h to 14FFFFh 0A0000h to 0A7FFFh
SA21
0
1
0
1
0
1
X
X
X
X
64/32
150000h to 15FFFFh 0A8000h to 0AFFFFh
SA22
0
1
0
1
1
0
X
X
X
X
64/32
160000h to 16FFFFh 0B0000h to 0B7FFFh
SA23
0
1
0
1
1
1
X
X
X
X
64/32
170000h to 17FFFFh 0B8000h to 0BFFFFh
SA24
0
1
1
0
0
0
X
X
X
X
64/32
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA25
0
1
1
0
0
1
X
X
X
X
64/32
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26
0
1
1
0
1
0
X
X
X
X
64/32
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA27
0
1
1
0
1
1
X
X
X
X
64/32
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA28
0
1
1
1
0
0
X
X
X
X
64/32
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA29
0
1
1
1
0
1
X
X
X
X
64/32
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA30
0
1
1
1
1
0
X
X
X
X
64/32
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31
0
1
1
1
1
1
X
X
X
X
64/32
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA32
1
0
0
0
0
0
X
X
X
X
64/32
200000h to 20FFFFh
100000h to 107FFFh
MBM29DL32XTE/BE
80
/90
22
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA33
1
0
0
0
0
1
X
X
X
X
64/32
210000h to 21FFFFh
108000h to 10FFFFh
SA34
1
0
0
0
1
0
X
X
X
X
64/32
220000h to 22FFFFh
110000h to 117FFFh
SA35
1
0
0
0
1
1
X
X
X
X
64/32
230000h to 23FFFFh
118000h to 11FFFFh
SA36
1
0
0
1
0
0
X
X
X
X
64/32
240000h to 24FFFFh
120000h to 127FFFh
SA37
1
0
0
1
0
1
X
X
X
X
64/32
250000h to 25FFFFh
128000h to 12FFFFh
SA38
1
0
0
1
1
0
X
X
X
X
64/32
260000h to 26FFFFh
130000h to 137FFFh
SA39
1
0
0
1
1
1
X
X
X
X
64/32
270000h to 27FFFFh
138000h to 13FFFFh
SA40
1
0
1
0
0
0
X
X
X
X
64/32
280000h to 28FFFFh
140000h to 147FFFh
SA41
1
0
1
0
0
1
X
X
X
X
64/32
290000h to 29FFFFh
148000h to 14FFFFh
SA42
1
0
1
0
1
0
X
X
X
X
64/32
2A0000h to 2AFFFFh 150000h to 157FFFh
SA43
1
0
1
0
1
1
X
X
X
X
64/32
2B0000h to 2BFFFFh 158000h to 15FFFFh
SA44
1
0
1
1
0
0
X
X
X
X
64/32
2C0000h to 2CFFFFh 160000h to 167FFFh
SA45
1
0
1
1
0
1
X
X
X
X
64/32
2D0000h to 2DFFFFh 168000h to 16FFFFh
SA46
1
0
1
1
1
0
X
X
X
X
64/32
2E0000h to 2EFFFFh 170000h to 177FFFh
SA47
1
0
1
1
1
1
X
X
X
X
64/32
2F0000h to 2FFFFFh 178000h to 17FFFFh
Bank
1
SA48
1
1
0
0
0
0
X
X
X
X
64/32
300000h to 30FFFFh
180000h to 187FFFh
SA49
1
1
0
0
0
1
X
X
X
X
64/32
310000h to 31FFFFh
188000h to 18FFFFh
SA50
1
1
0
0
1
0
X
X
X
X
64/32
320000h to 32FFFFh
190000h to 197FFFh
SA51
1
1
0
0
1
1
X
X
X
X
64/32
330000h to 33FFFFh
198000h to 19FFFFh
SA52
1
1
0
1
0
0
X
X
X
X
64/32
340000h to 34FFFFh 1A0000h to 1A7FFFh
SA53
1
1
0
1
0
1
X
X
X
X
64/32
350000h to 35FFFFh 1A8000h to 1AFFFFh
SA54
1
1
0
1
1
0
X
X
X
X
64/32
360000h to 36FFFFh 1B0000h to 1B7FFFh
SA55
1
1
0
1
1
1
X
X
X
X
64/32
370000h to 37FFFFh 1B8000h to 1BFFFFh
SA56
1
1
1
0
0
0
X
X
X
X
64/32
380000h to 38FFFFh 1C0000h to 1C7FFFh
SA57
1
1
1
0
0
1
X
X
X
X
64/32
390000h to 39FFFFh 1C8000h to 1CFFFFh
SA58
1
1
1
0
1
0
X
X
X
X
64/32
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA59
1
1
1
0
1
1
X
X
X
X
64/32
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA60
1
1
1
1
0
0
X
X
X
X
64/32
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA61
1
1
1
1
0
1
X
X
X
X
64/32
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA62
1
1
1
1
1
0
X
X
X
X
64/32
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA63
1
1
1
1
1
1
0
0
0
X
8/4
3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
SA64
1
1
1
1
1
1
0
0
1
X
8/4
3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
SA65
1
1
1
1
1
1
0
1
0
X
8/4
3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
SA66
1
1
1
1
1
1
0
1
1
X
8/4
3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
MBM29DL32XTE/BE
80
/90
23
(Continued)
Note : The address range is A
20
: A-
1
if in byte mode (BYTE
=
V
IL
) .
The address range is A
20
: A
0
if in word mode (BYTE
=
V
IH
) .
Sector Address Table (MBM29DL323BE)
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
1
SA67
1
1
1
1
1
1
1
0
0
X
8/4
3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
SA68
1
1
1
1
1
1
1
0
1
X
8/4
3FA000h to 3FBFFFh 1FD000h to 1FDFFFh
SA69
1
1
1
1
1
1
1
1
0
X
8/4
3FC000h to 3FDFFFh 1FE000h to 1FEFFFh
SA70
1
1
1
1
1
1
1
1
1
X
8/4
3FE000h to 3FFFFFh 1FF000h to 1FFFFFh
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA70
1
1
1
1
1
1
X
X
X
X
64/32
3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
SA69
1
1
1
1
1
0
X
X
X
X
64/32
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA68
1
1
1
1
0
1
X
X
X
X
64/32
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA67
1
1
1
1
0
0
X
X
X
X
64/32
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA66
1
1
1
0
1
1
X
X
X
X
64/32
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA65
1
1
1
0
1
0
X
X
X
X
64/32
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA64
1
1
1
0
0
1
X
X
X
X
64/32
390000h to 39FFFFh 1C8000h to 1CFFFFh
SA63
1
1
1
0
0
0
X
X
X
X
64/32
380000h to 38FFFFh 1C0000h to 1C7FFFh
SA62
1
1
0
1
1
1
X
X
X
X
64/32
370000h to 37FFFFh 1B8000h to 1BFFFFh
SA61
1
1
0
1
1
0
X
X
X
X
64/32
360000h to 36FFFFh 1B0000h to 1B7FFFh
SA60
1
1
0
1
0
1
X
X
X
X
64/32
350000h to 35FFFFh 1A8000h to 1AFFFFh
SA59
1
1
0
1
0
0
X
X
X
X
64/32
340000h to 34FFFFh 1A0000h to 1A7FFFh
SA58
1
1
0
0
1
1
X
X
X
X
64/32
330000h to 33FFFFh
198000h to 19FFFFh
SA57
1
1
0
0
1
0
X
X
X
X
64/32
320000h to 32FFFFh
190000h to 197FFFh
SA56
1
1
0
0
0
1
X
X
X
X
64/32
310000h to 31FFFFh
188000h to 18FFFFh
SA55
1
1
0
0
0
0
X
X
X
X
64/32
300000h to 30FFFFh
180000h to 187FFFh
SA54
1
0
1
1
1
1
X
X
X
X
64/32
2F0000h to 2FFFFFh 178000h to 17FFFFh
SA53
1
0
1
1
1
0
X
X
X
X
64/32
2E0000h to 2EFFFFh 170000h to 177FFFh
SA52
1
0
1
1
0
1
X
X
X
X
64/32
2D0000h to 2DFFFFh 168000h to 16FFFFh
SA51
1
0
1
1
0
0
X
X
X
X
64/32
2C0000h to 2CFFFFh 160000h to 167FFFh
SA50
1
0
1
0
1
1
X
X
X
X
64/32
2B0000h to 2BFFFFh 158000h to 15FFFFh
SA49
1
0
1
0
1
0
X
X
X
X
64/32
2A0000h to 2AFFFFh 150000h to 157FFFh
MBM29DL32XTE/BE
80
/90
24
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA48
1
0
1
0
0
1
X
X
X
X
64/32
290000h to 29FFFFh
148000h to 14FFFFh
SA47
1
0
1
0
0
0
X
X
X
X
64/32
280000h to 28FFFFh
140000h to 147FFFh
SA46
1
0
0
1
1
1
X
X
X
X
64/32
270000h to 27FFFFh
138000h to 13FFFFh
SA45
1
0
0
1
1
0
X
X
X
X
64/32
260000h to 26FFFFh
130000h to 137FFFh
SA44
1
0
0
1
0
1
X
X
X
X
64/32
250000h to 25FFFFh
128000h to 12FFFFh
SA43
1
0
0
1
0
0
X
X
X
X
64/32
240000h to 24FFFFh
120000h to 127FFFh
SA42
1
0
0
0
1
1
X
X
X
X
64/32
230000h to 23FFFFh
118000h to 11FFFFh
SA41
1
0
0
0
1
0
X
X
X
X
64/32
220000h to 22FFFFh
110000h to 117FFFh
SA40
1
0
0
0
0
1
X
X
X
X
64/32
210000h to 21FFFFh
108000h to 10FFFFh
SA39
1
0
0
0
0
0
X
X
X
X
64/32
200000h to 20FFFFh
100000h to 107FFFh
SA38
0
1
1
1
1
1
X
X
X
X
64/32
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA37
0
1
1
1
1
0
X
X
X
X
64/32
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA36
0
1
1
1
0
1
X
X
X
X
64/32
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA35
0
1
1
1
0
0
X
X
X
X
64/32
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA34
0
1
1
0
1
1
X
X
X
X
64/32
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA33
0
1
1
0
1
0
X
X
X
X
64/32
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA32
0
1
1
0
0
1
X
X
X
X
64/32
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA31
0
1
1
0
0
0
X
X
X
X
64/32
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA30
0
1
0
1
1
1
X
X
X
X
64/32
170000h to 17FFFFh 0B8000h to 0BFFFFh
SA29
0
1
0
1
1
0
X
X
X
X
64/32
160000h to 16FFFFh 0B0000h to 0B7FFFh
SA28
0
1
0
1
0
1
X
X
X
X
64/32
150000h to 15FFFFh 0A8000h to 0AFFFFh
SA27
0
1
0
1
0
0
X
X
X
X
64/32
140000h to 14FFFFh 0A0000h to 0A7FFFh
SA26
0
1
0
0
1
1
X
X
X
X
64/32
130000h to 13FFFFh
098000h to 09FFFFh
SA25
0
1
0
0
1
0
X
X
X
X
64/32
120000h to 12FFFFh
090000h to 097FFFh
SA24
0
1
0
0
0
1
X
X
X
X
64/32
110000h to 11FFFFh
088000h to 08FFFFh
SA23
0
1
0
0
0
0
X
X
X
X
64/32
100000h to 10FFFFh
080000h to 087FFFh
Bank
1
SA22
0
0
1
1
1
1
X
X
X
X
64/32
0F0000h to 0FFFFFh 078000h to 07FFFFh
SA21
0
0
1
1
1
0
X
X
X
X
64/32
0E0000h to 0EFFFFh 070000h to 077FFFh
SA20
0
0
1
1
0
1
X
X
X
X
64/32
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA19
0
0
1
1
0
0
X
X
X
X
64/32
0C0000h to 0CFFFFh 060000h to 067FFFh
SA18
0
0
1
0
1
1
X
X
X
X
64/32
0B0000h to 0BFFFFh 058000h to 05FFFFh
SA17
0
0
1
0
1
0
X
X
X
X
64/32
0A0000h to 0AFFFFh 050000h to 057FFFh
SA16
0
0
1
0
0
1
X
X
X
X
64/32
090000h to 09FFFFh
048000h to 04FFFFh
SA15
0
0
1
0
0
0
X
X
X
X
64/32
080000h to 08FFFFh
040000h to 047FFFh
MBM29DL32XTE/BE
80
/90
25
(Continued)
Note : The address range is A
20
: A-
1
if in byte mode (BYTE
=
V
IL
) .
The address range is A
20
: A
0
if in word mode (BYTE
=
V
IH
) .
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
1
SA14
0
0
0
1
1
1
X
X
X
X
64/32
070000h to 07FFFFh
038000h to 03FFFFh
SA13
0
0
0
1
1
0
X
X
X
X
64/32
060000h to 06FFFFh
030000h to 037FFFh
SA12
0
0
0
1
0
1
X
X
X
X
64/32
050000h to 05FFFFh
028000h to 02FFFFh
SA11
0
0
0
1
0
0
X
X
X
X
64/32
040000h to 04FFFFh
020000h to 027FFFh
SA10
0
0
0
0
1
1
X
X
X
X
64/32
030000h to 03FFFFh
018000h to 01FFFFh
SA9
0
0
0
0
1
0
X
X
X
X
64/32
020000h to 02FFFFh
010000h to 017FFFh
SA8
0
0
0
0
0
1
X
X
X
X
64/32
010000h to 01FFFFh
008000h to 00FFFFh
SA7
0
0
0
0
0
0
1
1
1
X
8/4
00E000h to 00FFFFh
007000h to 007FFFh
SA6
0
0
0
0
0
0
1
1
0
X
8/4
00C000h to 00DFFFh 006000h to 006FFFh
SA5
0
0
0
0
0
0
1
0
1
X
8/4
00A000h to 00BFFFh 005000h to 005FFFh
SA4
0
0
0
0
0
0
1
0
0
X
8/4
008000h to 009FFFh
004000h to 004FFFh
SA3
0
0
0
0
0
0
0
1
1
X
8/4
006000h to 007FFFh
003000h to 003FFFh
SA2
0
0
0
0
0
0
0
1
0
X
8/4
004000h to 005FFFh
002000h to 002FFFh
SA1
0
0
0
0
0
0
0
0
1
X
8/4
002000h to 003FFFh
001000h to 001FFFh
SA0
0
0
0
0
0
0
0
0
0
X
8/4
000000h to 001FFFh
000000h to 000FFFh
MBM29DL32XTE/BE
80
/90
26
Sector Address Table (MBM29DL324TE)
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA0
0
0
0
0
0
0
X
X
X
X
64/32
000000h to 00FFFFh
000000h to 007FFFh
SA1
0
0
0
0
0
1
X
X
X
X
64/32
010000h to 01FFFFh
008000h to 00FFFFh
SA2
0
0
0
0
1
0
X
X
X
X
64/32
020000h to 02FFFFh
010000h to 017FFFh
SA3
0
0
0
0
1
1
X
X
X
X
64/32
030000h to 03FFFFh
018000h to 01FFFFh
SA4
0
0
0
1
0
0
X
X
X
X
64/32
040000h to 04FFFFh
020000h to 027FFFh
SA5
0
0
0
1
0
1
X
X
X
X
64/32
050000h to 05FFFFh
028000h to 02FFFFh
SA6
0
0
0
1
1
0
X
X
X
X
64/32
060000h to 06FFFFh
030000h to 037FFFh
SA7
0
0
0
1
1
1
X
X
X
X
64/32
070000h to 07FFFFh
038000h to 03FFFFh
SA8
0
0
1
0
0
0
X
X
X
X
64/32
080000h to 08FFFFh
040000h to 047FFFh
SA9
0
0
1
0
0
1
X
X
X
X
64/32
090000h to 09FFFFh
048000h to 04FFFFh
SA10
0
0
1
0
1
0
X
X
X
X
64/32
0A0000h to 0AFFFFh 050000h to 057FFFh
SA11
0
0
1
0
1
1
X
X
X
X
64/32
0B0000h to 0BFFFFh 058000h to 05FFFFh
SA12
0
0
1
1
0
0
X
X
X
X
64/32
0C0000h to 0CFFFFh 060000h to 067FFFh
SA13
0
0
1
1
0
1
X
X
X
X
64/32
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA14
0
0
1
1
1
0
X
X
X
X
64/32
0E0000h to 0EFFFFh 070000h to 077FFFh
SA15
0
0
1
1
1
1
X
X
X
X
64/32
0F0000h to 0FFFFFh 078000h to 07FFFFh
SA16
0
1
0
0
0
0
X
X
X
X
64/32
100000h to 10FFFFh
080000h to 087FFFh
SA17
0
1
0
0
0
1
X
X
X
X
64/32
110000h to 11FFFFh
088000h to 08FFFFh
SA18
0
1
0
0
1
0
X
X
X
X
64/32
120000h to 12FFFFh
090000h to 097FFFh
SA19
0
1
0
0
1
1
X
X
X
X
64/32
130000h to 13FFFFh
098000h to 09FFFFh
SA20
0
1
0
1
0
0
X
X
X
X
64/32
140000h to 14FFFFh 0A0000h to 0A7FFFh
SA21
0
1
0
1
0
1
X
X
X
X
64/32
150000h to 15FFFFh 0A8000h to 0AFFFFh
SA22
0
1
0
1
1
0
X
X
X
X
64/32
160000h to 16FFFFh 0B0000h to 0B7FFFh
SA23
0
1
0
1
1
1
X
X
X
X
64/32
170000h to 17FFFFh 0B8000h to 0BFFFFh
SA24
0
1
1
0
0
0
X
X
X
X
64/32
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA25
0
1
1
0
0
1
X
X
X
X
64/32
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA26
0
1
1
0
1
0
X
X
X
X
64/32
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA27
0
1
1
0
1
1
X
X
X
X
64/32
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA28
0
1
1
1
0
0
X
X
X
X
64/32
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA29
0
1
1
1
0
1
X
X
X
X
64/32
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA30
0
1
1
1
1
0
X
X
X
X
64/32
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31
0
1
1
1
1
1
X
X
X
X
64/32
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
MBM29DL32XTE/BE
80
/90
27
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
1
SA32
1
0
0
0
0
0
X
X
X
X
64/32
200000h to 20FFFFh
100000h to 107FFFh
SA33
1
0
0
0
0
1
X
X
X
X
64/32
210000h to 21FFFFh
108000h to 10FFFFh
SA34
1
0
0
0
1
0
X
X
X
X
64/32
220000h to 22FFFFh
110000h to 117FFFh
SA35
1
0
0
0
1
1
X
X
X
X
64/32
230000h to 23FFFFh
118000h to 11FFFFh
SA36
1
0
0
1
0
0
X
X
X
X
64/32
240000h to 24FFFFh
120000h to 127FFFh
SA37
1
0
0
1
0
1
X
X
X
X
64/32
250000h to 25FFFFh
128000h to 12FFFFh
SA38
1
0
0
1
1
0
X
X
X
X
64/32
260000h to 26FFFFh
130000h to 137FFFh
SA39
1
0
0
1
1
1
X
X
X
X
64/32
270000h to 27FFFFh
138000h to 13FFFFh
SA40
1
0
1
0
0
0
X
X
X
X
64/32
280000h to 28FFFFh
140000h to 147FFFh
SA41
1
0
1
0
0
1
X
X
X
X
64/32
290000h to 29FFFFh
148000h to 14FFFFh
SA42
1
0
1
0
1
0
X
X
X
X
64/32
2A0000h to 2AFFFFh 150000h to 157FFFh
SA43
1
0
1
0
1
1
X
X
X
X
64/32
2B0000h to 2BFFFFh 158000h to 15FFFFh
SA44
1
0
1
1
0
0
X
X
X
X
64/32
2C0000h to 2CFFFFh 160000h to 167FFFh
SA45
1
0
1
1
0
1
X
X
X
X
64/32
2D0000h to 2DFFFFh 168000h to 16FFFFh
SA46
1
0
1
1
1
0
X
X
X
X
64/32
2E0000h to 2EFFFFh 170000h to 177FFFh
SA47
1
0
1
1
1
1
X
X
X
X
64/32
2F0000h to 2FFFFFh 178000h to 17FFFFh
SA48
1
1
0
0
0
0
X
X
X
X
64/32
300000h to 30FFFFh
180000h to 187FFFh
SA49
1
1
0
0
0
1
X
X
X
X
64/32
310000h to 31FFFFh
188000h to 18FFFFh
SA50
1
1
0
0
1
0
X
X
X
X
64/32
320000h to 32FFFFh
190000h to 197FFFh
SA51
1
1
0
0
1
1
X
X
X
X
64/32
330000h to 33FFFFh
198000h to 19FFFFh
SA52
1
1
0
1
0
0
X
X
X
X
64/32
340000h to 34FFFFh 1A0000h to 1A7FFFh
SA53
1
1
0
1
0
1
X
X
X
X
64/32
350000h to 35FFFFh 1A8000h to 1AFFFFh
SA54
1
1
0
1
1
0
X
X
X
X
64/32
360000h to 36FFFFh 1B0000h to 1B7FFFh
SA55
1
1
0
1
1
1
X
X
X
X
64/32
370000h to 37FFFFh 1B8000h to 1BFFFFh
SA56
1
1
1
0
0
0
X
X
X
X
64/32
380000h to 38FFFFh 1C0000h to 1C7FFFh
SA57
1
1
1
0
0
1
X
X
X
X
64/32
390000h to 39FFFFh 1C8000h to 1CFFFFh
SA58
1
1
1
0
1
0
X
X
X
X
64/32
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA59
1
1
1
0
1
1
X
X
X
X
64/32
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA60
1
1
1
1
0
0
X
X
X
X
64/32
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA61
1
1
1
1
0
1
X
X
X
X
64/32
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA62
1
1
1
1
1
0
X
X
X
X
64/32
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA63
1
1
1
1
1
1
0
0
0
X
8/4
3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
SA64
1
1
1
1
1
1
0
0
1
X
8/4
3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
SA65
1
1
1
1
1
1
0
1
0
X
8/4
3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
MBM29DL32XTE/BE
80
/90
28
(Continued)
Note : The address range is A
20
: A-
1
if in byte mode (BYTE
=
V
IL
) .
The address range is A
20
: A
0
if in word mode (BYTE
=
V
IH
) .
Sector Address Table (MBM29DL324BE)
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
1
SA66
1
1
1
1
1
1
0
1
1
X
8/4
3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
SA67
1
1
1
1
1
1
1
0
0
X
8/4
3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
SA68
1
1
1
1
1
1
1
0
1
X
8/4
3FA000h to 3FBFFFh 1FD000h to 1FDFFFh
SA69
1
1
1
1
1
1
1
1
0
X
8/4
3FC000h to 3FDFFFh 1FE000h to 1FEFFFh
SA70
1
1
1
1
1
1
1
1
1
X
8/4
3FE000h to 3FFFFFh 1FF000h to 1FFFFFh
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA70
1
1
1
1
1
1
X
X
X
X
64/32
3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
SA69
1
1
1
1
1
0
X
X
X
X
64/32
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA68
1
1
1
1
0
1
X
X
X
X
64/32
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA67
1
1
1
1
0
0
X
X
X
X
64/32
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA66
1
1
1
0
1
1
X
X
X
X
64/32
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA65
1
1
1
0
1
0
X
X
X
X
64/32
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA64
1
1
1
0
0
1
X
X
X
X
64/32
390000h to 39FFFFh 1C8000h to 1CFFFFh
SA63
1
1
1
0
0
0
X
X
X
X
64/32
380000h to 38FFFFh 1C0000h to 1C7FFFh
SA62
1
1
0
1
1
1
X
X
X
X
64/32
370000h to 37FFFFh 1B8000h to 1BFFFFh
SA61
1
1
0
1
1
0
X
X
X
X
64/32
360000h to 36FFFFh 1B0000h to 1B7FFFh
SA60
1
1
0
1
0
1
X
X
X
X
64/32
350000h to 35FFFFh 1A8000h to 1AFFFFh
SA59
1
1
0
1
0
0
X
X
X
X
64/32
340000h to 34FFFFh 1A0000h to 1A7FFFh
SA58
1
1
0
0
1
1
X
X
X
X
64/32
330000h to 33FFFFh
198000h to 19FFFFh
SA57
1
1
0
0
1
0
X
X
X
X
64/32
320000h to 32FFFFh
190000h to 197FFFh
SA56
1
1
0
0
0
1
X
X
X
X
64/32
310000h to 31FFFFh
188000h to 18FFFFh
SA55
1
1
0
0
0
0
X
X
X
X
64/32
300000h to 30FFFFh
180000h to 187FFFh
SA54
1
0
1
1
1
1
X
X
X
X
64/32
2F0000h to 2FFFFFh 178000h to 17FFFFh
SA53
1
0
1
1
1
0
X
X
X
X
64/32
2E0000h to 2EFFFFh 170000h to 177FFFh
SA52
1
0
1
1
0
1
X
X
X
X
64/32
2D0000h to 2DFFFFh 168000h to 16FFFFh
SA51
1
0
1
1
0
0
X
X
X
X
64/32
2C0000h to 2CFFFFh 160000h to 167FFFh
SA50
1
0
1
0
1
1
X
X
X
X
64/32
2B0000h to 2BFFFFh 158000h to 15FFFFh
MBM29DL32XTE/BE
80
/90
29
(Continued)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
2
SA49
1
0
1
0
1
0
X
X
X
X
64/32
2A0000h to 2AFFFFh 150000h to 157FFFh
SA48
1
0
1
0
0
1
X
X
X
X
64/32
290000h to 29FFFFh
148000h to 14FFFFh
SA47
1
0
1
0
0
0
X
X
X
X
64/32
280000h to 28FFFFh
140000h to 147FFFh
SA46
1
0
0
1
1
1
X
X
X
X
64/32
270000h to 27FFFFh
138000h to 13FFFFh
SA45
1
0
0
1
1
0
X
X
X
X
64/32
260000h to 26FFFFh
130000h to 137FFFh
SA44
1
0
0
1
0
1
X
X
X
X
64/32
250000h to 25FFFFh
128000h to 12FFFFh
SA43
1
0
0
1
0
0
X
X
X
X
64/32
240000h to 24FFFFh
120000h to 127FFFh
SA42
1
0
0
0
1
1
X
X
X
X
64/32
230000h to 23FFFFh
118000h to 11FFFFh
SA41
1
0
0
0
1
0
X
X
X
X
64/32
220000h to 22FFFFh
110000h to 117FFFh
SA40
1
0
0
0
0
1
X
X
X
X
64/32
210000h to 21FFFFh
108000h to 10FFFFh
SA39
1
0
0
0
0
0
X
X
X
X
64/32
200000h to 20FFFFh
100000h to 107FFFh
Bank
1
SA38
0
1
1
1
1
1
X
X
X
X
64/32
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA37
0
1
1
1
1
0
X
X
X
X
64/32
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA36
0
1
1
1
0
1
X
X
X
X
64/32
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA35
0
1
1
1
0
0
X
X
X
X
64/32
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA34
0
1
1
0
1
1
X
X
X
X
64/32
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA33
0
1
1
0
1
0
X
X
X
X
64/32
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA32
0
1
1
0
0
1
X
X
X
X
64/32
190000h to 19FFFFh 0C8000h to 0CFFFFh
SA31
0
1
1
0
0
0
X
X
X
X
64/32
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA30
0
1
0
1
1
1
X
X
X
X
64/32
170000h to 17FFFFh 0B8000h to 0BFFFFh
SA29
0
1
0
1
1
0
X
X
X
X
64/32
160000h to 16FFFFh 0B0000h to 0B7FFFh
SA28
0
1
0
1
0
1
X
X
X
X
64/32
150000h to 15FFFFh 0A8000h to 0AFFFFh
SA27
0
1
0
1
0
0
X
X
X
X
64/32
140000h to 14FFFFh 0A0000h to 0A7FFFh
SA26
0
1
0
0
1
1
X
X
X
X
64/32
130000h to 13FFFFh
098000h to 09FFFFh
SA25
0
1
0
0
1
0
X
X
X
X
64/32
120000h to 12FFFFh
090000h to 097FFFh
SA24
0
1
0
0
0
1
X
X
X
X
64/32
110000h to 11FFFFh
088000h to 08FFFFh
SA23
0
1
0
0
0
0
X
X
X
X
64/32
100000h to 10FFFFh
080000h to 087FFFh
SA22
0
0
1
1
1
1
X
X
X
X
64/32
0F0000h to 0FFFFFh 078000h to 07FFFFh
SA21
0
0
1
1
1
0
X
X
X
X
64/32
0E0000h to 0EFFFFh 070000h to 077FFFh
SA20
0
0
1
1
0
1
X
X
X
X
64/32
0D0000h to 0DFFFFh 068000h to 06FFFFh
SA19
0
0
1
1
0
0
X
X
X
X
64/32
0C0000h to 0CFFFFh 060000h to 067FFFh
SA18
0
0
1
0
1
1
X
X
X
X
64/32
0B0000h to 0BFFFFh 058000h to 05FFFFh
SA17
0
0
1
0
1
0
X
X
X
X
64/32
0A0000h to 0AFFFFh 050000h to 057FFFh
SA16
0
0
1
0
0
1
X
X
X
X
64/32
090000h to 09FFFFh
048000h to 04FFFFh
MBM29DL32XTE/BE
80
/90
30
(Continued)
Note : The address range is A
20
: A-
1
if in byte mode (BYTE
=
V
IL
) .
The address range is A
20
: A
0
if in word mode (BYTE
=
V
IH
)
Bank
Sec-
tor
Sector address
Sector
size
(Kbytes/
Kwords)
(
8)
Address range
(
16)
Address range
Bank address
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
Bank
1
SA15
0
0
1
0
0
0
X
X
X
X
64/32
080000h to 08FFFFh
040000h to 047FFFh
SA14
0
0
0
1
1
1
X
X
X
X
64/32
070000h to 07FFFFh
038000h to 03FFFFh
SA13
0
0
0
1
1
0
X
X
X
X
64/32
060000h to 06FFFFh
030000h to 037FFFh
SA12
0
0
0
1
0
1
X
X
X
X
64/32
050000h to 05FFFFh
028000h to 02FFFFh
SA11
0
0
0
1
0
0
X
X
X
X
64/32
040000h to 04FFFFh
020000h to 027FFFh
SA10
0
0
0
0
1
1
X
X
X
X
64/32
030000h to 03FFFFh
018000h to 01FFFFh
SA9
0
0
0
0
1
0
X
X
X
X
64/32
020000h to 02FFFFh
010000h to 017FFFh
SA8
0
0
0
0
0
1
X
X
X
X
64/32
010000h to 01FFFFh
008000h to 00FFFFh
SA7
0
0
0
0
0
0
1
1
1
X
8/4
00E000h to 00FFFFh
007000h to 007FFFh
SA6
0
0
0
0
0
0
1
1
0
X
8/4
00C000h to 00DFFFh 006000h to 006FFFh
SA5
0
0
0
0
0
0
1
0
1
X
8/4
00A000h to 00BFFFh 005000h to 005FFFh
SA4
0
0
0
0
0
0
1
0
0
X
8/4
008000h to 009FFFh
004000h to 004FFFh
SA3
0
0
0
0
0
0
0
1
1
X
8/4
006000h to 007FFFh
003000h to 003FFFh
SA2
0
0
0
0
0
0
0
1
0
X
8/4
004000h to 005FFFh
002000h to 002FFFh
SA1
0
0
0
0
0
0
0
0
1
X
8/4
002000h to 003FFFh
001000h to 001FFFh
SA0
0
0
0
0
0
0
0
0
0
X
8/4
000000h to 001FFFh
000000h to 000FFFh
MBM29DL32XTE/BE
80
/90
31
Sector Group Addresses (MBM29DL32XTE)
(Top Boot Block)
Sector group
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Sectors
SGA0
0
0
0
0
0
0
X
X
X
SA0
SGA1
0
0
0
0
0
1
X
X
X
SA1 to SA3
1
0
1
1
SGA2
0
0
0
1
X
X
X
X
X
SA4 to SA7
SGA3
0
0
1
0
X
X
X
X
X
SA8 to SA11
SGA4
0
0
1
1
X
X
X
X
X
SA12 to SA15
SGA5
0
1
0
0
X
X
X
X
X
SA16 to SA19
SGA6
0
1
0
1
X
X
X
X
X
SA20 to SA23
SGA7
0
1
1
0
X
X
X
X
X
SA24 to SA27
SGA8
0
1
1
1
X
X
X
X
X
SA28 to SA31
SGA9
1
0
0
0
X
X
X
X
X
SA32 to SA35
SGA10
1
0
0
1
X
X
X
X
X
SA36 to SA39
SGA11
1
0
1
0
X
X
X
X
X
SA40 to SA43
SGA12
1
0
1
1
X
X
X
X
X
SA44 to SA47
SGA13
1
1
0
0
X
X
X
X
X
SA48 to SA51
SGA14
1
1
0
1
X
X
X
X
X
SA52 to SA55
SGA15
1
1
1
0
X
X
X
X
X
SA56 to SA59
SGA16
1
1
1
1
0
0
X
X
X
SA60 to SA62
0
1
1
0
SGA17
1
1
1
1
1
1
0
0
0
SA63
SGA18
1
1
1
1
1
1
0
0
1
SA64
SGA19
1
1
1
1
1
1
0
1
0
SA65
SGA20
1
1
1
1
1
1
0
1
1
SA66
SGA21
1
1
1
1
1
1
1
0
0
SA67
SGA22
1
1
1
1
1
1
1
0
1
SA68
SGA23
1
1
1
1
1
1
1
1
0
SA69
SGA24
1
1
1
1
1
1
1
1
1
SA70
MBM29DL32XTE/BE
80
/90
32
Sector Group Addresses (MBM29DL32XBE)
(Bottom Boot Block)
Sector group
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Sectors
SGA0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
1
1
1
SA7
SGA8
0
0
0
0
0
1
X
X
X
SA8 to SA10
1
0
1
1
SGA9
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA15
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA16
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA17
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA18
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA19
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA20
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA21
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA22
1
1
1
0
X
X
X
X
X
SA63 to SA66
SGA23
1
1
1
1
0
0
X
X
X
SA67 to SA69
0
1
1
0
SGA24
1
1
1
1
1
1
X
X
X
SA70
MBM29DL32XTE/BE
80
/90
33
Common Flash Memory Interface Code
(Continued)
Description
A
0
to A
6
DQ
0
to DQ
15
Query-unique ASCII string "QRY"
10h
11h
12h
0051h
0052h
0059h
Primary OEM Command Set
02h : AMD/FJ standard type
13h
14h
0002h
0000h
Address for Primary Extended Table
15h
16h
0040h
0000h
Alternate OEM Command Set (00h
=
not applicable)
17h
18h
0000h
0000h
Address for Alternate OEM Extended Table
19h
1Ah
0000h
0000h
V
CC
Min (write/erase)
DQ
7
to DQ
4
: 1 V, DQ
3
to DQ
0
: 100 mV
1Bh
0027h
V
CC
Max (write/erase)
DQ
7
to DQ
4
: 1 V, DQ
3
to DQ
0
: 100 mV
1Ch
0036h
V
PP
Min voltage
1Dh
0000h
V
PP
Max voltage
1Eh
0000h
Typical timeout per single byte/word write 2
N
s
1Fh
0004h
Typical timeout for Min size buffer write 2
N
s
20h
0000h
Typical timeout per individual sector erase 2
N
ms
21h
000Ah
Typical timeout for full chip erase 2
N
ms
22h
0000h
Max timeout for byte/word write 2
N
times typical
23h
0005h
Max timeout for buffer write 2
N
times typical
24h
0000h
Max timeout per individual sector erase 2
N
times typical
25h
0004h
Max timeout for full chip erase 2
N
times typical
26h
0000h
Device Size
=
2
N
byte
27h
0016h
Flash Device Interface description
02h :
8/
16
28h
29h
0002h
0000h
Max number of byte in
multi-byte write
=
2
N
2Ah
2Bh
0000h
0000h
Number of Erase Block Regions within device
2Ch
0002h
Erase Block Region 1 Information
bit 15 to bit 0 : y = number of sectors
bit 31 to bit 16 : z = size
(z
256 bytes)
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 2 Information
bit 15 to bit 0 : y = number of sectors
bit 31 to bit 16 : z = size
(z
256 bytes)
31h
32h
33h
34h
003Eh
0000h
0000h
0001h
MBM29DL32XTE/BE
80
/90
34
(Continued)
Description
A
0
to A
6
DQ
0
to DQ
15
Query-unique ASCII string "PRI"
40h
41h
42h
0050h
0052h
0049h
Major version number, ASCII
43h
0031h
Minor version number, ASCII
44h
0032h
Address Sensitive Unlock
00h
=
Required
45h
0000h
Erase Suspend
02h
=
To Read & Write
46h
0002h
Sector Protection
00h
=
Not Supported
X
=
Number of sectors in per group
47h
0001h
Sector Temporary Unprotection
01h
=
Supported
48h
0001h
Sector Protection Algorithm
49h
0004h
Number of Sector for Bank 2
00h
=
Not Supported
38h
=
MBM29DL322TE
30h
=
MBM29DL323TE
20h
=
MBM29DL324TE
38h
=
MBM29DL322BE
30h
=
MBM29DL323BE
20h
=
MBM29DL324BE
4Ah
00XXh
Burst Mode Type
00h
=
Not Supported
4Bh
0000h
Page Mode Type
00h
=
Not Supported
4Ch
0000h
V
ACC
(Acceleration) Supply Minimum
DQ
7
to DQ
4
: 1 V, DQ
3
to DQ
0
: 100 mV
4Dh
0085h
V
ACC
(Acceleration) Supply Maximum
DQ
7
to DQ
4
: 1 V, DQ
3
to DQ
0
: 100 mV
4Eh
0095h
Boot Type
02h
=
MBM29DL32XBE
03h
=
MBM29DL32XTE
4Fh
00XXh
Program Suspend
01h
=
Supported
50h
0001h
MBM29DL32XTE/BE
80
/90
35
s
FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL32XTE/BE have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation) , in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank
selection can be selected by bank address (A
20
to A
15
) with zero latency.
The MBM29DL322TE/BE have two banks which contain
Bank 1 (8 KB
eight sectors, 64 KB
seven sectors) and Bank 2 (64 KB
fifty-six sectors) .
The MBM29DL323TE/BE have two banks which contain
Bank 1 (8 KB
eight sectors, 64 KB
fifteen sectors) and Bank 2 (64 KB
forty-eight sectors) .
The MBM29DL324TE/BE have two banks which contain
Bank 1 (8 KB
eight sectors, 64 KB
thirty-one sectors) and Bank 2 (64 KB
thirty-two sectors) .
The simultaneous operation can not execute multi-function mode in the same bank. "Simultaneous Operation"
in "
s
FUNCTIONAL DESCRIPTION" shows combination to be possible for simultaneous operation. (Refer to
the "Bank-to-bank Read/Write Timing Diagram" in "
s
TIMING DIAGRAM".)
Simultaneous Operation
* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets
suspended so that it enables reading from or programming the remaining sectors.
Read Mode
The MBM29DL32XTE/BE have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the
addresses have been stable for at least t
ACC
-t
OE
time) . When reading out a data without changing addresses
after power-up, it is necessary to input hardware reset or to change CE pin from "H" or "L"
Standby Mode
There are two ways to implement the standby mode on the MBM29DL32XTE/BE devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
0.3 V.
Under this condition the current consumed is less than 5
A Max During Embedded Algorithm operation, V
CC
Case
Bank 1 status
Bank 2 status
1
Read Mode
Read Mode
2
Read Mode
Autoselect Mode
3
Read Mode
Program Mode
4
Read Mode
Erase Mode *
5
Autoselect Mode
Read Mode
6
Program Mode
Read Mode
7
Erase Mode *
Read Mode
MBM29DL32XTE/BE
80
/90
36
active current (I
CC2
) is required even CE
=
"H". The device can be read with standard access time (t
CE
) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
0.3 V (CE
=
"H" or "L") . Under this condition the current is consumed is less than 5
A Max Once the RESET pin is taken
high, the device requires t
RH
of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL32XTE/BE data. This mode can be used effectively with an application requested low power con-
sumption such as handy terminals.
To activate this mode, MBM29DL32XTE/BE automatically switch themselves to low power mode when
MBM29DL32XTE/BE addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1
A (CMOS Level) .
During simultaneous operation, V
CC
active current (I
CC2
) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL32XTE/BE read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (V
IH
) , output from the devices are disabled. This will cause the output
pins to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force V
ID
(11.5 V to 12.5 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are DON'T CARES except A
0
, A
1
, and A
6
(A-
1
) . (See "MBM29DL32XTE/BE User Bus Operations
(BYTE
=
V
IH
) " and "MBM29DL32XTE/BE User Bus Operations (BYTE
=
V
IL
) " in "
s
DEVICE BUS OPERATION".)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL32XTE/BE are erased or programmed in a system without access to high voltage on the A
9
pin. The
command sequence is illustrated in "MBM29DL32XTE/BE Command Definitions" in "
s
DEVICEBUS OPERA-
TION". (Refer to Autoselect Command section.)
Byte 0 (A
0
=
V
IL
) represents the manufacturer's code (Fujitsu
=
04h) and word 1 (A
0
=
V
IH
) represents the device
identifier code (MBM29DL322TE
=
55h and MBM29DL322BE
=
56h for
8 mode; MBM29DL322TE
=
2255h
and MBM29DL322BE
=
2256h for
16 mode) . (MBM29DL323TE
=
50h and MBM29DL323BE
=
53h for
8
mode; MBM29DL323TE
=
2250h and MBM29DL323BE
=
2253h for
16
mode) . (MBM29DL324TE
=
5Ch and MBM29DL324BE
=
5Fh for
8 mode; MBM29DL324TE
=
225Ch and
MBM29DL324BE
=
225Fh for
16 mode) . These two bytes/words are given in "MBM29DL322/323/324TE/BE
Sector Group Protection Verify Autoselect Codes Tables", "Extended Autoselect Code Tables" in "
s
DEVICE
BUS OPERATION". All identifiers for manufactures and device will exhibit odd parity with DQ
7
defined as the
parity bit. In order to read the proper device codes when executing the autoselect, A
1
must be V
IL
. (See
"MBM29DL322/323/324TE/BE Sector Group Protection Verify Autoselect Codes Tables", "Extended Autoselect
Code Tables" in "
s
DEVICE BUS OPERATION".)
MBM29DL32XTE/BE
80
/90
37
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched on the
falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The MBM29DL32XTE/BE feature hardware sector group protection. This feature will disable both program and
erase operations in any combination of twenty five sector groups of memory. (See "Sector Group
Addresses (MBM29DL32XTE) (Top Boot Block) " and "Sector Group Addresses (MBM29DL32XBE) (Bottom
Boot Block) " in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE") . The sector group protection feature is
enabled using programming equipment at the user's site. The device is shipped with all sector groups unpro-
tected.
To activate this mode, the programming equipment must force V
ID
on address pin A
9
and control pin OE, (suggest
V
ID
=
11.5 V) , CE
=
V
IL
and A
6
=
A
0
=
V
IL
, A
1
=
V
IH
. The sector group addresses (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
,
A
13
, and A
12
) should be set to the sector to be protected. "Sector Address Table (MBM29DL322TE) ", "Sector
Address Table (MBM29DL322BE) ", "Sector Address Table (MBM29DL323TE) ", "Sector Address Table
(MBM29DL323BE) ", "Sector Address Table (MBM29DL324TE) " and "Sector Address Table (MBM29DL324
BE) " in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE" define the sector address for each of the seventy
one (71) individual sectors, and "Sector Group Addresses (MBM29DL32XTE) (Top Boot Block) " and "Sector
Group Addresses (MBM29DL32XBE) (Bottom Boot Block) " in "
s
FLEXIBLE SECTOR-ERASE ARCHITEC-
TURE" define the sector group address for each of the twenty five (25) individual group sectors. Programming
of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of
the same. Sector group addresses must be held constant during the WE pulse. See "Sector Group Protection
Timing Diagram" in "
s
TIMING DIAGRAM" and "Sector Group Protection Algorithm" in "
s
FLOW CHART" for
sector group protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector group addresses (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
,
and A
12
) while (A
6
, A
1
, A
0
)
=
(0, 1, 0) will produce a logical "1" code at device output DQ
0
for a protected sector.
Otherwise the device will produce "0" for unprotected sector. In this mode, the lower order addresses, except
for A
0
, A
1
, and A
6
are DON'T CARES. Address locations with A
1
=
V
IL
are reserved for Autoselect manufacturer
and device codes. A-
1
requires to apply to V
IL
on byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses (A
20
, A
19
, A
18
, A
17
,
A
16
, A
15
, A
14
, A
13
, and A
12
) are the desired sector group address will produce a logical "1" at DQ
0
for a protected
sector group. See "MBM29DL322/323/324TE/BE Sector Group Protection Verify Autoselect Codes Tables",
"Extended Autoselect Code Tables" in "
s
DEVICE BUS OPERATION" for Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32XTE/BE
devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to
high voltage (V
ID
) . During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the V
ID
is taken away from the RESET pin, all the previously protected sector
groups will be protected again. Refer to "Temporary Sector Group Unprotection Timing Diagram" in "
s
TIMING
DIAGRAM" and "Temporary Sector Group Unprotection Algorithm" in "
s
FLOW CHART".
MBM29DL32XTE/BE
80
/90
38
RESET
Hardware Reset
The MBM29DL32XTE/BE devices may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least "t
RP
" in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode "t
READY
" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional "t
RH
" before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See "RESET, RY/BY Timing
Diagram" in "
s
TIMING DIAGRAM" for the timing diagram. Refer to Temporary Sector Group Unprotection for
additional functionality.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTE/BE devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
/A-
1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to "Timing Diagram for Word Mode Configuration", "Timing Diagram for Byte Mode Configuration" and "BYTE
Timing Diagram for Write Operations" in "
s
TIMING DIAGRAM" for the timing diagram.
Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using V
ID
.
This function is one of two provided by the WP/ACC pin.
If the system asserts V
IL
on the WP/ACC pin, the device disables program and erase functions in the two
"outermost" 8 Kbyte boot sectors (MBM29DL32XTE : SA69 and SA70, MBM29DL32XBE : SA0 and SA1)
independently of whether those sectors were protected or unprotected using the method described in "Sector
Group Protection". The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses
in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured
device.
If the system asserts V
IH
on the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unprotected. That is, sector group protection or unprotection for these
two sectors depends on whether they were last protected or unprotected using the method described in "Sector
Group Protection".
Accelerated Program Operation
MBM29DL32XTE/BE offers accelerated program operation which enables the programming in high speed.
If the system asserts V
ACC
to the WP/ACC pin, the device automatically enters the acceleration mode and the
time required for program operation will reduce to about 60
%
. This function is primarily intended to allow high
speed program, so caution is needed as the sector group will temporarily be unprotected.
The system would use a fact program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used
for programming and detection of completion during acceleration mode.
Removing V
ACC
from the WP/ACC pin returns the device to normal operation. Do not remove V
ACC
from
WP/ACC pin while programming. See "Accelerated Program Timing Diagram" in "
s
TIMING DIAGRAM".
Erase operation during Accelerated Program Operation is strictly prohibited.
MBM29DL32XTE/BE
80
/90
39
s
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Some
commands are required Bank Address (BA) input. When command sequences are inputted to bank being read,
the commands have priority than reading. "MBM29DL32XTE/BE Command Definitions" in "
s
DEVICEBUS
OPERATION" defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase
Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program
Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress.
Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please
note that commands are always written at DQ
0
to DQ
7
and DQ
8
to DQ
15
bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
5
=
1) to Read/Reset mode, the
Read/Reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-
grammers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high voltage
onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and an actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA) 00h retrieves the manufacture code of 04h. A
read cycle from address (BA) 01h for
16 ( (BA) 02h for
8) returns the device code (MBM29DL322TE
=
55h
and MBM29DL322BE
=
56h for
8 mode; MBM29DL322TE
=
2255h and MBM29DL322BE
=
2256h for
16
mode) . (MBM29DL323TE
=
50h and MBM29DL323BE
=
53h for
8 mode; MBM29DL323TE
=
2250h and
MBM29DL323BE
=
2253h for
16 mode) . (MBM29DL324TE
=
5Ch and MBM29DL324BE
=
5Fh for
8 mode;
MBM29DL324TE
=
225Ch and MBM29DL324BE
=
225Fh for
16
mode) . (See "MBM29DL322/323/324TE/BE Sector Group Protection Verify Autoselect Codes Tables", "Ex-
tended Autoselect Code Tables" in "
s
DEVICE BUS OPERATION".)
All manufacturer and device codes will exhibit odd parity with DQ
7
defined as the parity bit. Sector state (protection
or unprotection) will be informed by address (BA) 02h for
16 ( (BA) 04h for
8) . Scanning the sector group
addresses (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
) while (A
6
, A
1
, A
0
)
=
(0, 1, 0) will produce a logical "1" at
device output DQ
0
for a protected sector group. The programming verification should be performed by verify
sector group protection on the protected sector. (See "Sector Address Table (MBM29DL324TE) ", "Sector
Address Table (MBM29DL324BE) ", "Sector Group Addresses (MBM29DL32XTE) (Top Boot Block) " and
"Sector Group Addresses (MBM29DL32XBE) (Bottom Boot Block) " in "
s
FLEXIBLE SECTOR-ERASE AR-
CHITECTURE".)
The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and
device codes and sector group protection status from non-selected bank, it is necessary to write Read/Reset
command sequence into the register and then Autoselect command should be written into the bank to be read.
MBM29DL32XTE/BE
80
/90
40
If the software (program code) for Autoselect command is stored into the Flash memory, the device and manu-
facture codes should be read from the other bank where is not contain the software.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command se-
quence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two "unlock" write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ
7
(Data Polling) , DQ
6
(Toggle Bit) ,
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See "Hardware
Sequence Flags" in "
s
COMMAND DEFINITIONS", Hardware Sequence Flags.) Therefore, the devices require
that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data
Polling must be performed at the memory location which is being programmed.
If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being
written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only
erase operations can convert "0"s to "1"s.
"Embedded Program
TM
Algorithm" in "
s
FLOW CHART" illustrates the Embedded Program
TM
Algorithm using
typical command strings and bus operations.
Program Suspend/Resume
The Profram Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation
immediately suspends the programming. The Program Suspend command may also be issued during a pro-
gramming operation while an erase is suspended. The bank addresses of sector being programmed should be
set when writing the Program Suspend command.
When the Program Suspend command is written during a process, the device halts the program operation within
1
s and updates the state bits.
After the program operation has been suspended, the system can read data from any address. The data at
program-suspended address is not valid. Normal read timing and command definitions apply.
After Program Resume command (30h) is written, the device reverts to programming. The bank address of
sectors being suspended should be set when writing the Program Resume command. The system can determine
the program operation status using the DQ
7
or DQ
6
status bits, just as in the standard program operation. See
"Write Operation Status" for more information.
The system may also write Autoselect command sequence when the device in the Program Suspend mode.
The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are
not stored in the memory. When the device exits form the Autoselect mode, the device reverts to the Program
MBM29DL32XTE/BE
80
/90
41
Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more infor-
mation.
The system must write the Program Resume command (address bits are "Bank Address") to exit from the
Program Suspend mode and continue programming operation. Further writes of the Resume command are
ignored. Another Program Suspend command can be written after the device resumes programming.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling) , DQ
6
(Toggle Bit) , or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ
7
is "1" (See Write Operation Status section.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time
All sectors
+
Chip Program Time (Preprogramming)
"Embedded Erase
TM
Algorithm" in "
s
FLOW CHART" illustrates the Embedded Erase
TM
Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data
=
30h) is latched on the rising edge of CE or WE which happens first.
After time-out of "t
TOW
" from the rising edge of the last sector erase command, the sector erase operation will
begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on "MBM29DL32XTE/BE
Command Definitions" in "
s
DEVICEBUS OPERATION". This sequence is followed with writes of the Sector
Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must
be less than "t
TOW
" otherwise that command will not be accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
after the last Sector Erase command is written. A time-out of "t
TOW
" from the rising edge of last CE or WE whichever
happens first will initiate the execution of the Sector Erase command (s) . If another falling edge of CE or WE,
whichever happens first occurs within the "t
TOW
" time-out window the timer is reset. (Monitor DQ
3
to determine
if the sector erase timer window is still open, see section DQ
3
, Sector Erase Timer.) Resetting the devices once
execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow
them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the
sector erase buffer may be done in any sequence and with any number of sectors (0 to 38) .
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling) , DQ
6
(Toggle Bit) , or
RY/BY.
The sector erase begins after the "t
TOW
" time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ
7
is "1" (See Write Operation Status
MBM29DL32XTE/BE
80
/90
42
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time
+
Sector Program Time (Preprogramming) ]
Number of Sector
Erase
In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform.
"Embedded Erase
TM
Algorithm" in "
s
FLOW CHART" illustrates the Embedded Erase
TM
Algorithm using typical
command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation.
Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being
erasing or suspending should be set when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of "t
SPD
" to suspend the erase operation. When the devices have entered the erase-suspended mode, the
RY/BY output pin will be at high impedence state and the DQ
7
bit will be at logic "1", and DQ
6
will stop toggling.
The user must use the address of the erasing sector for reading DQ
6
and DQ
7
to determine if the erase operation
has been suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ
2
to toggle. (See the section on DQ
2
.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-
mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, pro-
gramming in this mode is the same as programming in the regular Program mode except that the data must be
programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ
2
to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ
7
or by the Toggle Bit I
(DQ
6
) which is the same as the regular Program operation. Note that DQ
7
must be read from the Program address
while DQ
6
can be read from any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
Extended Command
(1) Fast Mode
MBM29DL32XTE/BE has Fast Mode function. This mode dispenses with the initial two unclock cycles required
in the standard program command sequence by writing Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first
cycle must contain the bank address. (Refer to the "Extended Sector Group Protection Algorithm" in "
s
FLOW
CHART".) The V
CC
active current is required even CE
=
V
IH
during Fast Mode.
MBM29DL32XTE/BE
80
/90
43
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to the
"Extended Sector Group Protection Algorithm" in "
s
FLOW CHART".)
(3) Extended Sector Group Protection
In addition to normal sector group protection, the MBM29DL32XTE/BE has Extended Sector Group Protection
as extended function. This function enable to protect sector group by forcing V
ID
on RESET pin and write a
command sequence. Unlike conventional procedure, it is not necessary to force V
ID
and control timing for control
pins. The only RESET pin requires V
ID
for sector group protection in this mode. The extended sector group
protection requires V
ID
on RESET pin. With this condition, the operation is initiated by writing the set-up command
(60h) into the command register. Then, the sector group addresses pins (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and
A
12
) and (A
6
, A
1
, A
0
)
=
(0, 1, 0) should be set to the sector group to be protected (recommend to set V
IL
for the
other addresses pins) , and write extended sector group protection command (60h) . A sector group is typically
protected in 250
s. To verify programming of the protection circuitry, the sector group addresses pins (A
20
, A
19
,
A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and A
12
) and (A
6
, A
1
, A
0
)
=
(0, 1, 0) should be set and write a command (40h) . Following
the command write, a logical "1" at device output DQ
0
will produce for protected sector in the read operation. If
the output data is logical "0", please repeat to write extended sector group protection command (60h) again. To
terminate the operation, it is necessary to set RESET pin to V
IH
. (Refer to the "Extended Sector Group Protection
Timing Diagram" in "
s
TIMING DIAGRAM" and "Extended Sector Group Protection Algorithm" in "
s
FLOW
CHART".)
(4) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation
handshake which allows specific vendor-specified software algorithms to be used for entire families of devices.
This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software sup-
port for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98h) into the command register. The bank address
should be set when writing this command. Then the device information can be read from the bank, and an actual
data of memory cell be read from the another bank. Following the command write, a read cycle from specific
address retrieves device information. Please note that output data of upper byte (DQ
15
to DQ
8
) is "0" in word
mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset
command sequence into the register. (See "Common Flash Memory Interface Code" in "
s
FLEXIBLE SECTOR-
ERASE ARCHITECTURE".)
HiddenROM Region
The HiddenROM feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the HiddenROM region is protected, any further
modification of that region is impossible. This ensures the security of the ESN once the product is shipped to
the field.
The HiddenROM region is 64 Kbytes in length and is stored at the same address of the 8 KB
8 sectors. The
MBM29DL32XTE occupies the address of the byte mode 3F0000h to 3FFFFFh (word mode 1F8000h to
1FFFFFh) and the MBM29DL32XBE type occupies the address of the byte mode 000000h to 00FFFFh (word
mode 000000h to 007FFFh) . After the system has written the Enter HiddenROM command sequence, the
system may read the HiddenROM region by using the addresses normally occupied by the boot sectors. That
is, the device sends all commands that would normally be sent to the boot sectors to the HiddenROM region.
This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending
commands to the boot sectors.
MBM29DL32XTE/BE
80
/90
44
When reading the HiddenROM region, either change addresses or change CE pin from "H" to "L". The same
procedure should be taken (changing addresses or CE pin from "H" to "L") after the system issues the Exit
HiddenROM command sequence to read actual data of memory cell.
HiddenROM Entry Command
MBM29DL32XTE/BE has a HiddenROM area with One Time Protect function. This area is to enter the security
code and to unable the change of the code once set. Program/erase is possible in this area until it is protected.
However, once it is protected, it is impossible to unprotect, so please use this with caution.
HiddenROM area is 64 KByte and in the same address area of 8 KB sector. The address of top boot is 3F0000h
to 3FFFFFh at byte mode (1F8000h to 1FFFFFh at word mode) and the bottom boot is 000000h to 00FFFFh
at byte mode (000000h to 007FFFh at word mode) . These areas are normally the boot block area (8 KB
8
sector) . Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called
as HiddenROM mode when the HiddenROM area appears.
Sector other than the boot block area could be read during HiddenROM mode. Read/program/erase of the
HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit
the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset
command sequence.
HiddenROM Program Command
To program the data to the HiddenROM area, write the HiddenROM program command sequence during
HiddenROM mode. This command is same as the program command in the past except to write the command
during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the
DQ
7
data poling, DQ
6
toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the
address other than the HiddenROM area is selected to program, the data of the address will be changed.
HiddenROM Erase Command
To erase the HiddenROM area, write the HiddenROM erase command sequence during HiddenROM mode.
This command is same as the sector erase command in the past except to write the command during
HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ
7
data
poling, DQ
6
toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector
address other than the HiddenROM area is selected, the data of the sector will be changed.
HiddenROM Protect Command
There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command
(60h) , set the sector address in the HiddenROM area and (A
6
, A
1
, A
0
)
=
(0, 1, 0) , and write the sector group
protect command (60h) during the HiddenROM mode. The same command sequence could be used because
except that it is in the HiddenROM mode and that it does not apply high voltage to RESET pin, it is the same as
the extension sector group protect in the past. Please refer to "Function Explanation Extended Command (3)
Extended Sector Group Protection" for details of extension sector group protect setting.
The other is to apply high voltage (V
ID
) to A
9
and OE, set the sector address in the HiddenROM area and (A
6
,
A
1
, A
0
)
=
(0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply
high voltage (V
ID
) to A
9
, specify (A
6
, A
1
, A
0
)
=
(0, 1, 0) and the sector address in the HiddenROM area, and
read. When "1" appears to DQ
0
, the protect setting is completed. "0" will appear to DQ
0
if it is not protected.
Please apply write pulse again. The same command sequence could be used for the above method because
other than the HiddenROM mode, it is the same as the sector group protect in the past. Please refer to "Function
Explanation Sector Group Protection" for details of sector group protect setting
Other sector group will be effected if the address other than the HiddenROM area is selected for the sector group
address, so please be careful. Once it is protected, protection can not be cancelled, so please pay closest
attention.
MBM29DL32XTE/BE
80
/90
45
Write Operation Status
Detailed in "Hardware Sequence Flags" in "
s
COMMAND DEFINITIONS" are all the status flags that can
determine the status of the bank for the current mode operation. The read operation from the bank where is not
operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether
a Embedded Algorithm is completed properly. The information on DQ
2
is address sensitive. This means that if
an address from an erasing sector is consecutively read, then the DQ
2
bit will toggle. However, DQ
2
will not
toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which
sectors are erasing and which are not.
The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there
is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1]
<
busy
bank
>
, [2]
<
non-busy bank
>
, [3]
<
busy bank
>
, the DQ
6
is toggling in the case of [1] and [3]. In case of [2],
the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ
6
will
not be toggled in the [1] and [3].
In the erase suspend read mode, DQ
2
is toggled in the [1] and [3]. In case of [2], the data of memory cell is
outputted.
Hardware Sequence Flags
*1 : Successive reads from the erasing or erase-suspend sector causes DQ
2
to toggle.
*2 : Reading from non-erase suspend sector address will indicate logic "1" at the DQ
2
bit.
DQ
7
Data Polling
The MBM29DL32XTE/BE devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ
7
. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded
Erase Algorithm, an attempt to read the device will produce a "0" at the DQ
7
output. Upon completion of the
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle*
1
Erase
Suspended
Mode
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
0
0
1*
2
Program
Suspended
Mode
Program Suspend Read
(Program Suspended Sector)
Data
Data
Data Data
Data
Program Suspend Read
(Non-Program Suspended Sector)
Data
Data
Data Data
Data
Exceeded
Time Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A
MBM29DL32XTE/BE
80
/90
46
Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ
7
output. The flowchart
for Data Polling (DQ
7
) is shown in "Data Polling Algorithm" in "
s
FLOW CHART".
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling also works as a flag to indicate whether the device is in erase-suspended
mode. DQ
7
goes from "0" to "1" during erase-suspended mode. Notice that to determine DQ
7
entering erase-
suspended mode, indicate the sector adress of sector being erased. Data Polling must be performed at sector
address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ
7
is active for approximately 1
s, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
7
is active for approximately 400
s, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTE/BE data pins (DQ
7
)
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ
7
at one instant of time and then that byte's valid data at the next instant of time.
Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See "Hardware Sequence Flags" in "
s
COMMAND DEFINITIONS".)
See "Data Polling during Embedded Algorithm Operation Timing Diagram" in "
s
TIMING DIAGRAM" for the Data
Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The MBM29DL32XTE/BE also feature the "Toggle Bit I" as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1
s and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ
6
to toggle.
The system can use DQ
6
to determine whether a sector is actively erasing or is erase-suspended. When a bank
is actively erasing (that is, the Embedded Erase Algorithm is in progress) , DQ
6
toggles. When a bank enters
the Erase Suspend mode, DQ
6
stops toggling. Successive read cycles during the erase-suspend-program cause
DQ
6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See "Toggle Bit I during Embedded Algorithm Operation Timing Diagram" in "
s
TIMING DIAGRAM" for the Toggle
Bit I timing specifications and diagrams.
MBM29DL32XTE/BE
80
/90
47
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions DQ
5
will produce a "1". This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) .
The OE and WE pins will control the output disable functions as described in "MBM29DL32XTE/BE User Bus
Operations (BYTE
=
V
IH
) " and "MBM29DL32XTE/BE User Bus Operations (BYTE
=
V
IL
) " in "
s
DEVICE BUS
OPERATION".
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the devices have exceeded timing limits, the
DQ
5
bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high ("1") the internally controlled
erase cycle has begun. If DQ
3
is low ("0") the device will accept additional sector erase commands. To insure
the command has been accepted, the system software should check the status of DQ
3
prior to and following
each subsequent Sector Erase command. If DQ
3
were high on the second status check, the command may not
have been accepted.
See "Hardware Sequence Flags" in "
s
COMMAND DEFINITIONS" : Hardware Sequence Flags.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic "1" at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows :
For example, DQ
2
and DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
(DQ
2
toggles while DQ
6
does not.) See also "Toggle Bit Status" in "
s
COMMAND DEFINITIONS" and "DQ
2
vs.
DQ
6
" in "
s
TIMING DIAGRAM".
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
MBM29DL32XTE/BE
80
/90
48
Reading Toggle Bits DQ
6
/DQ
2
Whenever the system initially begins reading toggle bit status, it must read DQ
7
to DQ
0
at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
7
to DQ
0
on the following read cycle.
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
5
is high (see the section on DQ
5
) . If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
5
has not
gone high. The system may continue to monitor the toggle bit and DQ
5
through successive read cycles, deter-
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the begining of the algorithm when it returns to determine the status
of the operation. (Refer to "Toggle Bit Algorithm" in "
s
FLOW CHART".)
Toggle Bit Status
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ
2
to toggle.
*2 : Reading from the non-erase suspend sector address will indicate logic "1" at the DQ
2
bit.
RY/BY
Ready/Busy
The MBM29DL32XTE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. If the MBM29DL32XTE/BE are placed in an Erase Suspend mode, the RY/BY output
will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to "RY/BY Timing Diagram during Program/Erase Operations"
and "RESET, RY/BY Timing Diagram" for a detailed timing diagram. The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
CC
; multiples of devices may
be connected to the host system via more than one RY/BY pin in parallel.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle*
1
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle
1*
2
MBM29DL32XTE/BE
80
/90
49
Data Protection
The MBM29DL32XTE/BE are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices automat-
ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(Min) . If V
CC
<
V
LKO
, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the
V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when V
CC
is above V
LKO
(Min) .
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Write Pulse "Glitch" Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE
=
V
IL
, CE
=
V
IH
, or WE
=
V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE
=
CE
=
V
IL
and OE
=
V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Group Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignored (see "
s
FUNCTIONAL DESCRIP-
TION Sector Group Protection")
MBM29DL32XTE/BE
80
/90
50
s
ABSOLUTE MAXIMUM RATINGS (See WARNING)
*1 : Voltage is defined on the basis of V
SS
=
GND
=
0 V.
*2 : Minimum DC voltage on input or I/O pins is
-
0.5 V. During voltage transitions, input or I/O pins may undershoot
V
SS
to
-
2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V
CC
+
0.5 V. During voltage
transitions, input or I/O pins may overshoot to V
CC
+
2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A
9
, OE and RESET pins is
-
0.5 V. During voltage transitions, A
9
, OE and RESET
pins may undershoot V
SS
to
-
2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage
(V
IN
-
V
CC
) does not exceed
+
9.0 V. Maximum DC input voltage on A
9
, OE and RESET pins is
+
13.0 V which
may overshoot to
+
14.0 V for periods of up to 20 ns.
*4 : Minimum DC input voltage on WP/ACC pin is
-
0.5 V. During voltage transitions, WP/ACC pin may undershoot
V
SS
to
-
2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is
+
10.5 V which may
overshoot to
+
12.0 V for periods of up to 20 ns when Vcc is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s
RECOMMENDED OPERATING CONDITIONS
* : Voltage is defined on the basis of V
SS
=
GND
=
0 V.
Note : Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Rating
Unit
Min
Max
Storage Temperature
T
stg
-
55
+
125
C
Ambient Temperature with Power Applied
T
A
-
40
+
85
C
Voltage with Respect to Ground All pins except
A
9
, OE, RESET *
1,
*
2
V
IN
, V
OUT
-
0.5
V
CC
+
0.5
V
Power Supply Voltage *
1
V
CC
-
0.5
+
4.0
V
A
9
, OE, and RESET *
1,
*
3
V
IN
-
0.5
+
13.0
V
WP/ACC *
1,
*
4
V
ACC
-
0.5
+
10.5
V
Parameter
Symbol
Conditions
Value
Unit
Min
Max
Ambient Temperature
T
A
MBM29DL32XTE/BE80/90
-
40
+
85
C
Power Supply Voltage*
V
CC
MBM29DL32XTE/BE80
+
3.0
+
3.6
V
MBM29DL32XTE/BE90
+
2.7
+
3.6
V
MBM29DL32XTE/BE
80
/90
51
s
MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+
0.6 V
-
0.5 V
20 ns
-
2.0 V
20 ns
20 ns
Maximum Undershoot Waveform
V
CC
+
0.5 V
+
2.0 V
V
CC
+
2.0 V
20 ns
20 ns
20 ns
Maximum Overshoot Waveform 1
+
13.0 V
V
CC
+
0.5 V
+
14.0 V
20 ns
20 ns
20 ns
Maximum Overshoot Waveform 2
Note : This waveform is applied for A
9
, OE, and RESET.
MBM29DL32XTE/BE
80
/90
52
s
DC CHARACTERISTICS
*1 : The I
CC
current listed includes both the DC operating current and the frequency dependent component.
*2 : I
CC
active while Embedded Algorithm (program or erase) is in progress.
*3 : This timing is only for Sector Group Protection operation and Autoselect mode.
*4 : Applicable for only V
CC
.
*5 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*6 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)
Parameter
Symbol
Conditions
Value
Unit
Min
Typ
Max
Input Leakage Current
I
LI
V
IN
=
V
SS
to V
CC
, V
CC
=
V
CC
Max
-
1.0
+
1.0
A
Output Leakage Current
I
LO
V
OUT
=
V
SS
to V
CC
, V
CC
=
V
CC
Max
-
1.0
+
1.0
A
A
9
, OE, RESET Inputs Leakage Current
I
LIT
V
CC
=
V
CC
Max,
A
9
, OE, RESET
=
12.5 V
+
35
A
WP/ACC Accelerated Program Current
I
LIA
V
CC
=
V
CC
Max,
WP/ACC
=
V
ACC
Max
20
mA
V
CC
Active Current *
1
I
CC1
CE
=
V
IL
, OE
=
V
IH
,
f
=
5 MHz
Byte
16
mA
Word
18
CE
=
V
IL
, OE
=
V
IH
,
f
=
1 MHz
Byte
7
mA
Word
7
V
CC
Active Current *
2
I
CC2
CE
=
V
IL
, OE
=
V
IH
35
mA
V
CC
Current (Standby)
I
CC3
V
CC
=
V
CC
Max, CE
=
V
CC
0.3
V, RESET
=
V
CC
0.3 V,
WP/ACC
=
V
CC
0.3 V
1
5
A
V
CC
Current (Standby, Reset)
I
CC4
V
CC
=
V
CC
Max,
RESET
=
V
SS
0.3 V
1
5
A
V
CC
Current
(Automatic Sleep Mode) *
5
I
CC5
V
CC
=
V
CC
Max, CE
=
V
SS
0.3 V,
RESET
=
V
CC
0.3 V,
V
IN
=
V
CC
0.3 V or V
SS
0.3 V
1
5
A
V
CC
Active Current *
6
(Read-While-Program)
I
CC6
CE
=
V
IL
, OE
=
V
IH
Byte
51
mA
Word
53
V
CC
Active Current *
6
(Read-While-Erase)
I
CC7
CE
=
V
IL
, OE
=
V
IH
Byte
51
mA
Word
53
V
CC
Active Current
(Erase-Suspend-Program)
I
CC8
CE
=
V
IL
, OE
=
V
IH
35
mA
Input Low Voltage
V
IL
-
0.5
+
0.6
V
Input High Voltage
V
IH
2.0
V
CC
+
0.3
V
Voltage for Autoselect and Sector Group
Protection (A
9
, OE, RESET) *
3,
*
4
V
ID
11.5
12
12.5
V
Voltage for WP/ACC Sector Group Protection/
Unprotection and Program Acceleration *
4
V
ACC
8.5
9.0
9.5
V
Output Low Voltage
V
OL
I
OL
=
4.0 mA, V
CC
=
V
CC
Min
0.45
V
Output High Voltage
V
OH1
I
OH
=
-
2.0 mA, V
CC
=
V
CC
Min
2.4
V
V
OH2
I
OH
=
-
100
A
V
CC
-
0.4
V
Low V
CC
Lock-Out Voltage
V
LKO
2.3
2.4
2.5
V
MBM29DL32XTE/BE
80
/90
53
s
AC CHARACTERISTICS
Note : Test Conditions :
Output Load : 1 TTL gate and 30 pF (MBM29DL32XTE/BE80)
1 TTL gate and 100 pF (MBM29DL32XTE/BE90)
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or 3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
Parameter
Symbol
Test
setup
Value (Note)
Unit
80
90
JEDEC
Standard
Min
Max
Min
Max
Read Cycle Time
t
AVAV
t
RC
80
90
ns
Address to Output Delay
t
AVQV
t
ACC
CE
=
V
IL
OE
=
V
IL
80
90
ns
Chip Enable to Output Delay
t
ELQV
t
CE
OE
=
V
IL
80
90
ns
Output Enable to Output Delay
t
GLQV
t
OE
30
35
ns
Chip Enable to Output High-Z
t
EHQZ
t
DF
25
30
ns
Output Enable to Output High-Z
t
GHQZ
t
DF
25
30
ns
Output Hold Time from Addresses,
CE or OE, Whichever Occurs First
t
AXQX
t
OH
0
0
ns
RESET Pin Low to Read Mode
t
READY
20
20
s
CE to BYTE Switching Low or High
t
ELFL
t
ELFH
5
5
ns
C
L
3.3 V
Diodes
=
IN3064
or Equivalent
2.7 k
Device
Under
Test
IN3064
or Equivalent
6.2 k
Test Conditions
Notes :
C
L
=
30 pF including jig capacitance (MB29DL32XTE/BE80)
C
L
=
100 pF including jig capacitance (MB29DL32XTE/BE90)
MBM29DL32XTE/BE
80
/90
54
Write/Erase/Program Operations
(Continued)
Parameter
Symbol
Value
Unit
80
90
JEDEC
Standard
Min
Typ
Max
Min
Typ
Max
Write Cycle Time
t
AVAV
t
WC
80
90
ns
Address Setup Time
t
AVWL
t
AS
0
0
ns
Address Setup Time to OE Low During
Toggle Bit Polling
t
ASO
12
15
ns
Address Hold Time
t
WLAX
t
AH
45
45
ns
Address Hold Time from CE or OE High
During Toggle Bit Polling
t
AHT
0
0
ns
Data Setup Time
t
DVWH
t
DS
30
35
ns
Data Hold Time
t
WHDX
t
DH
0
0
ns
Output Enable
Hold Time
Read
t
OEH
0
0
ns
Toggle and Data Polling
10
10
ns
CE High During Toggle Bit Polling
t
CEPH
20
20
ns
OE High During Toggle Bit Polling
t
OEPH
20
20
ns
Read Recover Time Before Write
t
GHWL
t
GHWL
0
0
ns
Read Recover Time Before Write
t
GHEL
t
GHEL
0
0
ns
CE Setup Time
t
ELWL
t
CS
0
0
ns
WE Setup Time
t
WLEL
t
WS
0
0
ns
CE Hold Time
t
WHEH
t
CH
0
0
ns
WE Hold Time
t
EHWH
t
WH
0
0
ns
Write Pulse Width
t
WLWH
t
WP
35
35
ns
CE Pulse Width
t
ELEH
t
CP
35
35
ns
Write Pulse Width High
t
WHWL
t
WPH
25
30
ns
CE Pulse Width High
t
EHEL
t
CPH
25
30
ns
Programming
Operation
Byte
t
WHWH1
t
WHWH1
8
8
s
Word
16
16
s
Sector Erase Operation*
1
t
WHWH2
t
WHWH2
1
1
s
V
CC
Setup Time
t
VCS
50
50
s
Rise Time to V
ID
*
2
t
VIDR
500
500
ns
Rise Time to V
ACC
*
3
t
VACCR
500
500
ns
Voltage Transition Time*
2
t
VLHT
4
4
s
Write Pulse Width*
2
t
WPP
100
100
s
OE Setup Time to WE Active*
2
t
OESP
4
4
s
CE Setup Time to WE Active*
2
t
CSP
4
4
s
Recover Time from RY/BY
t
RB
0
0
ns
RESET Pulse Width
t
RP
500
500
ns
MBM29DL32XTE/BE
80
/90
55
(Continued)
*1 : This does not include preprogramming time.
*2 : This timing is for Sector Group Protection operation.
*3 : This timing is limited for Acclerated Program Operation only.
Parameter
Symbol
Value
Unit
80
90
JEDEC
Standard
Min
Typ
Max
Min
Typ
Max
RESET High Level Period before Read
t
RH
200
200
ns
BYTE Switching Low to Output High-Z
t
FLQZ
30
30
ns
BYTE Switching High to Output Active
t
FHQV
80
90
ns
Program/Erase Valid to RY/BY Delay
t
BUSY
90
90
ns
Delay Time from Embedded Output Enable
t
EOE
80
90
ns
Erase Time-Out Time
t
TOW
50
50
s
Erase Suspend Transition Time
t
SPD
20
20
s
MBM29DL32XTE/BE
80
/90
56
s
ERASE AND PROGRAMMING PERFORMANCE
s
PIN CAPACITANCE
Notes :
Test conditions T
A
=
+
25
C, f
=
1.0 MHz
DQ
15
/A
-1
pin capacitance is stipulated by output capacitance.
s
FBGA PIN CAPACITANCE
Notes :
Test conditions T
A
=
+
25
C, f
=
1.0 MHz
DQ
15
/A
-1
pin capacitance is stipulated by output capacitance.
Parameter
Limit
Unit
Comments
Min
Typ
Max
Sector Erase Time
1
10
s
Excludes programming time
prior to erasure
Word Programming Time
16
360
s
Excludes system-level
overhead
Byte Programming Time
8
300
s
Chip Programming Time
100
s
Excludes system-level
overhead
Program/Erase Cycle
100,000
cycle
Parameter
Symbol
Test setup
Typ
Max
Unit
Input Capacitance
C
IN
V
IN
=
0
6.0
7.5
pF
Output Capacitance
C
OUT
V
OUT
=
0
8.5
12.0
pF
Control Pin Capacitance
C
IN2
V
IN
=
0
8.0
11.0
pF
WP/ACC Pin Capacitance
C
IN3
V
IN
=
0
21.5
22.5
pF
Parameter
Symbol
Condition
Typ
Max
Unit
Input Capacitance
C
IN
V
IN
=
0
7.0
9.0
pF
Output Capacitance
C
OUT
V
OUT
=
0
9.5
13.0
pF
Control Pin Capacitance
C
IN2
V
IN
=
0
9.0
12.0
pF
WP/ACC Pin Capacitance
C
IN3
V
IN
=
0
21.5
22.5
pF
MBM29DL32XTE/BE
80
/90
57
s
TIMING DIAGRAM
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
"H" or "L"
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will
Change
from H to L
Will
Change
from L to H
Changing
State
Unknown
Center Line is
High-
Impedance
"Off" State
Read Operation Timing Diagram
WE
OE
CE
t
ACC
t
DF
t
CE
t
OE
Outputs
t
RC
Address
Address Stable
High-Z
Output Valid
High-Z
t
OEH
t
OH
MBM29DL32XTE/BE
80
/90
58
RESET
t
ACC
t
OH
Outputs
t
RC
Address
Address Stable
High-Z
Outputs Valid
t
RH
CE
t
RP
t
RH
t
CE
Hardware Reset/Read Operation Timing Diagram
MBM29DL32XTE/BE
80
/90
59
t
CH
t
WP
t
WHWH1
t
WC
t
AH
CE
OE
t
RC
Address
Data
t
AS
t
OE
t
WPH
t
GHWL
t
DH
DQ
7
PD
A0h
D
OUT
WE
555h
PA
PA
t
OH
Data Polling
3rd Bus Cycle
t
CS
t
CE
t
DS
D
OUT
t
DF
Alternate WE Controlled Program Operation Timing Diagram
Notes :
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the
16 mode. (The addresses differ from
8 mode.)
MBM29DL32XTE/BE
80
/90
60
t
CP
t
DS
t
WHWH1
t
WC
t
AH
WE
OE
Address
Data
t
AS
t
CPH
t
DH
DQ
7
A0h
D
OUT
CE
555h
PA
PA
Data Polling
3rd Bus Cycle
t
WS
t
WH
t
GHEL
PD
Alternate CE Controlled Program Operation Timing Diagram
Notes :
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the
16 mode. (The addresses differ from
8 mode.)
MBM29DL32XTE/BE
80
/90
61
V
CC
CE
OE
Address
Data
t
WP
WE
555h
2AAh
555h
555h
2AAh
SA*
t
DS
t
CH
t
AS
t
AH
t
CS
t
WPH
t
DH
t
GHWL
t
VCS
t
WC
55h
55h
80h
AAh
AAh
10h/
30h
10 for chip Erase
Chip/Sector Erase Operation Timing Diagram
* : SA is the sector address for Sector Erase. Addresses
=
555h (Word) , AAAh (Byte) for Chip Erase.
Note : These waveforms are for the
16 mode. (The addresses differ from
8 mode.)
MBM29DL32XTE/BE
80
/90
62
t
OEH
t
OE
t
WHWH1 or 2
CE
OE
t
EOE
t
BUSY
WE
Data
t
DF
t
CH
t
CE
High-Z
High-Z
DQ
7
=
Valid Data
DQ
6
to DQ
0
Valid Data
DQ
7
*
DQ
7
DQ
6
to DQ
0
RY/BY
Data
DQ
6
to DQ
0
=
Output Flag
Data Polling during Embedded Algorithm Operation Timing Diagram
* : DQ
7
=
Valid Data (The device has completed the Embedded operation) .
MBM29DL32XTE/BE
80
/90
63
t
DH
t
OE
t
CE
CE
WE
OE
DQ
6
/DQ
2
Address
RY/BY
Data
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggling
Output
Valid
*
t
BUSY
t
OEH
t
OEH
t
OEPH
t
AHT
t
AHT
t
ASO
t
AS
t
CEPH
Toggle Bit I during Embedded Algorithm Operation Timing Diagram
* : DQ
6
stops toggling (The device has completed the Embedded operation) .
MBM29DL32XTE/BE
80
/90
64
CE
DQ
WE
Address
BA1
BA1
BA1
BA2
(555h)
BA2
(PA)
BA2
(PA)
OE
Valid
Output
Valid
Output
Valid
Output
Status
Valid
Intput
Valid
Intput
t
RC
t
RC
t
RC
t
RC
t
WC
t
WC
t
AHT
t
AS
t
AS
t
AH
t
ACC
t
CE
t
OE
t
OEH
t
WP
t
GHWL
t
DS
t
DF
t
DH
t
DF
t
CEPH
Read
Command
Command
Read
Read
Read
(A0h)
(PD)
Bank-to-bank Read/Write Timing Diagram
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1
BA2 : Address corresponding to Bank 2
DQ
2
*
DQ
6
WE
Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase
Erase
Complete
Toggle
DQ
2
and DQ
6
with OE or CE
DQ
2
vs. DQ
6
* : DQ
2
is read from the erase-suspended sector.
MBM29DL32XTE/BE
80
/90
65
Rising edge of the last WE signal
CE
RY/BY
WE
t
BUSY
Entire programming
or erase operations
RY/BY Timing Diagram during Program/Erase Operations
t
RP
RESET
t
READY
RY/BY
WE
t
RB
RESET, RY/BY Timing Diagram
MBM29DL32XTE/BE
80
/90
66
t
CE
t
FHQV
t
ELFH
A
-1
Data Output
(DQ
7
to DQ
0
)
Data Output
(DQ
14
to DQ
0
)
DQ
15
CE
BYTE
DQ
14
to DQ
0
DQ
15
/A
-1
Timing Diagram for Word Mode Configuration
t
ELFL
t
ACC
t
FLQZ
A
-1
Data Output
(DQ
14
to DQ
0
)
Data Output
(DQ
7
to DQ
0
)
DQ
15
CE
BYTE
DQ
14
to DQ
0
DQ
15
/A
-1
Timing Diagram for Byte Mode Configuration
Falling edge of the last write signal
CE or WE
t
AH
t
AS
Input
Valid
BYTE
BYTE Timing Diagram for Write Operations
MBM29DL32XTE/BE
80
/90
67
t
VLHT
SPAX
A
20
, A
19
, A
18
A
17
, A
16
, A
15
A
14
, A
13
, A
12
A
6
, A
0
SPAY
A
9
V
ID
V
IH
t
VLHT
OE
V
ID
V
IH
t
VLHT
t
VLHT
t
OESP
t
WPP
t
CSP
WE
CE
t
OE
01h
Data
V
CC
A
1
t
VCS
Sector Group Protection Timing Diagram
SPAX : Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
Note : A-
1
is V
IL
on byte mode.
MBM29DL32XTE/BE
80
/90
68
V
IH
RESET
V
CC
CE
WE
RY/BY
t
VLHT
Program or Erase Command Sequence
t
VLHT
t
VCS
t
VIDR
V
ID
t
VLHT
Unprotection period
Temporary Sector Group Unprotection Timing Diagram
MBM29DL32XTE/BE
80
/90
69
V
CC
WE
OE
CE
RESET
t
WC
t
WC
t
VLHT
t
VIDR
t
VCS
TIME-OUT
SPAX
SPAX
SPAY
t
WP
t
OE
60h
01h
40h
60h
60h
Data
Address
A
6
, A
0
A
1
Extended Sector Group Protection Timing Diagram
SPAX : Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window
=
250
s (Min)
MBM29DL32XTE/BE
80
/90
70
V
IH
WP/ACC
V
CC
CE
WE
RY/BY
t
VLHT
Program Command Sequence
t
VLHT
t
VCS
t
VACCR
V
ACC
t
VLHT
Acceleration period
Accelerated Program Timing Diagram
MBM29DL32XTE/BE
80
/90
71
s
FLOW CHART
555h/AAh
555h/A0h
2AAh/55h
Program Address/Program Data
Programming Completed
Last Address
?
Increment Address
Verify Data
?
Data Polling
Program Command Sequence (Address/Command)
:
Write Program
Command Sequence
(See Below)
Start
No
No
Yes
Yes
Embedded
Program
Algorithm
in program
Embedded Program
TM
Algorithm
Notes :
The sequence is applied for
16 mode.
The addresses differ from
8 mode.
EMBEDDED ALGORITHM
MBM29DL32XTE/BE
80
/90
72
555h/AAh
555h/80h
2AAh/55h
555h/AAh
555h/10h
2AAh/55h
555h/AAh
555h/80h
2AAh/55h
555h/AAh
Sector Address
/30h
Sector Address
/30h
Sector Address
/30h
2AAh/55h
Erasure Completed
Data
=
FFh
?
Data Polling
Write Erase
Command Sequence
(See Below)
Start
No
Yes
Embedded
Erase
Algorithm
in progress
Chip Erase Command Sequence
(Address/Command)
:
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command)
:
Additional sector
erase commands
are optional.
Embedded Erase
TM
Algorithm
Notes :
The sequence is applied for
16 mode.
The addresses differ from
8 mode.
EMBEDDED ALGORITHM
MBM29DL32XTE/BE
80
/90
73
DQ
7
=
Data?
DQ
5
=
1?
Fail
Pass
DQ
7
=
Data?
*
Read Byte
(DQ
7
to DQ
0
)
Addr.
=
VA
Read Byte
(DQ
7
to DQ
0
)
Addr.
=
VA
Start
No
No
No
Yes
Yes
Yes
Data Polling Algorithm
* : DQ
7
is rechecked even if DQ
5
=
"1" because DQ
7
may change simultaneously with DQ
5
.
VA
=
Address for programming
=
Any of the sector addresses
within the sector being erased
during sector erase or multiple
sector erases operation.
=
Any of the sector addresses
within the sector not being
protected during chip erase
operation.
MBM29DL32XTE/BE
80
/90
74
DQ
6
=
Toggle?
DQ
5
=
1?
DQ
6
=
Toggle?
Read DQ
7
to DQ
0
Addr.
=
VA
Read DQ
7
to DQ
0
Addr.
=
VA
Read DQ
7
to DQ
0
Twice
Addr.
=
VA
Start
No
No
No
Yes
Yes
Yes
*1
*1, 2
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
Toggle Bit Algorithm
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ
5
changes to "1".
VA
=
Bank address being executed
Embedded Algorithm.
MBM29DL32XTE/BE
80
/90
75
Start
No
No
No
Yes
Yes
Yes
Data
=
01h?
Device Failed
PLSCNT
=
25?
PLSCNT
=
1
Remove V
ID
from A
9
Write Reset Command
Remove V
ID
from A
9
Write Reset Command
Sector Group Protection
Completed
Protect Another Sector
Group?
Increment PLSCNT
Read from Sector Group
Addr.
=
SPA, A
1
=
V
IH
A
6
=
A
0
=
V
IL
Setup Sector Group Addr.
A
20
, A
19
, A
18
, A
17
,A
16
,
A
15
, A
14
, A
13
, A
12
OE
=
V
ID
, A
9
=
V
ID
CE
=
V
IL
, RESET
=
V
IH
A
6
=
A
0
=
V
IL
, A
1
=
V
IH
Activate WE Pulse
Time out 100
s
WE
=
V
IH
, CE
=
OE
=
V
IL
(A
9
should remain V
ID
)
(
)
(
)
*
Sector Group Protection Algorithm
* : A-
1
is V
IL
on byte mode.
MBM29DL32XTE/BE
80
/90
76
Start
Perform Erase or
Program Operations
RESET
=
V
ID
*1
RESET
=
V
IH
Temporary Sector Group
Unprotection Completed
*2
Temporary Sector Group Unprotection Algorithm
*1 : All protected sector groups are unprotected.
*2 : All previously protected sector groups are protected once again.
MBM29DL32XTE/BE
80
/90
77
Start
No
Yes
Yes
Data
=
01h?
PLSCNT
=
1
No
No
Yes
Device Failed
PLSCNT
=
25?
Remove V
ID
from RESET
Write Reset Command
Sector Group
Protection Completed
Protect Other Sector
Group?
Increment PLSCNT
Read from Sector Group Address
(A
6
=
A
0
=
V
IL
, A
1
=
V
IH
)
Remove V
ID
from RESET
Write Reset Command
Time out 250
s
RESET
=
V
ID
Wait to 4
s
No
Yes
Setup Next Sector
Group Address
Device is Operating in
Temporary Sector Group
Unprotection Mode
To Protect Secter Group
Write 60h to Secter Address
(A
6
=
A
0
=
V
IL
, A
1
=
V
IH
)
To Verify Sector Group Protection
Write 40h to Secter Address
(A
6
=
A
0
=
V
IL
, A
1
=
V
IH
)
To Setup Sector Group Protection
Write XXXh/60h
Extended Sector Group
Protection Entry?
Extended Sector Group Protection Algorithm
MBM29DL32XTE/BE
80
/90
78
555h/AAh
555h/20h
(BA) XXXh/90h
XXXh/F0h
XXXh/A0h
2AAh/55h
Program Address/Program Data
Programming Completed
Last Address?
Increment Address
Verify Data?
Data Polling
Start
No
No
Yes
Yes
Set Fast Mode
In Fast Program
Reset Fast Mode
Embedded Programming Algorithm for Fast Mode
Note : The sequence is applied for
16 mode.
The addresses differ from
8 mode.
FAST MODE ALGORITHM
MBM29DL32XTE/BE
80
/90
79
s
ORDERING INFORMATION
(Continued)
Part No.
Package
Access Time (ns)
Remarks
MBM29DL322TE80TN
MBM29DL322TE90TN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
80
90
Top Sector
MBM29DL323TE80TN
MBM29DL323TE90TN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
80
90
MBM29DL324TE90TN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
90
MBM29DL322TE80TR
MBM29DL322TE90TR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
80
90
MBM29DL323TE80TR
MBM29DL323TE90TR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
80
90
MBM29DL324TE90TR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
90
MBM29DL322TE80PBT
MBM29DL322TE90PBT
63-pin plastic FBGA
(BGA-63P-M01)
80
90
MBM29DL323TE80PBT
MBM29DL323TE90PBT
63-pin plastic FBGA
(BGA-63P-M01)
80
90
MBM29DL324TE90PBT
63-pin plastic FBGA
(BGA-63P-M01)
90
MBM29DL322BE80TN
MBM29DL322BE90TN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
80
90
Bottom Sector
MBM29DL323BE80TN
MBM29DL323BE90TN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
80
90
MBM29DL324BE90TN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
90
MBM29DL322BE80TR
MBM29DL322BE90TR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
80
90
MBM29DL323BE80TR
MBM29DL323BE90TR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
80
90
MBM29DL324BE90TR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
90
MBM29DL32XTE/BE
80
/90
80
(Continued)
Part No.
Package
Access Time (ns)
Remarks
MBM29DL322BE80PBT
MBM29DL322BE90PBT
63-pin plastic FBGA
(BGA-63P-M01)
80
90
Bottom Sector
MBM29DL323BE80PBT
MBM29DL323BE90PBT
63-pin plastic FBGA
(BGA-63P-M01)
80
90
MBM29DL324BE90PBT
63-pin plastic FBGA
(BGA-63P-M01)
90
MBM29DL32X T E 80 TN
DEVICE NUMBER/DESCRIPTION
MBM29DL32X
32 Mega-bit (4 M
8-Bit or 2 M
16-Bit) CMOS Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
PACKAGE TYPE
TN
=
48-Pin Thin Small Outline Package
(TSOP) Normal Bend
TR
=
48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PBT
=
Fine pitch Ball Grid Array
Package (FBGA)
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
B
=
Bottom sector
MBM29DL32XTE/BE
80
/90
81
s
PACKAGE DIMENSIONS
(Continued)
48-pin plastic TSOP (1)
(FPT-48P-M19)
Note 1)
*
: Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
.003
+.001
0.08
+0.03
.007
0.17
"A"
(Stand off height)
0.10(.004)
(Mounting
height)
(.472.008)
12.00
0.20
LEAD No.
48
25
24
1
(.004
.002)
0.10(.004)
M
1.10
+0.10
0.05
+.004
.002
.043
0.10
0.05
(.009
.002)
0.22
0.05
(.787
.008)
20.00
0.20
(.724
.008)
18.40
0.20
INDEX
2003 FUJITSU LIMITED F48029S-c-6-7
C
0~8
0.25(.010)
0.50(.020)
0.60
0.15
(.024
.006)
Details of "A" part
*
*
MBM29DL32XTE/BE
80
/90
82
(Continued)
48-pin plastic TSOP (1)
(FPT-48P-M20)
Note 1)
*
: Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
.003
+.001
.007
0.08
+0.03
0.17
"A"
(Stand off height)
(.004
.002)
0.10
0.05
0.10(.004)
(Mounting height)
12.000.20(.472.008)
LEAD No.
48
25
24
1
0.10(.004)
M
1.10
+0.10
0.05
+.004
.002
.043
(.009
.002)
0.22
0.05
(.787
.008)
20.00
0.20
(.724
.008)
18.40
0.20
INDEX
2003 FUJITSU LIMITED F48030S-c-6-7
C
0~8
0.25(.010)
0.600.15
(.024.006)
Details of "A" part
*
*
0.50(.020)
MBM29DL32XTE/BE
80
/90
83
(Continued)
63-ball plastic FBGA
(BGA-63P-M01)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED B63001S-c-2-2
11.00
0.10(.433
.004)
.041
.004
+.006
0.10
+0.15
1.05
(Mounting height)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
0.80(.031)TYP
(5.60(.220))
(5.60(.220))
INDEX BALL
M
0.08(.003)
0.10(.004)
INDEX AREA
7.00
0.10
(.276
.004)
(7.20(.283))
J
K
(63-0.18
.002)
63-0.45
0.05
M
L
(8.80(.346))
(4.00(.157))
0.38
0.10
(.015
.004)
(Stand off)
MBM29DL32XTE/BE
80
/90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party's
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0303
FUJITSU LIMITED Printed in Japan
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