DS05-20860-6E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
8M (1M
8 / 512K
16) BIT
MBM29DL800TA
-70/90
/MBM29DL800BA
-70/90
s
FEATURES
Single 3.0 V read, program, and erase
Minimizes system level power requirements
Simultaneous operations
Read-while-Erase or Read-while-Program
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
Compatible with JEDEC-standard worldwide pinouts (Pin compatible with MBM29LV800TA/BA)
48-pin TSOP(1) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
Minimum 100,000 program/erase cycles
High performance
70 ns maximum access time
Sector erase architecture
Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
Low V
CC
write inhibit
2.5 V
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
(Continued)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
2
(Continued)
Sector protection
Hardware method disables any combination of sectors from program or erase operations
Sector Protection Set function by Extended sector protection command
Fast Programming Function by Extended Command
Temporary sector unprotection
Temporary sector unprotection via the RESET pin.
s
PACKAGES
48-pin plastic TSOP (I)
(FPT-48P-M19)
48-pin plastic TSOP (I)
(FPT-48P-M20)
Marking Side
Marking Side
48-pin plastic FBGA
(BGA-48P-M12)
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
3
s
GENERAL DESCRIPTION
The MBM29DL800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1 M bytes of 8 bits each or
512 K words of 16 bits each. The MBM29DL800TA/BA are offered in a 48-pin TSOP(1) and 48-ball FBGA
packages. These devices are designed to be programmed in-system with the standard system 3.0 V V
CC
supply.
12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations. The devices can also be reprogrammed
in standard EPROM programmers.
MBM29DL800TA/BA provide simultaneous operation which can read a data during program/erase. The
simultaneous operation architecture provides simultaneous operation by dividing the memory space into two
banks. The device can allow a host system to program or erase in one bank, then immediately and simultaneously
read from the other bank.
The standard MBM29DL800TA/BA offer access times 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29DL800TA/BA are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29DL800TA/BA are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL800TA/BA are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29DL800TA/BA memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
4
s
s
s
s
PRODUCT LINE UP
s
BLOCK DIAGRAM
Part No.
MBM29DL800TA/MBM29DL800BA
Ordering Part No.
V
CC
= 3.3 V
-70
--
V
CC
= 3.0 V
--
-90
Max Address Access Time (ns)
70
90
Max CE Access Time (ns)
70
90
Max OE Access Time (ns)
30
35
V
SS
V
CC
Bank 2 Address
Bank 1 Address
WE
CE
A
0
to A
18
(A
-1
)
OE
BYTE
RESET
DQ
0
to DQ
15
RY/BY
State
Control
Command
Register
X-Decoder
X-Decoder
Cell Matrix
(Bank 2)
Cell Matrix
(Bank 1)
Y-Gating & Data Latch
Y-Gating &
Data Latch
DQ
0
to DQ
15
Status
+0.3 V
0.3 V
+0.6 V
0.3 V
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
5
s
PIN ASSIGNMENTS
(Continued)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MBM29DL800TA/MBM29DL800BA
Normal Bend
MBM29DL800TA/MBM29DL800BA
Reverse Bend
TSOP(1)
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
(Marking Side)
(Marking Side)
(FPT-48P-M19)
(FPT-48P-M20)
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
6
(Continued)
A3
A1
A2
A6
A5
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
(Top View)
Marking side
FBGA
A4
A1
A
3
A2
A
7
A3
RY/BY
A4
WE
A5
A
9
A6
A
13
B1
A
4
B2
A
17
B3
N.C.
B4
RESET
B5
A
8
B6
A
12
C1
A
2
C2
A
6
C3
A
18
C4
N.C.
C5
A
10
C6
A
14
D1
A
1
D2
A
5
D3
N.C.
D4
N.C.
D5
A
11
D6
A
15
E1
A
0
E2
DQ
0
E3
DQ
2
E4
DQ
5
E5
DQ
7
E6
A
16
F1
CE
F2
DQ
8
F3
DQ
10
F4
DQ
12
F5
DQ
14
F6
BYTE
G1
OE
G2
DQ
9
G3
DQ
11
G4
V
CC
G5
DQ
13
G6
DQ
15
/A
-1
H1
V
SS
H2
DQ
1
H3
DQ
3
H4
DQ
4
H5
DQ
6
H6
V
SS
(BGA-48P-M12)
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
7
s
s
s
s
PIN DESCRIPTION
s
s
s
s
LOGIC SYMBOL
Pin Name
Function
A
-1
, A
0
to A
18
Address Inputs
DQ
0
to DQ
15
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector
Unprotection
BYTE
Selects 8-bit or 16-bit mode
N.C.
No Internal Connection
V
SS
Device Ground
V
CC
Device Power Supply
19
A
0
to A
18
WE
OE
CE
DQ
0
to DQ
15
16 or 8
BYTE
RESET
A
-1
RY/BY
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
8
s
s
s
s
DEVICE BUS OPERATION
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
,
= Pulse input. See "
DC CHARACTERISTICS" for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence. See
"MBM29DL800TA/BA Command Definitions Table".
*2 : Refer to the section on Sector Protection.
*3 : WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
*4 : V
CC
= 3.0 V 10%
*5 : It is also used for the extended sector protection.
MBM29DL800TA/BA User Bus Operations Table (BYTE = V
IH
)
Operation
CE
OE
WE
A
0
A
1
A
6
A
9
DQ
0
to DQ
15
RESET
Auto-Select Manufacturer Code*
1
L
L
H
L
L
L
V
ID
Code
H
Auto-Select Device Code*
1
L
L
H
H
L
L
V
ID
Code
H
Read*
3
L
L
H
A
0
A
1
A
6
A
9
D
OUT
H
Standby
H
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
A
0
A
1
A
6
A
9
D
IN
H
Enable Sector Protection*
2
, *
4
L
V
ID
L
H
L
V
ID
X
H
Verify Sector Protection *
2
, *
4
L
L
H
L
H
L
V
ID
Code
H
Temporary Sector Unprotection*
5
X
X
X
X
X
X
X
X
V
ID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
High-Z
L
MBM29DL800TA/BA User Bus Operations Table (BYTE = V
IL
)
Operation
CE
OE
WE
DQ
15
/
A
-1
A
0
A
1
A
6
A
9
DQ
0
to DQ
7
RESET
Auto-Select Manufacturer Code*
1
L
L
H
L
L
L
L
V
ID
Code
H
Auto-Select Device Code*
1
L
L
H
L
H
L
L
V
ID
Code
H
Read*
3
L
L
H
A
-1
A
0
A
1
A
6
A
9
D
OUT
H
Standby
H
X
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
A
-1
A
0
A
1
A
6
A
9
D
IN
H
Enable Sector Protection*
2
, *
4
L
V
ID
L
L
H
L
V
ID
X
H
Verify Sector Protection *
2
, *
4
L
L
H
L
L
H
L
V
ID
Code
H
Temporary Sector Unprotection *
5
X
X
X
X
X
X
X
X
X
V
ID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
High-Z
L
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
9
*1 : This command is valid during Fast Mode.
*2 : This command is valid while RESET=V
ID
.
*3 : This data "00h" is also acceptable.
Notes :
Address bits A
12
to A
18
= X = "H" or "L" for all address commands except or Program Address (PA), Sector
Address (SA), and Bank Address (BA).
Bus operations are defined in "MBM29DL800TA/BA User Bus Operations Tables (BYTE = V
IH
and BYTE
= V
IL
)".
RA =Address of the memory location to be read
PA =Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA =Address of the sector to be erased. The combination of A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
will
uniquely select any sector.
BA =Bank Address (A
16
to A
18
)
RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
SPA =Sector address to be protected. Set sector address (SA) and (A
6
, A
1
, A
0
) = (0, 1, 0).
SD =Sector protection verify data. Output 01h at protected sector addresses and output 00h at
unprotected sector addresses.
The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A
0
to A
11
Byte Mode: AAAh or 555h to addresses A
1
and A
0
to A
11
Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
The command combinations not described in "MBM29DL800TA/BA Command Definitions Table" are illegal.
MBM29DL800TA/BA Command Definitions Table
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset
Word
1
XXXh
F0h
--
--
--
--
--
--
--
--
--
--
Byte
Read/Reset
Word
3
555h
AAh
2AAh
55h
555h
F0h
RA
RD
--
--
--
--
Byte
AAAh
555h
AAAh
Autoselect
Word
3
555h
AAh
2AAh
55h
(BA)
555h
90h
--
--
--
--
--
--
Byte
AAAh
555h
(BA)
AAAh
Program
Word
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
--
--
--
--
Byte
AAAh
555h
AAAh
Chip Erase
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Byte
AAAh
555h
AAAh
AAAh
555h
AAAh
Sector Erase
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
SA
30h
Byte
AAAh
555h
AAAh
AAAh
555h
Erase Suspend
1
BA
B0h
--
--
--
--
--
--
--
--
--
--
Erase Resume
1
BA
30h
--
--
--
--
--
--
--
--
--
--
Set to
Fast Mode
Word
3
555h
AAh
2AAh
55h
555h
20h
--
--
--
--
--
--
Byte
AAAh
555h
AAAh
Fast
Program *
1
Word
2
XXXh
A0h
PA
PD
--
--
--
--
--
--
--
--
Byte
XXXh
Reset from
Fast Mode *
1
Word
2
BA
90h
XXXh
F0h
*
3
--
--
--
--
--
--
--
--
Byte
BA
XXXh
Extended
Sector
Protect*
2
Word
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
--
--
--
--
Byte
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
10
*1 : A
-1
is for Byte mode. At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A
-1
, the lowest address.
*2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
(B): Byte mode
(W): Word mode
HI-Z: High-Z
* : At Byte mode, DQ
8
to DQ
14
are High-Z and DQ
15
is A-
1
, the lowest address.
MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table
Type
A
12
to A
18
A
6
A
1
A
0
A
-1
*1
Code (HEX)
Manufacture's Code
X
V
IL
V
IL
V
IL
V
IL
04h
Device Code
MBM29DL800TA
Byte
X
V
IL
V
IL
V
IH
V
IL
4Ah
Word
X
224Ah
MBM29DL800BA
Byte
X
V
IL
V
IL
V
IH
V
IL
CBh
Word
X
22CBh
Sector Protection
Sector
Addresses
V
IL
V
IH
V
IL
V
IL
01h
*2
Extended Autoselect Code Table
Type
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacturer's Code
04h
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Device
Code
MBM29DL800TA
(B)*
4Ah A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
1
0
0
1
0
1
0
(W)
224Ah
0
0
1
0
0
0
1
0
0
1
0
0
1
0
1
0
MBM29DL800BA
(B)*
CBh A
-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
1
1
0
0
1
0
1
1
(W) 22CBh
0
0
1
0
0
0
1
0
1
1
0
0
1
0
1
1
Sector Protection
01h
A
-1
/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
11
s
s
s
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
Two 16 K bytes, four 8 K bytes, two 32 K bytes, and fourteen 64 K bytes
Individual-sector, multiple-sector, or bulk-erase capability
Individual or multiple-sector protection is user definable.
16 K byte
32 K byte
8 K byte
8 K byte
8 K byte
8 K byte
32 K byte
16 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
7FFFFh
7DFFFh
79FFFh
78FFFh
77FFFh
76FFFh
75FFFh
71FFFh
6FFFFh
67FFFh
5FFFFh
57FFFh
4FFFFh
47FFFh
3FFFFh
37FFFh
2FFFFh
27FFFh
1FFFFh
17FFFh
0FFFFh
07FFFh
00000h
FFFFFh
FBFFFh
F3FFFh
F1FFFh
EFFFFh
EDFFFh
EBFFFh
E3FFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
00000h
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
64 K byte
16 K byte
32 K byte
8 K byte
8 K byte
8 K byte
8 K byte
32 K byte
16 K byte
FFFFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
1BFFFh
13FFFh
11FFFh
0FFFFh
0DFFFh
0BFFFh
03FFFh
00000h
7FFFFh
77FFFh
6FFFFh
67FFFh
5FFFFh
57FFFh
4FFFFh
47FFFh
3FFFFh
37FFFh
2FFFFh
27FFFh
1FFFFh
17FFFh
0FFFFh
0DFFFh
09FFFh
08FFFh
07FFFh
06FFFh
05FFFh
01FFFh
00000h
MBM29DL800TA Sector Architecture
MBM29DL800BA Sector Architecture
(
16)
(
8)
(
16)
(
8)
Bank 2
Bank 1
Bank 2
Bank 1
MB
M29DL800TA
-70/90
/MBM29DL800BA
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12
Note : The address range is A
18
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
18
: A
0
if in word mode (BYTE = V
IH
).
Sector Address Table (MBM29DL800BA)
Bank
Sector
Sector Address
Sector Size
(Kbytes/
Kwords)
(
8)
Address Range
(
16)
Address Range
Bank
Address
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Bank 2
SA21
1
1
1
1
X
X
X
64/32
F0000h to FFFFFh
78000h to 7FFFFh
SA20
1
1
1
0
X
X
X
64/32
E0000h to EFFFFh
70000h to 77FFFh
SA19
1
1
0
1
X
X
X
64/32
D0000h to DFFFFh
68000h to 6FFFFh
SA18
1
1
0
0
X
X
X
64/32
C0000h to CFFFFh
60000h to 67FFFh
SA17
1
0
1
1
X
X
X
64/32
B0000h to BFFFFh
58000h to 5FFFFh
SA16
1
0
1
0
X
X
X
64/32
A0000h to AFFFFh
50000h to 57FFFh
SA15
1
0
0
1
X
X
X
64/32
90000h to 9FFFFh
48000h to 4FFFFh
SA14
1
0
0
0
X
X
X
64/32
80000h to 8FFFFh
40000h to 47FFFh
SA13
0
1
1
1
X
X
X
64/32
70000h to 7FFFFh
38000h to 3FFFFh
SA12
0
1
1
0
X
X
X
64/32
60000h to 6FFFFh
30000h to 37FFFh
SA11
0
1
0
1
X
X
X
64/32
50000h to 5FFFFh
28000h to 2FFFFh
SA10
0
1
0
0
X
X
X
64/32
40000h to 4FFFFh
20000h to 27FFFh
SA9
0
0
1
1
X
X
X
64/32
30000h to 3FFFFh
18000h to 1FFFFh
SA8
0
0
1
0
X
X
X
64/32
20000h to 2FFFFh
10000h to 17FFFh
Bank 1
SA7
0
0
0
1
1
1
X
16/8
1C000h to 1FFFFh
0E000h to 0FFFFh
SA6
0
0
0
1
1
0
X
32/16
18000h to 1BFFFh,
14000h to 17FFFh
0C000h to 0DFFFh,
0A000h to 0BFFFh
0
1
X
SA5
0
0
0
1
0
0
1
8/4
12000h to 13FFFh
09000h to 09FFFh
SA4
0
0
0
1
0
0
0
8/4
10000h to 11FFFh
08000h to 08FFFh
SA3
0
0
0
0
1
1
1
8/4
0E000h to 0FFFFh
07000h to 07FFFh
SA2
0
0
0
0
1
1
0
8/4
0C000h to 0DFFFh
06000h to 06FFFh
SA1
0
0
0
0
1
0
X
32/16
08000h to 0BFFFh,
04000h to 07FFFh
04000h to 05FFFh,
02000h to 03FFFh
0
1
X
SA0
0
0
0
0
0
0
X
16/8
00000h to 03FFFh
00000h to 01FFFh
MB
M29DL800TA
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/MBM29DL800BA
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13
Note : The address range is A
18
: A
-1
if in byte mode (BYTE = V
IL
).
The address range is A
18
: A
0
if in word mode (BYTE = V
IH
).
Sector Address Table (MBM29DL800TA)
Bank
Sector
Sector Address
Sector Size
(Kbytes/
Kwords)
(
8)
Address Range
(
16)
Address Range
Bank
Address
A
18
A
17
A
16
A
15
A
14
A
13
A
12
Bank 2
SA0
0
0
0
0
X
X
X
64/32
00000h to 0FFFFh
00000h to 07FFFh
SA1
0
0
0
1
X
X
X
64/32
10000h to 1FFFFh
08000h to 0FFFFh
SA2
0
0
1
0
X
X
X
64/32
20000h to 2FFFFh
10000h to 17FFFh
SA3
0
0
1
1
X
X
X
64/32
30000h to 3FFFFh
18000h to 1FFFFh
SA4
0
1
0
0
X
X
X
64/32
40000h to 4FFFFh
20000h to 27FFFh
SA5
0
1
0
1
X
X
X
64/32
50000h to 5FFFFh
28000h to 2FFFFh
SA6
0
1
1
0
X
X
X
64/32
60000h to 6FFFFh
30000h to 37FFFh
SA7
0
1
1
1
X
X
X
64/32
70000h to 7FFFFh
38000h to 3FFFFh
SA8
1
0
0
0
X
X
X
64/32
80000h to 8FFFFh
40000h to 47FFFh
SA9
1
0
0
1
X
X
X
64/32
90000h to 9FFFFh
48000h to 4FFFFh
SA10
1
0
1
0
X
X
X
64/32
A0000h to AFFFFh
50000h to 57FFFh
SA11
1
0
1
1
X
X
X
64/32
B0000h to BFFFFh
58000h to 5FFFFh
SA12
1
1
0
0
X
X
X
64/32
C0000h to CFFFFh
60000h to 67FFFh
SA13
1
1
0
1
X
X
X
64/32
D0000h to DFFFFh
68000h to 6FFFFh
Bank 1
SA14
1
1
1
0
0
0
X
16/8
E0000h to E3FFFh
70000h to 71FFFh
SA15
1
1
1
0
0
1
X
32/16
E4000h to E7FFFh,
E8000h to EBFFFh
72000h to 73FFFh,
74000h to 75FFFh
1
0
X
SA16
1
1
1
0
1
1
0
8/4
EC000h to EDFFFh
76000h to 76FFFh
SA17
1
1
1
0
1
1
1
8/4
EE000h to EFFFFh
77000h to 77FFFh
SA18
1
1
1
1
0
0
0
8/4
F0000h to F1FFFh
78000h to 78FFFh
SA19
1
1
1
1
0
0
1
8/4
F2000h to F3FFFh
79000h to 79FFFh
SA20
1
1
1
1
0
1
X
32/16
F4000h to F7FFFh,
F8000h to FBFFFh
7A000h to 7BFFFh,
7C000h to 7DFFFh
1
0
X
SA21
1
1
1
1
1
1
X
16/8
FC000h to FFFFFh
7E000h to 7FFFFh
MB
M29DL800TA
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/MBM29DL800BA
-70/90
14
s
s
s
s
FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL800TA/BA have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A
16
to A
18
) with zero latency.
The MBM29DL800TA/BA have two banks which contain Bank 1 (16 KB, 32 KB, 8 KB, 8 KB, 8 KB, 8 KB, 32 KB,
and 16 KB) and Bank 2 (64 KB
fourteen sectors).
The simultaneous operation can not execute multi-function mode in the same bank. "Simultaneous Operation
Table" shows combination to be possible for simultaneous operation.
*: An erase operation may also be supended to read from or program to a sector not being erased.
Read Mode
The MBM29DL800TA/BA have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t
ACC
-t
OE
time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from "H" or "L"
Standby Mode
There are two ways to implement the standby mode on the MBM29DL800TA/BA devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
0.3 V.
Under this condition the current consumed is less than 5
A Max During Embedded Algorithm operation, V
CC
active current (I
CC2
) is required even CE = "H". The device can be read with standard access time (t
CE
) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
0.3 V (CE
= "H" or "L"). Under this condition the current is consumed is less than 5
A Max Once the RESET pin is taken
high, the device requires t
RH
of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Simultaneous Operation Table
Case
Bank 1 Status
Bank 2 Status
1
Read mode
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode *
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode *
Read mode
MB
M29DL800TA
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/MBM29DL800BA
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15
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL800TA/BA data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29DL800TA/BA automatically switch themselves to low power mode when
MBM29DL800TA/BA addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1
A (CMOS Level).
During simultaneous operation, V
CC
active current (I
CC2
) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL800TA/BA read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (V
IH
), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force V
ID
(11.5 V to 12.5 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are DON'T CARES except A
0
, A
1
, and A
6
(A
-1
). (See "MBM29DL800TA/BA User Bus Operations
Tables (BYTE = V
IH
and BYTE = V
IL
)" in
s
DEVICE BUS OPERATION.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL800TA/BA are erased or programmed in a system without access to high voltage on the A
9
pin. The
command sequence is illustrated in "MBM29DL800TA/BA Command Definitions Table" (in
s
DEVICE BUS
OPERATION). (Refer to Autoselect Command section.)
Word 0 (A
0
= V
IL
) represents the manufacturer's code (Fujitsu = 04h) and word 1 (A
0
= V
IH
) represents the device
identifier code (MBM29DL800TA = 4Ah and MBM29DL800BA = CBh for
8 mode; MBM29DL800TA = 224Ah
and MBM29DL800BA = 22CBh for
16 mode). These two bytes/words are given in "MBM29DL800TA/BA Sector
Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" (in
s
DEVICE BUS
OPERATION). All identifiers for manufactures and device will exhibit odd parity with DQ
7
defined as the parity
bit. In order to read the proper device codes when executing the autoselect, A
1
must be V
IL
. (See
"MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table"
in
s
DEVICE BUS OPERATION.)
In case of applying V
ID
on A
9
, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation
can not be executed.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
MB
M29DL800TA
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/MBM29DL800BA
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16
Sector Protection
The MBM29DL800TA/BA feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 21). The sector protection feature is enabled using programming
equipment at the user's site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.
To activate this mode, the programming equipment must force V
ID
on address pin A
9
and control pin OE, (suggest
V
ID
= 11.5 V), CE = V
IL
, and A
0
= A
6
= V
IL
, A
1
= V
IH
. The sector addresses (A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
)
should be set to the sector to be protected. "Sector Address Tables (MBM29DL800TA/BA)" in
s
FLEXIBLE
SECTOR-ERASE ARCHITECTURE define the sector address for each of the twenty two (22) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
rising edge of the same. Sector addresses must be held constant during the WE pulse. See "(13) AC Waveforms
for Sector Protection" in
s
TIMING DIAGRAM and "(5) Sector Protection Algorithm" in
s
FLOW CHART for sector
protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector addresses (A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
) while
(A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical "1" code at device output DQ
0
for a protected sector. Otherwise the
devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A
0
, A
1
, and A
6
are DON'T CARES. Address locations with A
1
= V
IL
are reserved for Autoselect manufacturer and device codes.
A
-1
requires to apply to V
IL
on byte mode.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where the higher order addresses (A
18
, A
17
, A
16
, A
15
, A
14
, A
13
,
and A
12
) are the desired sector address will produce a logical "1" at DQ
0
for a protected sector. See
"MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table"
in
s
DEVICE BUS OPERATION for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29DL800TA/BA devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. See "(14) Temporary Sector Unprotection Timing Diagram" in
s
TIMING DIAGRAM and "(6) Temporary
Sector Unprotection Algorithm" in
s
FLOW CHART.
RESET
Hardware Reset
The MBM29DL800TA/BA devices may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20
s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional t
RH
before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See "(9) RESET/RY/BY Timing
Diagram" in
s
TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.
MB
M29DL800TA
-70/90
/MBM29DL800BA
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17
s
s
s
s
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed
to bank being read, the commands have priority than reading. "MBM29DL800TA/BA Command Definitions Table"
in
s
DEVICE BUS OPERATION defines the valid register command sequences. Note that the Erase Suspend
(B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress.
Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please
note that commands are always written at DQ
0
to DQ
7
and DQ
8
to DQ
15
bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
5
= 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and an actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read
cycle from address (BA)01h for
16((BA)02h for
8) returns the device code (MBM29DL800TA = 4Ah and
MBM29DL800BA = CBh for
8 mode; MBM29DL800TA = 224Ah and MBM29DL800BA = 22CBh for
16 mode).
(See "MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table" and "Extended Autoselect Code
Table" in
s
DEVICE BUS OPERATION.)
All manufacturer and device codes will exhibit odd parity with DQ
7
defined as the parity bit. Sector state (protection
or unprotection) will be informed by address (BA)02h for
16 ((BA)04h for
8). Scanning the sector addresses
(A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical "1" at device output DQ
0
for a protected sector. The programming verification should be performed by verify sector protection on the
protected sector. (See "MBM29DL800TA/BA User Bus Operations Tables (BYTE = V
IH
and BYTE = V
IL
)" in
s
DEVICE BUS OPERATION.)
The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and
device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command
sequence into the register and then Autoselect command should be written into the bank to be read.
If the software (program code) for Autoselect command is stored into the Frash memory, the device and
manufacture codes should be read from the other bank where is not contain the software.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
18
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two "unlock" write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit),
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See "Hardware
Sequence Flags Table".) Therefore, the devices require that a valid address to the devices be supplied by the
system at this particular instance of time. Hence, Data Polling must be performed at the memory location which
is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only
erase operations can convert "0"s to "1"s.
"(1) Embedded Program
TM
Algorithm" in
s
FLOW CHART illustrates the Embedded Program
TM
Algorithm using
typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit), or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ
7
is "1" (See Write Operation Status section.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time
All sectors + Chip Program Time (Preprogramming)
"(2) Embedded Erase
TM
Algorithm" in
s
FLOW CHART illustrates the Embedded Erase
TM
Algorithm using typical
command strings and bus operations.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
19
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data=30h) is latched on the rising edge of CE or WE which happens first.
After time-out of 50
s from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on "MBM29DL800TA/BA
Command Definitions Table" in
s
DEVICE BUS OPERATION. This sequence is followed with writes of the Sector
Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must
be less than 50 s otherwise that command will not be accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
after the last Sector Erase command is written. A time-out of 50
s from the rising edge of last CE or WE
whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE
or WE, whichever happens first occurs within the 50
s time-out window the timer is reset. (Monitor DQ
3
to
determine if the sector erase timer window is still open, see section DQ
3
, Sector Erase Timer.) Any command
other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode,
ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in
the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write
Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 21).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit), or
RY/BY.
The sector erase begins after the 50
s time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ
7
is "1" (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)]
Number of Sector
Erase
In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe.
"(2) Embedded Erase
TM
Algorithm" in
s
FLOW CHART illustrates the Embedded Erase
TM
Algorithm using typical
command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
(B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being
erasing or suspending should be set when writting the Erase Suspend or Erase Resume command.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
20
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20
s to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin will be at Hi-Z and the DQ
7
bit will be at logic "1", and DQ
6
will stop toggling. The user must use
the address of the erasing sector for reading DQ
6
and DQ
7
to determine if the erase operation has been
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ
2
to toggle. (See the section on DQ
2
.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ
2
to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ
7
or by the Toggle Bit I
(DQ
6
) which is the same as the regular Program operation. Note that DQ
7
must be read from the Program address
while DQ
6
can be read from any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
Extended Command
(1) Fast Mode
MBM29DL800TA/BA has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also executed
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. The first cycle must contain the bank address. (Refer to "(8) Embedded Program
TM
Algorithm for
Fast Mode" in
s
FLOW CHART Extended algorithm.) The V
CC
active current is required even CE = V
IH
during
Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to
"(8) Embedded Program
TM
Algorithm for Fast Mode" in
s
FLOW CHART Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29DL800TA/BA has Extended Sector Protection as extended
function. This function enable to protect sector by forcing V
ID
on RESET pin and write a commnad sequence.
Unlike conventional procedure, it is not necessary to force V
ID
and control timing for control pins. The only
RESET pin requires V
ID
for sector protection in this mode. The extended sector protect requires V
ID
on RESET
pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command
register. Then, the sector addresses pins (A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and A
12
) and (A
6
, A
1
, A
0
) = (0, 1, 0) should
be set to the sector to be protected (recommend to set V
IL
for the other addresses pins), and write extended
sector protect command (60h). A sector is typically protected in 250
s. To verify programming of the
protection circuitry, the sector addresses pins (A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and A
12
) and (A
6
, A
1
, A
0
) = (0, 1, 0)
should be set and write a command (40h). Following the command write, a logical "1" at device output DQ
0
will produce for protected sector in the read operation. If the output data is logical "0", please repeat to write
extended sector protect command (60h) again. To terminate the operation, it is necessary to set RESET pin
to V
IH
.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
21
Write Operation Status
Detailed in "Hardware Sequence Flags Table" are all the status flags that can determine the status of the bank
for the current mode operation. The read operation from the bank where is not operate Embedded Algorithm
returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is
completed properly. The information on DQ
2
is address sensitive. This means that if an address from an erasing
sector is consectively read, then the DQ
2
bit will toggle. However, DQ
2
will not toggle if an address from a non-
erasing sector is consectively read. This allows the user to determine which sectors are erasing and which are not.
The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there
is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>,
[2] <non-busy bank>, [3] <busy bank>, the DQ
6
is toggling in the case of [1] and [3]. In case of [2], the data of
memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ
6
will not be toggled
in the [1] and [3].
In the erase suspend read mode, DQ
2
is toggled in the [1] and [3]. In case of [2], the data of memory cell is
outputted.
*1 : Successive reads from the erasing or erase-suspend sector cause DQ
2
to toggle.
*2 : Reading from non-erase suspend sector address indicates logic "1" at the DQ
2
bit.
Hardware Sequence Flags Table
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle*
1
Erase
Suspended
Mode
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
0
0
1*
2
Exceeded
Time Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
22
DQ
7
Data Polling
The MBM29DL800TA/BA devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ
7
. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded
Erase Algorithm, an attempt to read the device will produce a "0" at the DQ
7
output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ
7
output. The flowchart
for Data Polling (DQ
7
) is shown in "(3) Data Polling Algorithm" in
s
FLOW CHART.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ
7
is active for approximately 1
s, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
7
is active for approximately 100
s, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the MBM29DL800TA/BA data pins (DQ
7
)
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ
7
at one instant of time and then that byte's valid data at the next instant of time.
Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See "Hardware Sequence Flags Table".)
See "(6) AC Waveforms for Data Polling during Embedded Algorithm Operations" in
s
TIMING DIAGRAM for the
Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The MBM29DL800TA/BA also feature the "Toggle Bit I" as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2
s and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 s
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ
6
to toggle.
The system can use DQ
6
to determine whether a sector is actively erasing or is erase-suspended. When a bank
is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ
6
toggles. When a bank enters the
Erase Suspend mode, DQ
6
stops toggling. Successive read cycles during the erase-suspend-program cause
DQ
6
to toggle.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
23
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See "(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations" in
s
TIMING DIAGRAM for the
Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a "1". This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in "MBM29DL800TA/BA User Bus
Operations Tables (BYTE = V
IH
and BYTE = V
IL
)" (in
s
DEVICE BUS OPERATION).
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the devices have exceeded timing limits, the
DQ
5
bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low ("0"), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
3
prior to and following each subsequent Sector Erase command. If DQ
3
were high on
the second status check, the command may not have been accepted.
See "Hardware Sequence Flags Table".
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic "1" at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
For example, DQ
2
and DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
(DQ
2
toggles while DQ
6
does not.) See also "Hardware Sequence Flags Table" and "(16) DQ
2
vs. DQ
6
" in
s
TIMING
DIAGRAM.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
24
Reading Toggle Bits DQ
6
/DQ
2
Whenever the system initially begins reading toggle bit status, it must read DQ
7
to DQ
0
at least twice in a row
to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation.
The system can read array data on DQ
7
to DQ
0
on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
5
is high (see "the section on DQ
5
") . If it is the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
5
has not
gone high. The system may continue to monitor the toggle bit and DQ
5
through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine
the status of the operation (See "(4) Toggle bit algorithm" in
s
FLOW CHART) .
Toggle Bit Status Table
*1 : Successive reads from the erasing or erase-suspend sector cause DQ
2
to toggle.
*2 : Reading from non-erase suspend sector address indicates logic "1" at the DQ
2
bit.
RY/BY
Ready/Busy
The MBM29DL800TA/BA provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL800TA/BA are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to "(8) RY/BY Timing Diagram during Program/Erase
Operations" and "(9) RESET/RY/BY Timing Diagram" in
s
TIMING DIAGRAM for a detailed timing diagram. The
RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
CC
; multiples of devices may
be connected to the host system via more than one RY/BY pin in parallel.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL800TA/BA devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle*
1
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle
1*
2
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
25
to DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to "(10) Timing Diagram for Word Mode Configuration" and "(11) Timing Diagram for Byte Mode Configuration"
and "(12) BYTE Timing Diagram for Write Operations" in
s
TIMING DIAGRAM for the timing diagram.
Data Protection
The MBM29DL800TA/BA are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse "Glitch" Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Protection
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressed to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see "Sector Protection" in
s
FUNCTIONAL DESCRIPTION)
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
26
s
s
s
s
ABSOLUTE MAXIMUM RATINGS
*1 : Voltage is defined on the basis of V
SS
=
GND
=
0 V.
*2 : Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, input or I/O pins may undershoot
V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V
CC
+0.5 V. During voltage
transitions, input or I/O pins may overshoot to V
CC
+2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A
9
, OE and RESET pins is 0.5 V. During voltage transitions, A
9
, OE and RESET
pins may undershoot V
SS
to 2.0 V for periods of up to 20 ns. Voltage difference between input and supply
voltage (V
IN
-
V
CC
) does not exceed
+
9.0 V. Maximum DC input voltage on A
9
, OE and RESET pins is +13.0 V
which may overshoot to
+
14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s
s
s
s
RECOMMENDED OPERATING CONDITIONS
* : Voltage is defined on the basis of V
SS
=
GND
=
0 V.
Note: Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Rating
Unit
Min
Max
Storage Temperature
Tstg
55
+125
C
Ambient Temperature with Power Applied
T
A
40
+85
C
Voltage with respect to Ground All pins except A
9
,
OE, RESET *
2
V
IN
, V
OUT
0.5
V
CC
+0.5
V
A
9
, OE, and RESET *
1
, *
3
V
IN
0.5
+13.0
V
Power Supply Voltage*
1
V
CC
0.5
+5.5
V
Parameter
Symbol
Part No.
Value
Unit
Min
Max
Ambient Temperature
T
A
40
+85
C
Power Supply Voltages*
V
CC
-70
+3.0
+3.6
V
-90
+2.7
+3.6
V
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
27
s
s
s
s
MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+0.6 V
0.5 V
20 ns
2.0 V
20 ns
20 ns
Figure 1 Maximum Undershoot Waveform
V
CC
+0.5 V
+2.0 V
V
CC
+2.0 V
20 ns
20 ns
20 ns
Figure 2 Maximum Overshoot Waveform 1
+13.0 V
V
CC
+0.5 V
+14.0 V
20 ns
20 ns
20 ns
Note : This waveform is applied for A
9
, OE, and RESET.
Figure 3 Maximum Overshoot Waveform 2
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
28
s
s
s
s
DC CHARACTERISTICS
*1 : The I
CC
current listed includes both the DC operating current and the frequency dependent component.
*2 : I
CC
active while Embedded Algorithm (program or erase) is in progress.
*3 : This timing is only for Sector Protection operation and Autoselect mode.
*4 : Applicable for only V
CC
applying.
*5 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*6 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)
Parameter
Symbol
Conditions
Value
Unit
Min
Typ
Max
Input Leakage Current
I
LI
V
IN
= V
SS
to V
CC
, V
CC
= V
CC
Max
1.0
+1.0
A
Output Leakage Current
I
LO
V
OUT
= V
SS
to V
CC
, V
CC
= V
CC
Max
1.0
+1.0
A
A
9
, OE, RESET Inputs Leakage
Current
I
LIT
V
CC
= V
CC
Max
A
9
, OE, RESET = 12.5 V
--
35
A
V
CC
Active Current *
1
I
CC1
CE = V
IL
, OE = V
IH
,
f=10 MHz
Byte
--
18
mA
Word
20
CE = V
IL
, OE = V
IH
,
f=5 MHz
Byte
--
8
mA
Word
10
V
CC
Active Current *
2
I
CC2
CE = V
IL
, OE = V
IH
--
35
mA
V
CC
Current (Standby)
I
CC3
V
CC
= V
CC
Max, CE = V
CC
0.3 V,
RESET = V
CC
0.3 V
--
1
5
A
V
CC
Current (Standby, Reset)
I
CC4
V
CC
= V
CC
Max,
RESET = V
SS
0.3 V
--
1
5
A
V
CC
Current
(Automatic Sleep Mode) *
5
I
CC5
V
CC
= V
CC
Max, CE = V
SS
0.3 V,
RESET = V
CC
0.3 V
V
IN
= V
CC
0.3 V or V
SS
0.3 V
--
1
5
A
V
CC
Active Current *
6
(Read-While-Program)
I
CC6
CE = V
IL
, OE = V
IH
Byte
--
45
mA
Word
--
45
V
CC
Active Current *
6
(Read-While-Erase)
I
CC7
CE = V
IL
, OE = V
IH
Byte
--
45
mA
Word
--
45
V
CC
Active Current
(Erase-Suspend-Program)
I
CC8
CE = V
IL
, OE = V
IH
--
35
mA
Input Low Voltage
V
IL
--
0.5
0.6
V
Input High Voltage
V
IH
--
2.0
V
CC
+0.3
V
Voltage for Autoselect and Sector
Protection (A
9
, OE, RESET) *
3,
*
4
V
ID
--
11.5
12
12.5
V
Output Low Voltage
V
OL
I
OL
= 4.0 mA, V
CC
= V
CC
Min
--
0.45
V
Output High Voltage
V
OH1
I
OH
= 2.0 mA, V
CC
= V
CC
Min
2.4
--
V
V
OH2
I
OH
= 100
A
V
CC
0.4
--
V
Low V
CC
Lock-Out Voltage
V
LKO
--
2.3
2.4
2.5
V
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
29
s
s
s
s
AC CHARACTERISTICS
Read Only Operations Characteristics
Note: Test Conditions:
Output Load: 1TTL gate and 30 pF (MBM29DL800TA/BA-70)
1TTL gate and 100 pF (MBM29DL800TA/BA-90
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
Parameter
Symbols
Test
Setup
Value (Note)
Unit
-70
-90
JEDEC
Standard
Min
Max
Min
Max
Read Cycle Time
t
AVAV
t
RC
--
70
--
90
--
ns
Address to Output Delay
t
AVQV
t
ACC
CE = V
IL
OE = V
IL
--
70
--
90
ns
Chip Enable to Output Delay
t
ELQV
t
CE
OE = V
IL
--
90
--
90
ns
Output Enable to Output Delay
t
GLQV
t
OE
--
--
30
--
35
ns
Chip Enable to Output High-Z
t
EHQZ
t
DF
--
--
25
--
30
ns
Output Enable to Output High-Z
t
GHQZ
t
DF
--
--
25
--
30
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
t
AXQX
t
OH
--
0
--
0
--
ns
RESET Pin Low to Read Mode
--
t
READY
--
--
20
--
20
s
CE to BYTE Switching Low or High
--
t
ELFL
t
ELFH
--
--
5
--
5
ns
C
L
3.3 V
Diodes = IN3064
or Equivalent
2.7 k
Device
Under
Test
IN3064
or Equivalent
6.2 k
Notes: C
L
= 30 pF including jig capacitance (MBM29DL800TA/BA-70)
C
L
= 100 pF including jig capacitance (MBM29DL800TA/BA-90)
Figure 4 Test Conditions
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
30
Write/Erase/Program Operations
(Continued)
Parameter
Symbol
Value
Unit
-70
-90
JEDEC
Standard
Min
Typ
Max
Min
Typ
Max
Write Cycle Time
t
AVAV
t
WC
70
--
--
90
--
--
ns
Address Setup Time
t
AVWL
t
AS
0
--
--
0
--
--
ns
Address Setup Time to OE Low During
Toggle Bit Polling
--
t
ASO
15
--
--
15
--
--
ns
Address Hold Time
t
WLAX
t
AH
45
--
--
45
--
--
ns
Address Hold Time from CE or OE High
During Toggle Bit Polling
--
t
AHT
0
--
--
0
--
--
ns
Data Setup Time
t
DVWH
t
DS
35
--
--
45
--
--
ns
Data Hold Time
t
WHDX
t
DH
0
--
--
0
--
--
ns
Output Enable
Hold Time
Read
--
t
OEH
0
--
--
0
--
--
ns
Toggle and Data Polling
10
--
--
10
--
--
ns
CE High During Toggle Bit Polling
--
t
CEPH
20
--
--
20
--
--
ns
OE High During Toggle Bit Polling
--
t
OEPH
20
--
--
20
--
--
ns
Read Recover Time Before Write
t
GHWL
t
GHWL
0
--
--
0
--
--
ns
Read Recover Time Before Write
t
GHEL
t
GHEL
0
--
--
0
--
--
ns
CE Setup Time
t
ELWL
t
CS
0
--
--
0
--
--
ns
WE Setup Time
t
WLEL
t
WS
0
--
--
0
--
--
ns
CE Hold Time
t
WHEH
t
CH
0
--
--
0
--
--
ns
WE Hold Time
t
EHWH
t
WH
0
--
--
0
--
--
ns
Write Pulse Width
t
WLWH
t
WP
35
--
--
45
--
--
ns
CE Pulse Width
t
ELEH
t
CP
35
--
--
45
--
--
ns
Write Pulse Width High
t
WHWL
t
WPH
25
--
--
25
--
--
ns
CE Pulse Width High
t
EHEL
t
CPH
25
--
--
25
--
--
ns
Programming Operation
Byte
t
WHWH1
t
WHWH1
--
8
--
--
8
--
s
Word
--
16
--
--
16
--
s
Sector Erase Operation *
1
t
WHWH2
t
WHWH2
--
1
--
--
1
--
s
V
CC
Setup Time
--
t
VCS
50
--
--
50
--
--
s
Rise Time to V
ID
*
2
--
t
VIDR
500
--
--
500
--
--
ns
Voltage Transition Time *
2
--
t
VLHT
4
--
--
4
--
--
s
Write Pulse Width *
2
--
t
WPP
100
--
--
100
--
--
s
OE Setup Time to WE Active *
2
--
t
OESP
4
--
--
4
--
--
s
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
31
(Continued)
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Protection operation.
Parameter
Symbol
Value
Unit
-70
-90
JEDEC
Standard
Min
Typ
Max
Min
Typ
Max
CE Setup Time to WE Active *
2
--
t
CSP
4
--
--
4
--
--
s
Recover Time From RY/BY
--
t
RB
0
--
--
0
--
--
ns
RESET Pulse Width
--
t
RP
500
--
--
500
--
--
ns
RESET Hold Time Before Read
--
t
RH
200
--
--
200
--
--
ns
BYTE Switching Low to Output High-Z
--
t
FLQZ
--
--
25
--
--
30
ns
BYTE Switching High to Output Active
--
t
FHQV
--
70
--
90
ns
Program/Erase Valid to RY/BY Delay
--
t
BUSY
--
--
90
--
--
90
ns
Delay Time from Embedded Output Enable
--
t
EOE
--
--
70
--
--
90
ns
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
32
s
ERASE AND PROGRAMMING PERFORMANCE
s
TSOP(1) PIN CAPACITANCE
Notes :
Test conditions T
A
=
+
25C, f = 1.0 MHz
DQ
15
/A-
1
pin capacitance is stipulated by output capacitance.
s
FBGA PIN CAPACITANCE
Notes :
Test conditions T
A
=
+
25C, f = 1.0 MHz
DQ
15
/A-
1
pin capacitance is stipulated by output capacitance.
Parameter
Limits
Unit
Comments
Min
Typ
Max
Sector Erase Time
--
1
10
s
Excludes programming time
prior to erasure
Word Programming Time
--
16
360
s
Excludes system-level
overhead
Byte Programming Time
--
8
300
s
Chip Programming Time
--
8.4
25
s
Excludes system-level
overhead
Program/Erase Cycle
100,000
--
--
cycle
--
Parameter
Symbol
Test Setup
Value
Unit
Typ
Max
Input Capacitance
C
IN
V
IN
= 0
6
7.5
pF
Output Capacitance
C
OUT
V
OUT
= 0
8.5
12
pF
Control Pin Capacitance
C
IN2
V
IN
= 0
8
10
pF
Parameter
Symbol
Test Setup
Value
Unit
Typ
Max
Input Capacitance
C
IN
V
IN
= 0
6
7.5
pF
Output Capacitance
C
OUT
V
OUT
= 0
8.5
12
pF
Control Pin Capacitance
C
IN2
V
IN
= 0
8
10
pF
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
33
s
s
s
s
TIMING DIAGRAM
Key to Switching Waveforms
(1) AC Waveforms for Read Operations
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
"H" or "L"
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center Line is
High-
Impedance
"Off" State
WE
OE
CE
t
ACC
t
DF
t
CE
t
OE
Outputs
t
RC
Address
Address Stable
High-Z
Output Valid
High-Z
t
OEH
t
OH
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
34
(2) AC Waveforms for Hardware Reset/Read Operations
(3) Alternate WE Controlled Program Operations
RESET
t
ACC
t
OH
Outputs
t
RC
Address
Address Stable
High-Z
Output Valid
t
RH
CE
t
RP
t
RH
t
CE
t
CH
t
WP
t
WHWH1
t
WC
t
AH
CE
OE
t
RC
Address
Data
t
AS
t
OE
t
WPH
t
GHWL
t
DH
DQ
7
PD
A0h
D
OUT
WE
555h
PA
PA
t
OH
Data Polling
3rd Bus Cycle
t
CS
t
CE
t
DS
D
OUT
t
DF
Notes:
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the
16 mode. The addresses differ from
8 mode.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
35
(4) Alternate CE Controlled Program Operations
t
CP
t
DS
t
WHWH1
t
WC
t
AH
WE
OE
Address
Data
t
AS
t
CPH
t
DH
DQ
7
A0h
D
OUT
CE
555h
PA
PA
Data Polling
3rd Bus Cycle
t
WS
t
WH
t
GHEL
PD
Notes:
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the
16 mode. (The addresses differ from
8 mode.)
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
36
(5) AC Waveforms Chip/Sector Erase Operations
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
Note : These waveforms are for the
16 mode. The addresses differ from
8 mode.
V
CC
CE
OE
Address
Data
t
WP
WE
555h
2AAh
555h
555h
2AAh
SA*
t
DS
t
CH
t
AS
t
AH
t
CS
t
WPH
t
DH
t
GHWL
t
VCS
t
WC
55h
55h
80h
AAh
AAh
10h/
30h
10h for chip Erase
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
37
(6) AC Waveforms for Data Polling during Embedded Algorithm Operations
t
OEH
t
OE
t
WHWH1 or 2
CE
OE
t
EOE
t
BUSY
WE
Data
t
DF
t
CH
t
CE
High-Z
High-Z
DQ
7
=
Valid Data
DQ
0
to DQ
6
Valid Data
DQ
7
*
DQ
7
DQ
0
to DQ
6
RY/BY
Data
DQ
0
to DQ
6
= Output Flag
* : DQ
7
= Valid Data (The device has completed the Embedded operation).
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
38
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
t
DH
t
OE
t
CE
CE
WE
OE
DQ
6
/DQ
2
Address
RY/BY
Data
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggling
Output
Valid
*
t
BUSY
t
OEH
t
OEH
t
OEPH
t
AHT
t
AHT
t
ASO
t
AS
t
CEPH
* : DQ
6
stops toggling (The device has completed the Embedded operation).
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
39
(8) RY/BY Timing Diagram during Program/Erase Operations
(9) RESET/RY/BY Timing Diagram
Rising edge of the last WE pulse
CE
RY/BY
WE
t
BUSY
Entire programming
or erase operations
t
RP
RESET
t
READY
RY/BY
WE
t
RB
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
40
(10) Timing Diagram for Word Mode Configuration
(11) Timing Diagram for Byte Mode Configuration
(12) BYTE Timing Diagram for Write Operations
DQ
15
CE
BYTE
DQ
14 to
DQ
0
DQ
15
/A
-
1
t
ELFH
t
FHQV
t
CE
A
-
1
Data Output
(DQ
7
to DQ
0
)
Data Output
(DQ
14
to DQ
0
)
CE
BYTE
DQ
14
to DQ
0
DQ
15
/A
-
1
t
ELFL
t
ACC
t
FLQZ
DQ
15
A
-
1
Data Output
(DQ
14
to DQ
0
)
Data Output
(DQ
7
to DQ
0
)
Falling edge of the last WE signal
CE or WE
t
AH
t
AS
Input
Valid
BYTE
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
41
(13) AC Waveforms for Sector Protection
t
VLHT
SPAX
A
18
, A
17
, A
16
A
15
, A
14
A
13
, A
12
SPAY
A
0
A
6
A
9
V
ID
V
IH
t
VLHT
OE
V
ID
V
IH
t
VLHT
t
VLHT
t
OESP
t
WPP
t
CSP
WE
CE
t
OE
01h
Data
V
CC
A
1
t
VCS
SPAX:Sector Address for initial sector
SPAY: Sector Address for next sector
Note : A
-1
is V
IL
on byte mode.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
42
(14) Temporary Sector Unprotection Timing Diagram
(15) Bank-to-bank Read/Write Timing Diagram
V
IH
RESET
V
CC
CE
WE
RY/BY
t
VLHT
Program or Erase Command Sequence
t
VLHT
t
VCS
t
VIDR
V
ID
t
VLHT
Unprotection period
Note
DQ
2
is read from the erase-suspended sector.
CE
DQ
WE
Address
BA1
BA1
BA1
BA2
(555H)
BA2
(PA)
BA2
(PA)
OE
Valid
Output
Valid
Output
Valid
Output
Status
Valid
Intput
Valid
Intput
t
RC
t
RC
t
RC
t
RC
t
WC
t
WC
t
AHT
t
AS
t
AS
t
AH
t
ACC
t
CE
t
OE
t
OEH
t
WP
t
GHWL
t
DS
t
DF
t
DH
t
DF
t
CEPH
Read
Command
Command
Read
Read
Read
(A0H)
(PD)
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address corresponding of Bank 1.
BA2: Address corresponding of Bank 2.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
43
(16) DQ
2
vs. DQ
6
DQ
2
*
DQ
6
WE
Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase
Erase
Complete
Toggle
DQ
2
and DQ
6
with OE or CE
* : DQ
2
is read from the erase-suspended sector.
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
44
(17) Extended Sector Protection Timing Diagram
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 250
s (Min)
SPAY
RESET
A
6
OE
WE
CE
Data
A
1
V
CC
A
0
Address
SPAX
SPAX
60h
01h
40h
60h
60h
TIME-OUT
t
VCS
t
VLHT
t
VIDR
t
OE
t
WP
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
45
s
s
s
s
FLOW CHART
(1) Embedded Program
TM
Algorithm
No
Yes
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Write Program
Command Sequence
(See below)
Data Polling
Increment Address
Last Address
?
Program Address/Program Data
Start
Programming Completed
Verify Data
?
No
Yes
Embedded
Program
Algorithm
in program
EMBEDDED ALGORITHM
Notes :
The sequence is applied for
16 mode.
The addresses differ from
8 mode.
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46
(2) Embedded Erase
TM
Algorithm
555h/AAh
2AAh/55h
555h/AAh
555h/80h
555h/10h
2AAh/55h
555h/AAh
2AAh/55h
555h/AAh
555h/80h
2AAh/55h
Additional sector
erase commands
are optional.
Write Erase
Command Sequece
(See below)
Data Polling
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Sector Address/30h
Sector Address/30h
Sector Address/30h
Erasure Completed
Start
Data = FFh
?
No
Yes
Embedded
Erase
Algorithm
in program
EMBEDDED ALGORITHM
Notes :
The sequence is applied for
16 mode.
The addresses differ from
8 mode.
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47
(3) Data Polling Algorithm
DQ
7
= Data?
*
No
No
DQ
7
= Data?
DQ
5
= 1?
Yes
Yes
No
Read Byte
(DQ
7
to DQ
0
)
Addr. = VA
Read Byte
(DQ
7
to DQ
0
)
Addr. = VA
Yes
Start
Fail
Pass
* : DQ
7
is rechecked even if DQ
5
= "1" because DQ
7
may change simultaneously with DQ
5
.
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase operation
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48
(4) Toggle Bit Algorithm
DQ
6
= Toggle
?
Yes
No
DQ
6
= Toggle
?
DQ
5
= 1?
Yes
No
No
Yes
Read DQ
7
to DQ
0
Twice
Addr. = VA
Read DQ
7
to DQ
0
Addr. = VA
Start
Program/Erase
Operation
Complete
Program/Erase
Operation Not
Complete. Write
Reset Command
Read DQ
7
to DQ
0
Addr. = VA
*1
*1, *2
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ
5
changes to "1".
VA = Bank address being executed
Embedded Algorithm.
MB
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49
(5) Sector Protection Algorithm
Setup Sector Addr.
(A
18
, A
17
, A
16
, A
15
, A
14
, A
13
, A
12
)
Activate WE Pulse
WE = V
IH
, CE = OE = V
IL
(A
9
should remain V
ID
)
Yes
Yes
No
No
OE = V
ID
, A
9
= V
ID
,
CE = V
IL
, RESET = V
IH
A
6
= A
0
= V
IL
, A
1
= V
IH
PLSCNT = 1
Time out 100
s
Read from Sector
Addr. = SPA, A
1
= V
IH
,
A
6
= A
0
= V
IL
Remove V
ID
from A
9
Write Reset Command
Increment PLSCNT
No
Yes
Protect Another Sector?
Data = 01h?
PLSCNT = 25?
Device Failed
Remove V
ID
from A
9
Write Reset Command
Start
Sector Protection
Completed
(
)
*
* : A
-1
is V
IL
on byte mode.
MB
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50
(6) Temporary Sector Unprotection Algorithm
RESET = V
ID
*1
Perform Erase or
Program Operations
RESET = V
IH
Start
Temporary Sector
Unprotection Completed
*2
*1 : All protected sectors are unprotected.
*2 : All previously protected sectors are protected once again.
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51
(7) Extended Sector Protection Algorithm
To Sector Protection
Yes
No
No
PLSCNT = 1
No
Yes
Protection Other Sector
Start
Sector Protection
Extended Sector
PLSCNT = 25?
Device Failed
Remove V
ID
from RESET
Completed
Remove
V
ID
from RESET
Write Reset Command
Write Reset Command
RESET = V
ID
Wait to 4
s
Protection Entry?
To Setup Sector Protection
Write XXXh/60h
Write SPA/60h
(A
0
= V
IL
, A
1
= V
IH
, A
6
= V
IL
)
Time Out 250
s
To Verify Sector Protection
Write SPA/40h
(A
0
= V
IL
, A
1
= V
IH
, A
6
= V
IL
)
Data = 01h?
?
Device is Operating in
Temporary Sector
Read from Sector Address
(A
0
= V
IL
, A
1
= V
IH
, A
6
= V
IL
)
Increment PLSCNT
Setup Next Sector Address
No
Yes
Yes
Unprotection Mode
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52
(8) Embedded Program
TM
Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
XXXh/A0h
555h/20h
Verify Data?
No
Program Address/Program Data
Data Polling
Last Address
?
Programming Completed
(BA)
XXXh/90h
XXXh/F0h
Increment Address
No
Yes
Yes
Set Fast Mode
In Fast Program
Reset Fast Mode
Notes :
The sequence is applied for
16 mode.
The addresses differ from
8 mode.
MB
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/MBM29DL800BA
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53
s
ORDERING INFORMATION
Part No.
Package
Access Time
Sector Architecture
MBM29DL800TA-70PFTN
MBM29DL800TA-90PFTN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
70
90
Top Sector
MBM29DL800TA-70PFTR
MBM29DL800TA-90PFTR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
70
90
MBM29DL800TA-70PBT
MBM29DL800TA-90PBT
48-pin plastic FBGA
(BGA-48P-M12)
70
90
MBM29DL800BA-70PFTN
MBM29DL800BA-90PFTN
48-pin plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
70
90
Bottom Sector
MBM29DL800BA-70PFTR
MBM29DL800BA-90PFTR
48-pin plastic TSOP (1)
(FPT-48P-M20)
(Reverse Bend)
70
90
MBM29DL800BA-70PBT
MBM29DL800BA-90PBT
48-pin plastic FBGA
(BGA-48P-M12)
70
90
MBM29DL800
T
A
-70
PFTN
DEVICE NUMBER/DESCRIPTION
MBM29DL800
8Mega-bit (1M
8-Bit or 512 K
16-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Bend
PBT-SF2 =48-Ball Fine Pitch Ball Grid Array
Package (FBGA:BGA-48P-M12)
SPEED OPTION
See Product Selector Guide.
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
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54
s
s
s
s
PACKAGE DIMENSIONS
(Continued)
48-pin plastic TSOP (1)
(FPT-48P-M19)
Note1 : * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are
+
0.15 (.006) Max (each side) .
Note2 : Pins width and pins thickness include plating thickness.
Dimensions in mm (inches)
48-pin plastic TSOP (1)
(FPT-48P-M20)
Note1 : * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are
+
0.15 (.006) Max (each side) .
Note2 : Pins width and pins thickness include plating thickness.
Dimensions in mm (inches)
.003
+.001
0.08
+0.03
.007
0.17
"A"
(Stand off height)
0.10(.004)
(Mounting
height)
(.472.008)
12.000.20
*
*
LEAD No.
48
25
24
1
(.004
.002)
0.10(.004)
M
1.10
+0.10
0.05
+.004
.002
.043
0.10
0.05
(.009
.002)
0.220.05
TYP
0.50(.020)
(.787
.008)
20.000.20
(.724
.008)
18.400.20
INDEX
2002 FUJITSU LIMITED F48029S-c-5-6
C
0~8
0.25(.010)
0.60
0.15
(.024
.006)
Details of "A" part
.003
+.001
.007
0.08
+0.03
0.17
"A"
(Stand off height)
(.004
.002)
0.10
0.05
0.10(.004)
(Mounting height)
12.000.20(.472.008)
*
*
LEAD No.
48
25
24
1
0.10(.004)
M
1.10
+0.10
0.05
+.004
.002
.043
(.009
.002)
0.22
0.05
TYP
0.50(.020)
(.787
.008)
20.00
0.20
(.724
.008)
18.40
0.20
INDEX
2002 FUJITSU LIMITED F48030S-c-5-6
C
0~8
0.25(.010)
0.600.15
(.024.006)
Details of "A" part
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55
(Continued)
48-pin plastic FBGA
(BGA-48P-M12)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED B48012S-c-3-3
9.000.20(.354.008)
0.380.10(.015.004)
(Stand off)
(Mounting height)
6.000.20
(.236.008)
0.10(.004)
0.80(.031)TYP
5.60(.220)
4.00(.157)
48-0.450.10
(48-.018.004)
M
0.08(.003)
INDEX
H
G
F
E
D
C
B
A
6
5
4
3
2
1
C0.25(.010)
.041
.004
+.006
0.10
+0.15
1.05
MB
M29DL800TA
-70/90
/MBM29DL800BA
-70/90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0211
FUJITSU LIMITED Printed in Japan
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