DS05-20842-4E

FUJITSU SEMICONDUCTOR

DATA SHEET

Embedded EraseTM, Embedded ProgramTM and ExpressFlashTM are trademarks of Advanced Micro Devices, Inc.

FLASH MEMORY

CMOS

4M (512K

8) BIT

MBM29F040C

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FEATURES

Single 5.0 V read, program and erase
Minimizes system level power requirements

Compatible with JEDEC-standard commands
Uses same software commands as E

PROMs

Compatible with JEDEC-standard byte-wide pinouts
32-pin PLCC (Package suffix: PD)
32-pin TSOP(I) (Package suffix: PF)
32-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)

Minimum 100,000 write/erase cycles

High performance
55 ns maximum access time

Sector erase architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase.

Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector

Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address

Data Polling and Toggle Bit feature for detection of program or erase cycle completion

Low V

write inhibit

3.2 V

Sector protection
Hardware method disables any combination of sectors from write or erase operations

Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device

MBM29F040C

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GENERAL DESCRIPTION

The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The
MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be
programmed in-system with the standard system 5.0 V V

supply. A 12.0 V V

is not required for write or erase

operations. The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29F040C offers access times 55 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.

The MBM29F040C is pin and command set compatible with JEDEC standard E

PROMs. Commands are written

to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 12.0 V Flash or EPROM devices.

The MBM29F040C is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell
margin.

Any individual sector is typically erased and verified in 1 second. (If already completely preprogrammed.)

The device also features a sector erase architecture. The sector mode allows for 64K byte sectors of memory
to be erased and reprogrammed without affecting other sectors. The MBM29F040C is erased when shipped
from the factory.

The device features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

or by the Toggle Bit feature on DQ

. Once the end of a program or erase cycle has been completed, the device

internally resets to the read mode.

Fujitsu's Flash technology combines years of EPROM and E

PROM experience to produce the highest levels

of quality, reliability and cost effectiveness. The MBM29F040C memory electrically erases the entire chip or all
bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot electron injection.

MBM29F040C

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CONNECTION DIAGRAMS

WE
V

OE
A

CE
DQ

WE
A

CE
A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

MBM29F040C

Standard Pinout

MBM29F040C

Reverse Pinout

TSOP (I)

PLCC

LCC-32P-M02

FPT-32P-M24

FPT-32P-M25

Marking Side

MBM29F040C

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LOGIC SYMBOL

Legend: L = V

, H = V

, X = V

or V

= Pulse Input. See DC Characteristics for voltage levels.

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 5.

2. Refer to the section on Sector Protection.
3. WE can be V

if OE is V

, OE at V

initiates the write operations.

Table 1 MBM29F040C Pin Configuration

Pin

Function

to A

Address Inputs

to DQ

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Device Ground

Device Power Supply

Table 2 MBM29F040C User Bus Operations

Operation

I/O

Auto-Select Manufacturer Code (1)

Code

Auto-Select Device Code (1)

Code

Read (3)

OUT

Standby

HIGH-Z

Output Disable

HIGH-Z

Write (Program/Erase)

Enable Sector Protection (2)

Verify Sector Protection (2)

Code

to A

to DQ

MBM29F040C

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FUNCTIONAL DESCRIPTION

Read Mode

The MBM29F040C has two control functions which must be satisfied in order to obtain data at the outputs. CE
is the power control and should be used for a device selection. OE is the output control and should be used to
gate data to the output pins if a device is selected.

Address access time (t

ACC

) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the
addresses have been stable for at least t

ACC

-t

time).

Standby Mode

The MBM29F040C has two standby modes, a CMOS standby mode (CE input held at V

±0.3 V.), when the

current consumed is less than 5 µA; and a TTL standby mode (CE is held at V

) when the current required is

reduced to approximately 1 mA. During Embedded Algorithm operation, V

Active current (I

CC2

) is required even

CE = V

. The device can be read with standard access time (t

) from either of these standby modes. In the

standby mode the outputs are in a high impedance state, independent of the OE input.

If the device is deselected during erasure or programming, the device will draw active current until the operation
is completed.

Output Disable

With the OE input at a logic high level (V

), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.

To activate this mode, the programming equipment must force V

(11.5 V to 12.5 V) on address pin A

. Two

identifier bytes may then be sequenced from the device outputs by toggling address A

from V

to V

. All

addresses are DON'T CARES except A

, A

, and A

. (Recommend V

for the other pins.)

The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F040C is erased or programmed in a system without access to high voltage on the A

pin. The command

sequence is illustrated in Table 5. (Refer to Autoselect Command section.)

Byte 0 (A

= V

) represents the manufacture's code (Fujitsu = 04H) and byte 1 (A

= V

) represents the device

identifier code (MBM29F040C = A4H). These two bytes are given in the Table 3. All identifiers for manufactures
and device will exhibit odd parity with the MSB (DQ

) defined as the parity bit. In order to read the proper device

codes when executing the autoselect, A

must be V

. (See Table 3.)

MBM29F040C

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* : Outputs 01H at protected sector addresses and 00H at unprotected sector addresses.

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V

, while CE is at V

and OE is at V

. Addresses are latched on

the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Protection

The MBM29F040C features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 8). The sector protection feature is enabled using programming
equipment at the user's site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V

on address pin A

and control pin OE, (suggest

= 11.5 V) and CE = V

. The sector addresses (A

, A

and A

) should be set to the sector to be protected.

Table 4 defines the sector address for each of the eight (8) individual sectors. Programming of the protection
circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector
addresses must be held constant during the WE pulse. See figures 11 and 17 sector protection waveforms and
algorithm.

Table 3 MBM29F040C Sector Protection Verify Autoselect Codes

Type

Code

(HEX) DQ

Manufacture's
Code

04H

Device Code

A4H

Sector
Protection

Sector

Addresses

01H*

Table 4 Sector Address Tables

Sector Address

Address Range

SA0

00000H to 0FFFFH

SA1

10000H to 1FFFFH

SA2

20000H to 2FFFFH

SA3

30000H to 3FFFFH

SA4

40000H to 4FFFFH

SA5

50000H to 5FFFFH

SA6

60000H to 6FFFFH

SA7

70000H to 7FFFFH

MBM29F040C

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To verify programming of the protection circuitry, the programming equipment must force V

on address pin A

with CE and OE at V

and WE at V

. Scanning the sector addresses (A

, A

and A

) while (A

, A

) = (0,

1, 0) will produce a logical "1" code at device output DQ

for a protected sector. Otherwise the device will read

00H for unprotected sector. In this mode, the lower order addresses, except for A

, A

and A

are DON'T CARES.

Address locations with A

= V

are reserved for Autoselect manufacturer and device codes.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A

, A

and A

) are the

sector address will produce a logical "1" at DQ

for a protected sector. See Table 3 for Autoselect codes.

Notes: 1. Address bits A

to A

= X = "H" or "L" for all address commands except for Program Address (PA) and

Sector Address (SA).

2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the

WE pulse.

SA = Address of the sector to be erased. The combination of A

, A

, and A

will uniquely select any

sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.

*: Either of the two reset commands will reset the device.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to read
mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase
Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both Read/
Reset Commands are functionally equivalent, resetting the device to the read mode.

Table 5 MBM29F040C Command Definitions

Command

Sequence

Read/Reset

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset*

XXXH F0H

Read/Reset*

555H

AAH

2AAH

55H

555H

F0H

Autoselect

555H

AAH

2AAH

55H

555H

90H

Byte Program

555H

AAH

2AAH

55H

555H

A0H

Chip Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

10H

Sector Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

30H

Sector Erase Suspend

Erase can be suspended during sector erase with Addr ("H" or "L"). Data (B0H)

Sector Erase Resume

Erase can be resumed after suspend with Addr ("H" or "L"). Data (30H)

MBM29F040C

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Read/Reset Command

The read or reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.

The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A

to a high voltage (V

= 11.5 V to 12.5). However,

multiplexing high voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H returns the device code A4H. (see Table 3.) All manufacturer and device codes will
exhibit odd parity with the MSB (DQ

) defined as the parity bit.

Sector state (protection or unprotection) will be informed address XX02H.
Scanning the sector addresses (A

, A

) while (A

, A

) = (0, 1, 0) will produce a logical "1" at device

output DQ

for a protected sector. The programming verification should be perform margin mode on the protected

sector. (See Table 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.

Byte Programming

The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycles. These are followed by the program setup command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ

is equivalent to data written to this

bit (See Write Operation Status section.) at which time the device returns to the read mode and addresses are
no longer latched. (See Table 6, Hardware Sequence Flags.) Therefore, the device requires that a valid address
to the device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed
at the memory location which is being programmed.

Any commands written to the chip during this period will be ignored.

Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device (Exceed timing limits.), or result
in an apparent success according to the data polling algorithm but a read from reset/read mode will show that
the data is still "0". Only erase operations can convert "0"s to "1"s.

Figure 13 illustrates the Embedded Program

Algorithm using typical command strings and bus operations.

MBM29F040C

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Chip Erase

Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ

is "1" (see Write Operation Status section.) at which time the device returns to read the

mode.

Figure 14 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector
address (Any address location within the desired sector.) is latched on the falling edge of WE, while the command
(Data = 30H) is latched on the rising edge of WE. A time-out of 50 µs from the rising edge of the last sector
erase command will initiate the sector erase command(s).

Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less than 50 µs, otherwise that command will not be
accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the
rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of
the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ

to determine if the sector erase

timer window is still open, see section DQ

, Sector Erase Timer.) Any command other than Sector Erase or

Erase Suspend during this time-out period will reset the device to read mode, ignoring the previous command
string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart
the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector
Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of
sectors (1 to 7).

Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ

is "1" (See Write Operation Status section.)

at which time the device returns to read mode. During the execution of the Sector Erase command, only the
Erase Suspend and Erase Resume commands are allowed. All other commands will reset the device to read
mode. Data polling must be performed at an address within any of the sectors being erased.

Figure 14 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

MBM29F040C

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Erase Suspend

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which include the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.

Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command.
Writing the Erase Resume command resumes the erase operation. The addresses are "DON'T CARES" when
writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 10

s to suspend the erase operation. When the devices have entered the erase-suspended mode, the DQ

bit will be at logic "1", and DQ

will stop toggling. The user must use the address of the erasing sector for reading

and DQ

to determine if the erase operation has been suspended. Further writes of the Erase Suspend

command are ignored.

When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ

to toggle. (See the section on DQ

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ

to toggle. The end of the erase-

suspended Program operation is detected by Data polling of DQ

, or by the Toggle Bit I (DQ

) which is the same

as the regular Program operation. Note that DQ

must be read from the Program address while DQ

can be read

from any address.

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.

MBM29F040C

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Write Operation Status

Notes: 1. Performing successive read operations from any address will cause DQ

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic

"1" at the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ

to toggle.

3. DQ

and DQ

are reserve pins for future use. DQ

is for Fujitsu internal use only.

Data Polling

The MBM29F040C device features Data Polling as a method to indicate to the host that the Embedded Algorithms
are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce
the compliment of the data last written to DQ

. Upon completion of the Embedded Program Algorithm, an attempt

to read the device will produce the true data last written to DQ

. During the Embedded Erase Algorithm, an

attempt to read the device will produce a "0" at the DQ

output. Upon completion of the Embedded Erase Algorithm

an attempt to read the device will produce a "1" at the DQ

output. The flowchart for Data Polling (DQ

) is shown

in Figure 15.

For chip erase, and sector erase the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to
being completed, the MBM29F040C data pins (DQ

) may change asynchronously while the output enable (OE)

is asserted low. This means that the device is driving status information on DQ

at one instant of time and then

that byte's valid data at the next instant of time. Depending on when the system samples the DQ

output, it may

read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ

has

a valid data, the data outputs on DQ

to DQ

may be still invalid. The valid data on DQ

to DQ

will be read on

the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out. (See Table 6.)

See Figure 9 for the Data Polling timing specifications and diagrams.

Table 6 Hardware Sequence Flags

Status

In Progress

Embedded Program Algorithm

Toggle

Embedded Erase Algorithm

Toggle

Erase
Suspended
Mode

Erase Suspend Read
(Erase Suspended Sector)

Toggle

Erase Suspend Read
(Non-Erase Suspended Sector)

Data

Erase Suspend Program
Non-Erase Suspended Sector)

Toggle

(Note 1)

(Note 2)

Exceeded
Time Limits

Embedded Program Algorithm

Toggle

Program/Erase in Embedded Erase Algorithm

Toggle

N/A

Erase
Suspended
Mode

Erase Suspend Program
(Non-Erase Suspended Sector)

Toggle

N/A

MBM29F040C

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Toggle Bit I

The MBM29F040C also features the "Toggle Bit I" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ

toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ

will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ

to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ

to toggle.

See Figure 10 for the Toggle Bit timing specifications and diagrams.

Exceeded Timing Limits

will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ

will produce a "1". This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling DQ

, DQ

is the only operating function of the device under

this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.

The DQ

failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ

bit and DQ

never stops toggling. Once the device has exceeded timing limits, the

bit will indicate a "1." Please note that this is not a device failure condition since the device was incorrectly

used. If this occurs, reset the device with command sequence.

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ

will

remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command. DQ

may

be used to determine if the sector erase timer window is still open. If DQ

is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ

is low ("0"), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ

prior to and following each subsequent sector erase command. If DQ

were high on the

second status check, the command may not have been accepted.

Refer to Table 6: Hardware Sequence Flags.

MBM29F040C

-55/-70/-90

Toggle Bit II

This Toggle Bit II, along with DQ

, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ

to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ

to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic "1" at the DQ

bit.

is different from DQ

in that DQ

toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ

, is summarized

as follows:

Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended.

2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector.

Data Protection

The MBM29F040C is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting form V

power-up

and power-down transitions or system noise.

Low V

Write Inhibit

To avoid initiation of a write cycle during V

power-up and power-down, a write cycle is locked out for V

less

than 3.2 V (typically 3.7 V). If V

< V

LKO

, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored
until the V

level is greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = V

, CE = V

, or WE = V

. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Mode

Program

toggles

Erase

toggles

Erase Suspend Read
(Erase-Suspended Sector)
(Note 1)

toggles

Erase Suspend Program

(Note 2)

toggles

1 (Note 2)

MBM29F040C

-55/-70/-90

ABSOLUTE MAXIMUM RATINGS

Storage Temperature .................................................................................... 55°C to +125°C
Ambient Temperature with Power Applied .................................................... 40°C to +85°C
Voltage with Respect to Ground All pins except A

, OE (Note 1).................. 2.0 V to +7.0 V

(Note 1) .................................................................................................. 2.0 V to +7.0 V

, OE (Note 2) ............................................................................................. 2.0 V to +13.5 V

Notes: 1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, inputs may negative

overshoot V

to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is V

+0.5 V. During voltage transitions, outputs may positive overshoot to V

+2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A

and OE pins are 0.5 V. During voltage transitions, A

and OE pins may

negative overshoot V

to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A

and OE

pins are +13.5 V which may overshoot to 14.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING RANGES

Ambient Temperature (T

) ................................................................................ 40°C to +85°C

Supply Voltages

MBM29F040C-55.......................................................................................... +4.75 V to +5.25 V
MBM29F040C-70/-90 ................................................................................... +4.50 V to +5.50 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

MBM29F040C

-55/-70/-90

DC CHARACTERISTICS

Notes: 1. The I

current listed includes both the DC operating current and the frequency dependent component

(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at V

2. I

active while Embedded Algorithm (program or erase) is in progress.

3. Applicable to sector protection function.
4. (V

) do not exceed 9 V.

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Max.

Unit

Input Leakage Current

= V

to V

, V

= V

Max

±1.0

µA

Output Leakage Current

OUT

= V

to V

, V

= V

Max

±1.0

µA

LIT

, OE Input Leakage Current

= V

Max., A

, OE = 12.0 V

µA

CC1

Active Current (Note 1)

CE = V

, OE = V

CC2

Active Current (Note 2)

CE = V

, OE = V

CC3

Current (Standby)

= V

Max., CE = V

= V

Max., CE = V

±0.3 V

µA

Input Low Level

0.5

0.8

Input High Level

2.0

+0.3

Voltage for Autoselect and Sector
Protection (A

, OE) (Note 3, 4)

= 5.0 V

11.5

12.5

Output Low Voltage Level

= 12.0 mA, V

= V

Min

0.45

OH1

Output High Voltage Level

= 2.5 mA, V

= V

Min

2.4

OH2

= 100 µA

0.4

LKO

Low V

Lock-Out Voltage

3.2

4.2

MBM29F040C

-55/-70/-90

AC CHARACTERISTICS

Read Only Operations Characteristics

Note: 1. Test Conditions:

Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to3.0 V
Timing measurement reference level

Input: 1.5 V
Output: 1.5 V

Parameter

Symbols

Description

Test Setup

-55

(Note1)

-70

(Note2)

-90

(Note2)

Unit

JEDEC

Standard

AVAV

Read Cycle Time

Min.

AVQV

ACC

Address to Output Delay

CE = V

OE = V

Max.

ELQV

Chip Enable to Output Delay

OE = V

Max.

GLQV

Output Enable to Output Delay

Max.

EHQZ

Chip Enable to Output HIGH-Z

Max.

GHQZ

Output Enable to Output HIGH-Z

Max.

AXQX

Output Hold Time From
Addresses,
CE or OE, Whichever Occurs First

Min.

Figure 4 Test Conditions

5.0 V

Diodes = IN3064

or Equivalent

2.7 k

Device

Under

Test

IN3064

or Equivalent

6.2 k

Note: 1.C

= 30 pF including jig capacitance

2.C

= 100 pF including jig capacitance

Note: 2. Test Conditions:

Oput Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level
Input: 0.8 and 2.0 V
Output: 0.8 and 2.0 V

MBM29F040C

-55/-70/-90

Write/Erase/Program Operations

Notes: 1. This does not include the preprogramming time.

2. This timing is only for Sector Protect operations.

Parameter Symbols

Description

MBM29F040C

Unit

JEDEC

Standard

-55

-70

-90

AVAV

Write Cycle Time

Min.

AVWL

Address Setup Time

Min.

WLAX

Address Hold Time

Min.

DVWH

Data Setup Time

Min.

WHDX

Data Hold Time

Min.

OES

Output Enable Setup Time

Min.

OEH

Output Enable
Hold Time

Read

Min.

Toggle and Data Polling

Min.

GHWL

Read Recover Time Before Write

Min.

GHEL

Read Recover Time Before Write

Min.

ELWL

CE Setup Time

Min.

WLEL

WE Setup Time

Min.

WHEH

CE Hold Time

Min.

EHWH

WE Hold Time

Min.

WLWH

Write Pulse Width

Min.

ELEH

CE Pulse Width

Min.

WHWL

WPH

Write Pulse Width High

Min.

EHEL

CPH

CE Pulse Width High

Min.

WHWH1

Byte Programming Operation

Typ.

µs

WHWH2

Sector Erase Operation (Note 1)

Typ.

sec

Max.

sec

VCS

Setup Time

Min.

µs

VLHT

Voltage Transition Time (Notes 2)

Min.

µs

WPP

Write Pulse Width (Note 2)

Min.

100

µs

OESP

OE Setup Time to WE Active (Note 2)

Min.

µs

CSP

CE Setup Time to WE Active (Note 2)

Min.

µs

EOE

Delay Time from Embedded Output Enable

Max.

MBM29F040C

-55/-70/-90

ERASE AND PROGRAMMING PERFORMANCE

TSOP(I) PIN CAPACITANCE

Note: Test conditions T

= 25°C, f = 1.0 MHz

PLCC PIN CAPACITANCE

Note: Test conditions T

= 25°C, f = 1.0 MHz

Parameter

Limits

Unit

Comments

Min.

Typ.

Max.

Sector Erase Time

sec

Excludes 00H programming
prior to erasure

Byte Programming Time

150

µs

Excludes system-level
overhead

Chip Programming Time

4.2

sec

Excludes system-level
overhead

Erase/Program Cycle

100,000

cycles

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Control Pin Capacitance

= 0

8.5

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Control Pin Capacitance

= 0

8.5

MBM29F040C

-55/-70/-90

FUJITSU LIMITED

For further information please contact:

Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608
Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220

http://www.fmap.com.sg/

F9903

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have an inhereut chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.

Document Outline

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Document Outline

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