DS05-20850-4E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
8M (1M
8) BIT
MBM29F080A
-55/-70/-90
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GENERAL DESCRIPTION
The MBM29F080A is a 8 M-bit, 5.0 V-Only Flash memory organized as 1 M bytes of 8 bits each. The 1 M bytes
of data is divided into 16 sectors of 64 K bytes for flexible erase capability. The 8 bit of data will appear on DQ
0
to DQ
7
. The MBM29F080A is offered in a 48-pin TSOP(I), 40-pin TSOP, and 44-pin SOP packages. This device
is designed to be programmed in-system with the standard system 5.0 V V
CC
supply. A 12.0 V V
PP
is not required
for program or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F080A offers access times between 55 ns and 90 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F080A is command set compatible with JEDEC standard E
2
PROMs. Commands are written to the
command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 12.0 V Flash or EPROM devices.
The MBM29F080A is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished
by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal
algorithm that automatically preprograms the array if it is not already programmed before executing the erase
operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
(Continued)
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PRODUCT LINE UP
Part No.
MBM29F080A
Ordering Part No.
V
CC
= 5.0 V 5%
-55
--
--
V
CC
= 5.0 V 10%
--
-70
-90
Max Address Access Time (ns)
55
70
90
Max CE Access Time (ns)
55
70
90
Max OE Access Time (ns)
30
30
40
MBM29F080A
-55/-70/-90
2
(Continued)
This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to
be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1
second (if already completely preprogrammed). The MBM29F080A is erased when shipped from the factory.
The MBM29F080A device also features hardware sector group protection. This feature will disable both program
and erase operations in any combination of eight sector groups of memory.
A sector group consists of four
adjacent sectors grouped in the following pattern: sectors 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, and 14-15.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.
The device features single 5.0 V power supply operation for both read and program functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of
DQ
7
, or by the Toggle Bit I feature on DQ
6
or RY/BY output pin. Once the end of a program or erase cycle has
been completed, the device automatically resets to the read mode.
The MBM29F080A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into
the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs
during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read
mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu's Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F080A memory electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
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FEATURES
Single 5.0 V read, write, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
40-pin TSOP(I) (Package Suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
44-pin SOP (Package Suffix: PF)
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
Sector erase architecture
Uniform sectors of 64 K bytes each
Any combination of sectors can be erased. Also supports full chip erase.
Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded ProgramTM Algorithms
Automatically programs and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Low V
CC
write inhibit
3.2 V
(Continued)
MBM29F080A
-55/-70/-90
3
(Continued)
Hardware RESET pin
Resets internal state machine to the read mode
Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
Sector group protection
Hardware method that disables any combination of sector groups from write or erase operation (a sector group
consists of 2 adjacent sectors of 64 K bytes each)
Temporary sector groups unprotection
Temporary sector unprotection via the RESET pin
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PACKAGES
40-pin plastic TSOP(1)
(FPT-40P-M06)
40-pin plastic TSOP(1)
(FPT-40P-M07)
Marking Side
Marking Side
48-pin plastic TSOP(1)
(FPT-48P-M19)
48-pin plastic TSOP(1)
(FPT-48P-M20)
Marking Side
Marking Side
44-pin plastic SOP
(FPT-44P-M16)
MBM29F080A
-55/-70/-90
4
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PIN ASSIGNMENTS
(Continued)
A
19
A
18
A
17
A
16
A
15
A
14
RESET
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
N.C.
OE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
44
43
42
41
MBM29F080A
Normal Bend
TSOP(I)
FPT-48P-M19
(Marking Side)
A
13
A
12
CE
V
CC
N.C.
17
18
19
20
36
35
34
33
40
39
38
37
V
SS
V
SS
V
CC
RY/BY
WE
N.C.
21
22
23
24
48
47
46
45
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
19
A
18
A
17
A
16
A
15
A
14
RESET
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
N.C.
OE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
41
42
43
44
45
46
47
48
29
30
31
32
MBM29F080A
Reverse Bend
FPT-48P-M20
(Marking Side)
A
13
A
12
CE
V
CC
N.C.
8
7
6
5
37
38
39
40
33
34
35
36
V
SS
V
SS
V
CC
RY/BY
WE
N.C.
4
3
2
1
25
26
27
28
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
MBM29F080A
-55/-70/-90
5
(Continued)
Pin Name
Function
A
19
to A
0
Address Inputs
DQ
0
to DQ
7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Sector Protection Unlock
N.C.
No Internal Connection
V
SS
Device Ground
V
CC
Device Power Supply (5.0 V 10%)
A
19
A
18
A
17
A
16
A
15
A
14
RESET
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
N.C.
OE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
12
A
15
A
16
A
18
V
CC
CE
A
17
A
14
A
13
A
8
A
9
A
10
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
WE
N.C.
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
34
35
36
21
22
23
24
25
26
27
28
29
30
31
32
MBM29F080A
Normal Bend
MBM29F080A
Reverse Bend
TSOP(I)
FPT-40P-M06
FPT-40P-M07
Marking Side
Marking Side
A
13
A
12
CE
V
CC
N.C.
17
18
19
20
36
35
34
33
40
39
38
37
V
SS
V
SS
V
CC
RY/BY
WE
N.C.
A
11
RESET
N.C.
A
19
20
19
18
17
37
38
39
40
V
SS
V
CC
RY/BY
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
44
43
42
41
36
35
34
33
40
39
38
37
27
26
25
24
23
RESET
N.C.
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
N.C.
N.C.
SOP
FPT-44P-M16
V
CC
CE
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
N.C.
N.C.
N.C.
N.C.
WE
OE
RY/BY
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
A
0
A
1
A
2
A
3
DQ
3
DQ
2
DQ
1
DQ
0
V
SS
V
SS
(Top View)
MBM29F080A
-55/-70/-90
6
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LOGIC SYMBOL
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BLOCK DIAGRAM
20
A
19
to A
0
WE
OE
CE
DQ
7
to DQ
0
8
RESET
RY/BY
V
SS
V
CC
WE
CE
A
19
to A
0
OE
Erase Voltage
Generator
DQ
7
to DQ
0
State
Control
Command
Register
Program Voltage
Generator
Low V
CC
Detector
Address
Latch
X-Decoder
Y-Decoder
Cell Matrix
Y-Gating
Chip Enable
Output Enable
Logic
Data Latch
Input/Output
Buffers
STB
STB
Timer for
RESET
RY/BY
Buffer
RY/BY
Program/Erase
MBM29F080A
-55/-70/-90
7
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FLEXIBLE SECTOR-ERASE ARCHITECTURE
MBM29F080A User Bus Operations Table
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
,
= Pulse Input. See DC Characteristics for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
"MBM29F080A Command Definitions Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE".
*2 : Refer to the section on Sector Group Protection.
*3 : WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
MBM29F080A Sector Protection Verify Autoselect Codes Table
* : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
Operation
CE
OE
WE
A
0
A
1
A
6
A
9
DQ
0
to DQ
7
RESET
Auto-Select Manufacturer Code *
1
L
L
H
L
L
L
V
ID
Code
H
Auto-Select Device Code *
1
L
L
H
H
L
L
V
ID
Code
H
Read *
3
L
L
H
A
0
A
1
A
6
A
9
D
OUT
H
Standby
H
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
A
0
A
1
A
6
A
9
D
IN
H
Enable Sector Group Protection *
2
L
V
ID
X
X
X
V
ID
X
H
Verify Sector Group Protection *
2
L
L
H
L
H
L
V
ID
Code
H
Temporary Sector Group Unprotection
X
X
X
X
X
X
X
X
V
ID
Reset (Hardware)
X
X
X
X
X
X
X
High-Z
L
Type
A
17
to A
19
A
6
A
1
A
0
Code
(HEX) DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacture's
Code
X
X
X
V
IL
V
IL
V
IL
04h
0
0
0
0
0
1
0
0
Device Code
X
X
X
V
IL
V
IL
V
IH
D5h
1
0
1
0
1
1
0
1
Sector Group
Protection
Sector Group
Addresses
V
IL
V
IH
V
IL
01h*
0
0
0
0
0
0
0
1
MBM29F080A
-55/-70/-90
8
Sector Address Table
Sector Group Addresses Table
A
19
A
18
A
17
A
16
Address Range
SA0
0
0
0
0
000000h to 00FFFFh
SA1
0
0
0
1
010000h to 01FFFFh
SA2
0
0
1
0
020000h to 02FFFFh
SA3
0
0
1
1
030000h to 03FFFFh
SA4
0
1
0
0
040000h to 04FFFFh
SA5
0
1
0
1
050000h to 05FFFFh
SA6
0
1
1
0
060000h to 06FFFFh
SA7
0
1
1
1
070000h to 07FFFFh
SA8
1
0
0
0
080000h to 08FFFFh
SA9
1
0
0
1
090000h to 09FFFFh
SA10
1
0
1
0
0A0000h to 0AFFFFh
SA11
1
0
1
1
0B0000h to 0BFFFFh
SA12
1
1
0
0
0C0000h to 0CFFFFh
SA13
1
1
0
1
0D0000h to 0DFFFFh
SA14
1
1
1
0
0E0000h to 0EFFFFh
SA15
1
1
1
1
0F0000h to 0FFFFFh
A
19
A
18
A
17
Sectors
SGA0
0
0
0
SA0 to SA1
SGA1
0
0
1
SA2 to SA3
SGA2
0
1
0
SA4 to SA5
SGA3
0
1
1
SA6 to SA7
SGA4
1
0
0
SA8 to SA9
SGA5
1
0
1
SA10 to SA11
SGA6
1
1
0
SA12 to SA13
SGA7
1
1
1
SA14 to SA15
MBM29F080A
-55/-70/-90
9
MBM29F080A Command Definitions Table
Notes :
Address bits A
11
to A
19
=
X
=
"H" or "L" for all address commands except or Program Address (PA) and
Sector Address (SA).
Bus operations are defined in "MBM29F080A User Bus Operations Table" in "
s
FLEXIBLE SECTOR-
ERASE ARCHITECTURE".
RA
=
Address of the memory location to be read.
PA
=
Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA
=
Address of the sector to be erased. The combination of A
19
, A
18
, A
17
, and A
16
will uniquely select
any sector.
RD
=
Data read from location RA during read operation.
PD
=
Data to be programmed at location PA. Data is latched on the rising edge of WE.
Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.
The system should generate the following address pattens: 555h or 2AAh to addresses A
0
to A
10
.
The command combinations not described in "MBM29F080A Command Definitions Table" in "
s
FLEXIBLE
SECTOR-ERASE ARCHITECTURE" are illegal.
*1: Either of the two reset commands will reset the device.
*2: The fourth bus cycle is only for read.
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr. Data Addr. Data Addr. Data Addr.
Data Addr. Data Addr. Data
Read/Reset*
1
1
XXXh F0h
--
--
--
--
--
--
--
--
--
--
Reset/Read*
1
3
555h
AAh
2AAh
55h
555h
F0h
RA*
2
RD*
2
--
--
--
--
Manufacture Code
3
555h
AAh
2AAh
55h
555h
90h
00h*
2
04h*
2
--
--
--
--
Device Code
3
555h
AAh
2AAh
55h
555h
90h
01h*
2
05h*
2
--
--
--
--
Byte Program
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
--
--
--
--
Chip Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Sector Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
SA
30h
Sector Erase Suspend
Erase can be suspended during sector erase with Addr ("H" or "L"), Data (B0h)
Sector Erase Resume
Erase can be resumed after suspend with Addr ("H" or "L"), Data (30h)
MBM29F080A
-55/-70/-90
10
Thirty two 64 K byte sectors
8 sector groups each of which consists of 2
adjacent sectors in the following pattern;
sectors 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13,
and 14-15
Individual-sector or multiple-sector erase
capability
Sector group protection is user-definable
0FFFFFh
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
000000h
SA15
SA14
Sector
Group 7
Sector
Group 0
64 K byte
64 K byte
16 Sectors Total
64 K byte
64 K byte
SA1
SA0
MBM29F080A
-55/-70/-90
11
s
s
s
s
FUNCTIONAL DESCRIPTION
Read Mode
The MBM29F080A has two control functions which must be satisfied in order to obtain data at the outputs. CE
is the power control and should be used for a device selection. OE is the output control and should be used to
gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the
addresses have been stable for at least t
ACC
-t
OE
time).
Standby Mode
There are two ways to implement the standby mode on the MBM29F080A device, one using both the CE and
RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
0.3 V.
Under this condition the current consumed is less than 5
A. A TTL standby mode is achieved with CE and
RESET pins held at V
IH
. Under this condition the current is reduced to approximately 1 mA. During Embedded
Algorithm operation, V
CC
Active current (I
CC2
) is required even CE = V
IH
. The device can be read with standard
access time (t
CE
) from either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
0.3 V
(CE = "H" or "L"). Under this condition the current consumed is less than 5
A. A TTL standby mode is achieved
with RESET pin held at V
IL
(CE = "H" or "L"). Under this condition the current required is reduced to approximately
1 mA. Once the RESET pin is taken high, the device requires 500 ns of wake up time before outputs are valid
for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(11.5 V to 12.5 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the device outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are don't cares except A
0
, A
1
, and A
6
. (See "MBM29F080A Sector Protection Verify Autoselect Codes
Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE".)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F080A is erased or programmed in a system without access to high voltage on the A
9
pin. The command
sequence is illustrated in "MBM29F080A Command Definitions Table" in "
s
FLEXIBLE SECTOR-ERASE AR-
CHITECTURE". (Refer to Autoselect Command section.)
Byte 0 (A
0
= V
IL
) represents the manufacturer's code (Fujitsu = 04h) and byte 1 (A
0
= V
IH
) represents the device
identifier code for MBM29F080A = D5h. These two bytes are given in the "MBM29F080A Sector Protection
Verify Autoselect Codes Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE". All identifiers for
manufactures and device will exhibit odd parity with DQ
7
defined as the parity bit. In order to read the proper
device codes when executing the Autoselect, A
1
must be V
IL
. (See "MBM29F080A Sector Protection Verify
Autoselect Codes Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE".)
MBM29F080A
-55/-70/-90
12
The Autoselect mode also facilitates the determination of sector group protection in the system. By performing
a read operation at the address location XX02h with the higher order address bits A
17
, A
18
and A
19
set to the
desired sector group address, the device will return 01h for a protected sector group and 00h for a non-protected
sector group.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The MBM29F080A features hardware sector group protection. This feature will disable both program and erase
operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent
sectors grouped in the following pattern: sectors
0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, and 14-15
(see "Sector
Group Address Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE"). The sector group protection feature
is enabled using programming equipment at the user's site. The device is shipped with all sector groups
unprotected.
To activate this mode, the programming equipment must force V
ID
on address pin A
9
and control pin OE, (suggest
V
ID
= 11.5 V), CE = V
IL
. The sector addresses (A
19
, A
18
, and A
17
) should be set to the sector to be protected.
"Sector Address Table" and "Sector Group Address Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE"
define the sector address for each of the thirty two (16) individual sectors, and the sector group address for each
of the eight (8) individual group sectors. Programming of the protection circuitry begins on the falling edge of
the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during
the WE pulse. See "Temporary Sector Group Unprotection Timing Diagram" in "
s
TIMING DIAGRAM" and
"Temporary Sector Group Unprotection Algorithm" in "
s
FLOW CHART" for sector protection waveforms and
algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector addresses (A
19
, A
18
, and A
17
) while (A
6
, A
1
, A
0
) = (0,
1, 0) will produce a logical "1" code at device output DQ
0
for a protected sector. Otherwise the device will produce
00h for unprotected sector. In this mode, the lower order addresses, except for A
0
, A
1
, and A
6
are DON'T CARES.
Address locations with A
1
= V
IL
are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses (A
19
, A
18
, and
A
17
) are the desired sector group address will produce a logical "1" at DQ
0
for a protected sector group. See
"MBM29F080A Sector Protection Verify Autoselect Codes Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITEC-
TURE" for Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29F080A device
in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high
voltage (12 V). During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sector
MBM29F080A
-55/-70/-90
13
groups will be protected again. Refer to "Temporary Sector Group Unprotection Timing Diagram" in "
s
TIMING
DIAGRAM" and "Temporary Sector Group Unprotection Algorithm" in "
s
FLOW CHART".
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to the
read mode. "MBM29F080A Command Definitions Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE"
defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h)
commands are valid only while the Sector Erase operation is in progress. Moreover, both Read/Reset commands
are functionally equivalent, resetting the device to the read mode.
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desirable system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h returns the device code D5h. (See "MBM29F080A Sector Protection Verify Autoselect
Codes Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE").
All manufacturer and device codes will exhibit odd parity with the DQ
7
defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02h.
Scanning the sector group addresses (A
17
, A
18
, A
19
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical "1" at
device output DQ
0
for a protected sector group.
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is
not
required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
MBM29F080A
-55/-70/-90
14
This automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See "Hardware
Sequence Flags Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE".) Therefore, the device requires
that a valid address to the device be supplied by the system at this particular instance of time. Data Polling must
be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from reset/read mode will show that the data is still "0". Only
erase operations can convert "0"s to "1"s.
"Embedded Program
TM
Algorithm" in "
s
FLOW CHART" illustrates the Embedded Programming
TM
Algorithm
using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase does
not
require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is "1" (see Write Operation Status section) at which time the device returns to read the
mode.
"Embedded Erase
TM
Algorithm" in "
s
FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30h) is latched on the rising edge of WE. After time-out of 50
s from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on "MBM29F080A Command
Definitions Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE". This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50
s otherwise that command will not be accepted and erasure will start. It is
recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts
can be re-enabled after the last Sector Erase command is written. A time-out of 50
s from the rising edge of
the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs
within the 50
s time-out window the timer is reset. (Monitor DQ
3
to determine if the sector erase timer window
is still open, see section DQ
3
, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend
during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting
the device once execution has begun will corrupt the data in that sector. In that case, restart the erase on those
sectors and allow them to complete. (Refer to the Write Operation Status section for DQ
3
, Sector Erase Timer
operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 15).
MBM29F080A
-55/-70/-90
15
Sector erase does
not
require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is
not
required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50
s time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ
7
is "1" (see Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased.
"Embedded Erase
TM
Algorithm" in "
s
FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during a Sector Erase operation
which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written
during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation.
Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command.
Writing the Erase Resume command resumes the erase operation. The addresses are DON'T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 15
s to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY
output pin and the DQ
7
bit will be at logic "1", and DQ
6
will stop toggling. The user must use the address of the
erasing sector for reading DQ
6
and DQ
7
to determine if the erase operation has been suspended. Further writes
of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ
2
to toggle. (See the section on DQ
2
.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Byte Program. This program mode is known as the erase-suspend-program mode.
Again, programming in this mode is the same as programming in the regular Byte Program mode except that
the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-
suspended sector while the device is in the erase-suspend-program mode will cause DQ
2
to toggle. The end of
the erase-suspended program operation is detected by the RY/BY output pin, Data polling of DQ
7
, or by the
Toggle Bit I (DQ
6
) which is the same as the regular Byte Program operation. Note that DQ
7
must be read from
the Byte Program address while DQ
6
can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
MBM29F080A
-55/-70/-90
16
Write Operation Status
*1 : Performing successive read operations from the erase-suspended sector will cause DQ
2
to toggle.
*2 : Performing successive read operations from any address will cause DQ
6
to toggle.
*3 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1"
at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to toggle.
DQ
7
Data Polling
The MBM29F080A device features Data Polling as a method to indicate to the host that the embedded algorithms
are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will
produce the complement of the data last written to DQ
7
. Upon completion of the Embedded Program Algorithm,
an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded EraseTM
Algorithm, an attempt to read the device will produce a "0" at the DQ
7
output. Upon completion of the Embedded
Erase Algorithm an attempt to read the device will produce a "1" at the DQ
7
output. The flowchart for Data Polling
(DQ
7
) is shown in "Data Polling Algorithm" in "
s
FLOW CHART".
Data polling will also flag the entry into Erase Suspend. DQ
7
will switch "0" to "1" at the start of the Erase Suspend
mode. Please note that the address of an erasing sector must be applied in order to observe DQ
7
in the Erase
Suspend Mode.
During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside
of the suspend mode.
For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.
For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling
must be performed at sector address within any of the sectors being erased and not a sector that is within a
protected sector group. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operation DQ
7
may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ
7
at one instant of
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations
and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will
be read on the successive read attempts.
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase Sus-
pended
Mode
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle*
1
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle*
2
0
0
1*
3
Exceeded
Time Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A
MBM29F080A
-55/-70/-90
17
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See "Hardware Sequence
Flags Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE".)
See "AC Waveforms for Data Polling during Embedded Algorithm Operations" in "
s
TIMING DIAGRAM" for the
Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The MBM29F080A also features the "Toggle Bit I" as a method to indicate to the host system that the embedded
algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device
at any address
will result in DQ
6
toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ
6
will stop toggling and valid data will be read on
the next
successive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth
WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of
the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out.
In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2
s and then
stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for
the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100
s and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause DQ
6
to toggle.
See "AC Waveforms for Toggle Bit I during Embedded Algorithm Operations" in "
s
TIMING DIAGRAM" for the
Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a "1". This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ
7
, DQ
6
is the only operating function of the device under
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in "MBM29F080A User Bus
Operations Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE".
The DQ
5
failure condition may also appear if a user tries to program a 1 to a location that is previously programmed
to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the
system never reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the device has exceeded timing
limits, the DQ
5
bit will indicate a "1." Please note that this is not a device failure condition since the device was
incorrectly used. If this occurs, reset the device.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
MBM29F080A
-55/-70/-90
18
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low ("0"),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on the second status check, the command may not have been accepted.
Refer to "Hardware Sequence Flags Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE".
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded EraseTM
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded EraseTM Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic "1" at the DQ
2
bit.
*1 : These status flags apply when outputs are read from a sector that has been erase-suspended.
*2 : These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
For example, DQ
2
and DQ
6
can be used together to determine the erase-suspend-read mode (DQ
2
toggles while
DQ
6
does not). See also "Hardware Sequence Flags Table" in "
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE"
and "DQ
2
vs. DQ
6
" in "
s
TIMING DIAGRAM".
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29F080A provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29F080A is placed in an Erase Suspend mode,
the RY/BY output will be high, by means of connecting with a pull-up resistor to V
CC
.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read *
1
(Erase-Suspended Sector)
1
1
toggles
Erase Suspend Program
DQ
7
*
2
toggles
1 *
2
MBM29F080A
-55/-70/-90
19
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during RESET pulse. Refer to "RY/BY Timing Diagram during Program/Erase Operations" in
"
s
TIMING DIAGRAM" for a detailed timing diagram. The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
RESET
Hardware Reset
The MBM29F080A device may be reset by driving the RESET pin to V
IL
. The RESET pin must be kept low (V
IL
)
for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to
the read mode 20
s after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires t
RH
of wake up time until outputs are valid for read access.
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system's
microprocessor to read the boot-up firmware from the Flash memory.
Data Protection
The MBM29F080A is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 3.2 V (typically 3.7 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 3.2 V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
MBM29F080A
-55/-70/-90
20
s
s
s
s
ABSOLUTE MAXIMUM RATINGS
*1 : Voltage is defined on the basis of V
SS
=
GND
=
0 V.
*2 : Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may underhoot
V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is V
CC
+0.5 V. During voltage
transitions, input or I/O pins may overshoot to V
CC
+2.0 V for periods up to 20 ns.
*3 : Minimum DC input voltage on A
9
, OE, and RESET pins are 0.5 V. During voltage transitions, A
9
, OE, and
RESET pins may undershoot V
SS
to 2.0 V for periods of up to 20 ns. Voltage difference between input and
power supply (V
IN
V
CC
) does not exceed
+
9.0 V. Maximum DC input voltage on A
9
, OE, and RESET are
+13.0 V which may overshoot to
+
14.0 V for periods up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s
s
s
s
RECOMMENDED OPERATING CONDITIONS
* : Voltage is defined on the basis of V
SS
=
GND
=
0 V.
Note : Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Rating
Unit
Min
Max
Storage Temperature
Tstg
-
55
+
125
C
Ambient Temperature with Power Applied
T
A
-
40
+
85
C
Voltage with Respect to Ground All pins except
A
9
, OE, and RESET *
1,
*
2
V
IN
, V
OUT
-
2.0
+
7.0
V
Power Supply Voltage *
1,
*
3
V
CC
-
2.0
+
7.0
V
A
9
, OE, and RESET *
2
V
IN
-
2.0
+
13.5
V
Parameter
Symbol
Value
Unit
Min
Max
Ambient Temperature
MBM29F080A-55
T
A
-
20
+
70
C
MBM29F080A-70/-90
-
40
+
85
C
V
CC
Supply Voltages *
MBM29F080A-55
V
CC
+
4.75
+
5.25
V
MBM29F080A-70/-90
+
4.50
+
5.50
V
MBM29F080A
-55/-70/-90
21
s
s
s
s
MAXIMUM OVERSHOOT / MAXIMUM UNDERSHOOT
1.
Maximum Undershoot Waveform
2.
Maximum Overshoot Waveform 1
3.
Maximum Overshoot Waveform 2
+0.8 V
0.5 V
20 ns
2.0 V
20 ns
20 ns
+2.0 V
V
CC
+0.5 V
20 ns
V
CC
+2.0 V
20 ns
20 ns
V
CC
+0.5 V
+13.0 V
20 ns
+14.0 V
20 ns
20 ns
Note : This waveform is applied for A
9
, OE and RESET.
MBM29F080A
-55/-70/-90
22
s
s
s
s
DC CHARACTERISTICS
*1 : The I
CC
current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at V
IH
.
*2 : I
CC
active while Embedded Algorithm (program or erase) is in progress.
*3 : Applicable to sector protection function.
*4 : (V
ID
V
CC
) do not exceed 9 V.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
= V
SS
to V
CC
, V
CC
= V
CC
Max
--
1.0
A
Output Leakage Current
I
LO
V
OUT
= V
SS
to V
CC
,
V
CC
= V
CC
Max
--
1.0
A
A
9
, OE, RESET Inputs Leakage
Current
I
LIT
V
CC
= V
CC
Max
A
9
, OE, RESET = 12.5 V
--
50
A
V
CC
Active Current *
1
I
CC1
CE = V
IL
, OE = V
IH
--
40
mA
V
CC
Active Current *
2
I
CC2
CE = V
IL
, OE = V
IH
--
45
mA
V
CC
Current (Standby)
I
CC3
V
CC
= V
CC
Max, CE = V
IH
,
RESET = V
IH
--
1
mA
V
CC
= V
CC
Max, CE = V
CC
0.3 V,
RESET = V
CC
0.3 V
--
5
A
V
CC
Current (Standby, Reset)
I
CC4
V
CC
= V
CC
Max,
RESET = V
IL
--
1
mA
V
CC
= V
CC
Max,
RESET = V
SS
0.3 V
--
5
A
Input Low Level
V
IL
--
0.5
0.8
V
Input High Level
V
IH
--
2.0
V
CC
+0.5
V
Voltage for Autoselect and Sector
Protection (A
9
, OE, RESET) *
3,
*
4
V
ID
--
11.5
12.5
V
Output Low Voltage Level
V
OL
I
OL
= 12.0 mA, V
CC
= V
CC
Min
--
0.45
V
Output High Voltage Level
V
OH1
I
OH
= 2.5 mA, V
CC
= V
CC
Min
2.4
--
V
V
OH2
I
OH
= 100
A
V
CC
0.4
--
V
Low V
CC
Lock-Out Voltage
V
LKO
--
3.2
4.2
V
MBM29F080A
-55/-70/-90
23
s
s
s
s
AC CHARACTERISTICS
Read Only Operations Characteristics
*1 : Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
Parameter
Symbol
Test
Setup
-55 *
1
-70 *
2
-90 *
2
Unit
JEDEC Standard
Min Max Min Max
Min
Max
Read Cycle Time
t
AVAV
t
RC
--
55
--
70
--
90
--
ns
Address to Output Delay
t
AVQV
t
ACC
CE = V
IL
OE = V
IL
--
55
--
70
--
90
ns
Chip Enable to Output Delay
t
ELQV
t
CE
OE = V
IL
--
55
--
70
--
90
ns
Output Enable to Output Delay
t
GLQV
t
OE
--
--
30
--
30
--
40
ns
Chip Enable to Output HIGH-Z
t
EHQZ
t
DF
--
--
20
--
20
--
20
ns
Output Enable to Output HIGH-Z
t
GHQZ
t
DF
--
--
20
--
20
--
20
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
t
AXQX
t
OH
--
0
--
0
--
0
--
ns
RESET Pin Low to Read Mode
--
t
READY
--
--
20
--
20
--
20
s
Test Conditions
Notes :
MBM29F080A-55: C
L
= 30 pF including jig capacitance
MBM29F080A-70/-90: C
L
= 100 pF including jig capacitance
C
L
5.0 V
Diode=1N3064
or Equivalent
2.7 k
Device
Under
Test
Diode=1N3064
or Equivalent
6.2 k
*2 : Test Conditions:
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V or 2.4 V
Timing measurement reference level
Input: 0.8 V and 2.0 V
Output: 0.8 V and 2.0 V
MBM29F080A
-55/-70/-90
24
Write/Erase/Program Operations
(Continued)
Description
Symbol
MBM29F080A
Unit
JEDEC Standard
-55
-70
-90
Min Typ Max Min Typ Max Min Typ Max
Write Cycle Time
t
AVAV
t
WC
55
--
--
70
--
--
90
--
--
ns
Address Setup Time
t
AVWL
t
AS
0
--
--
0
--
--
0
--
--
ns
Address Hold Time
t
WLAX
t
AH
40
--
--
45
--
--
45
--
--
ns
Data Setup Time
t
DVWH
t
DS
25
--
--
30
--
--
45
--
--
ns
Data Hold Time
t
WHDX
t
DH
0
--
--
0
--
--
0
--
--
ns
Output Enable Setup Time
--
t
OES
0
--
--
0
--
--
0
--
--
ns
Output
Enable Hold
Time
Read
--
t
OEH
0
--
--
0
--
--
0
--
--
ns
Toggle Bit I and
Data Polling
10
--
--
10
--
--
10
--
--
ns
Read Recover Time Before Write
t
GHWL
t
GHWL
0
--
--
0
--
--
0
--
--
ns
Read Recover Time Before Write
t
GHEL
t
GHEL
0
--
--
0
--
--
0
--
--
ns
CE Setup Time
t
ELWL
t
CS
0
--
--
0
--
--
0
--
--
ns
WE Setup Time
t
WLEL
t
WS
0
--
--
0
--
--
0
--
--
ns
CE Hold Time
t
WHEH
t
CH
0
--
--
0
--
--
0
--
--
ns
WE Hold Time
t
EHWH
t
WH
0
--
--
0
--
--
0
--
--
ns
Write Pulse Width
t
WLWH
t
WP
30
--
--
35
--
--
45
--
--
ns
Write Pulse Width
t
ELEH
t
CP
30
--
--
35
--
--
45
--
--
ns
Write Pulse Width High
t
WHWL
t
WPH
20
--
--
20
--
--
20
--
--
ns
Write Pulse Width High
t
EHEL
t
CPH
20
--
--
20
--
--
20
--
--
ns
Byte Programming Operation
t
WHWH1
t
WHWH1
--
8
--
--
8
--
--
8
--
s
Sector Erase Operation *
1
t
WHWH2
t
WHWH2
--
1
--
--
1
--
--
1
--
s
--
--
8
--
--
8
--
--
8
s
V
CC
Setup Time
--
t
VCS
50
--
--
50
--
--
50
--
--
s
Rise Time to V
ID
--
t
VIDR
500
--
--
500 --
--
500
--
--
ns
Voltage Transition Time *
2
--
t
VLHT
4
--
--
4
--
--
4
--
--
s
Write Pulse Width *
2
--
t
WPP
100
--
--
100 --
--
100
--
--
s
OE Setup Time to WE Active *
2
--
t
OESP
4
--
--
4
--
--
4
--
--
s
CE Setup Time to WE Active *
2
--
t
CSP
4
--
--
4
--
--
4
--
--
s
Recover Time from RY/BY
--
t
RB
0
--
--
0
--
--
0
--
--
ns
MBM29F080A
-55/-70/-90
25
(Continued)
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Protection operation.
s
s
s
s
ERASE AND PROGRAMMING PERFORMANCE
s
TSOP(1) PIN CAPACITANCE
Note : Test conditions T
A
=
+
25C, f = 1.0 MHz
s
SOP PIN CAPACITANCE
Notes :
Sampled, not 100% tested.
Test conditions T
A
=
+
25C, f = 1.0 MHz
Description
Symbol
MBM29F080A
Unit
JEDEC Standard
-55
-70
-90
Min Typ Max
Min Typ Max
Min
Typ Max
RESET Pulse Width
--
t
RP
500 --
--
500
--
--
500
--
--
ns
RESET Hold Time Before Read
--
t
RH
50
--
--
50
--
--
50
--
--
ns
Program/Erase Valid to RY/BY Delay
--
t
BUSY
--
--
55
--
--
70
--
--
90
ns
Delay Time from Embedded Output
Enable
--
t
EOE
--
--
30
--
--
30
--
--
40
ns
Parameter
Limits
Unit
Comments
Min
Typ
Max
Sector Erase Time
--
1
8
s
Excludes 00h programming
prior to erasure
Byte Programming Time
--
8
150
s
Excludes system-level
overhead
Chip Programming Time
--
8.4
20
s
Excludes system-level
overhead
Erase/Program Cycle
100,000
--
--
cycle
Parameter
Symbol
Test Setup
Typ
Max
Unit
Input Capacitance
C
IN
V
IN
= 0
8
10
pF
Output Capacitance
C
OUT
V
OUT
= 0
8
10
pF
Control Pin Capacitance
C
IN2
V
IN
= 0
9
10
pF
Parameter
Symbol
Test Setup
Typ
Max
Unit
Input Capacitance
C
IN
V
IN
= 0
8
10.5
pF
Output Capacitance
C
OUT
V
OUT
= 0
8
10
pF
Control Pin Capacitance
C
IN2
V
IN
= 0
9.5
11
pF
MBM29F080A
-55/-70/-90
26
s
s
s
s
TIMING DIAGRAM
Key to Switching Waveforms
(1) AC Waveforms for Read Operations
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
"H" or "L"
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing,
State
Unknown
Center Line is
High-
Impedance
"Off" State
WE
OE
CE
t
ACC
t
DF
t
CE
t
OE
DQ
7
to DQ
0
t
RC
Address
Address Stable
High-Z
Output Valid
High-Z
t
OEH
t
OH
MBM29F080A
-55/-70/-90
27
(2) AC Waveforms for Read Operations
(3) AC Waveforms for Alternate WE Controlled Program Operations
RESET
t
ACC
t
OH
DQ
7
to DQ
0
t
RC
Address
Address Stable
High-Z
Output Valid
t
RH
t
WP
t
DF
t
DS
t
WHWH1
t
WC
t
AH
5.0 V
CE
OE
t
RC
Address
Data
t
AS
t
OE
t
WPH
t
CS
t
DH
DQ
7
PD
A0h
D
OUT
t
CE
WE
555h
PA
PA
t
OH
Data Polling
3rd Bus Cycle
t
GHWL
t
CH
D
OUT
Notes :
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles of four bus cycle sequence.
MBM29F080A
-55/-70/-90
28
(4) AC Waveforms for Alternate CE Controlled Program Operations
t
CP
t
DS
t
WHWH1
t
WC
t
AH
5.0 V
WE
OE
Address
Data
t
AS
t
CPH
t
WS
t
DH
DQ
7
PD
A0h
D
OUT
CE
555h
PA
PA
Data Polling
3rd Bus Cycle
t
GHEL
t
WH
Notes :
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ
7
is the output of the complement of the data written to the device.
D
OUT
is the output of the data written to the device.
Figure indicates last two bus cycles of four bus cycle sequence.
MBM29F080A
-55/-70/-90
29
(5) AC Waveforms Chip/Sector Erase Operations
(6) AC Waveforms for Data Polling during Embedded Algorithm Operations
V
CC
CE
OE
Address
Data
t
WP
WE
555h
2AAh
555h
555h
2AAh
SA*
t
DS
t
CH
t
AS
t
AH
t
CS
t
WPH
t
DH
t
VCS
t
WC
55h
55h
80h
AAh
AAh
10h/
30h
t
GHWL
*
: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
t
OEH
t
OE
t
WHWH1 or 2
CE
OE
WE
t
DF
t
CH
t
CE
High-Z
DQ
7
=
Valid Data
DQ
0
to DQ
6
= Output Flug
DQ
0
to DQ
7
DQ
7
*
Valid Data
High-Z
t
EOE
DQ
7
Data
Data
DQ
6
to DQ
0
* : DQ
7
= Valid Data (The device has completed the Embedded operation.)
MBM29F080A
-55/-70/-90
30
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
(8) RY/BY Timing Diagram During Program/Erase Operations
(9) RESET, RY/BY Timing Diagram
t
OEH
CE
WE
OE
DQ
6
= Toggle
*
t
OES
t
OE
DQ
6
=
Stop Toggling
DQ
0
to DQ
7
Valid
DQ
6
= Toggle
DQ
6
Data
* : DQ
6
stops toggling (The device has completed the Embedded operation.)
CE
WE
RY/BY
Rising edge of the last WE signal
Entire programming
or erase operations
t
BUSY
RESET
t
READY
t
RP
t
RB
WE
RY/BY
MBM29F080A
-55/-70/-90
31
(10) AC Waveforms for Sector Group Protection Timing Diagram
t
VLHT
SGAx
SGAy
A
0
A
6
A
9
V
ID
5 V
t
VLHT
OE
V
ID
5 V
t
VLHT
t
VLHT
WE
CE
t
OE
01h
Data
V
CC
A
1
Address
t
WPP
t
OESP
t
CSP
t
VCS
SGAx
=
Sector Group Address for initial sector
SGAy
=
Sector Group Address for next sector
MBM29F080A
-55/-70/-90
32
(11) Temporary Sector Group Unprotection Timing Diagram
(12) DQ
2
vs. DQ
6
RESET
V
ID
5 V
WE
CE
RY/BY
t
VLHT
t
VLHT
t
VLHT
V
CC
t
VCS
t
VIDR
Program or Erase Command Sequence
Unprotection period
DQ
2
*
DQ
6
WE
Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase
Erase
Complete
Toggle
DQ
2
and DQ
6
with OE or CE
* : DQ
2
is read from the erase-suspended sector.
MBM29F080A
-55/-70/-90
33
s
s
s
s
FLOW CHART
(1) Embedded Program
TM
Algorithm
No
Yes
Start
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Write Program Command
Sequence
(See Below)
Data Polling Device
Increment Address
Last Address
?
Programming Completed
Program Address/Program Data
EMBEDDED ALGORITHMS
MBM29F080A
-55/-70/-90
34
(2) Embedded EraseTM Algorithm
Start
555h/AAh
2AAh/55h
555h/AAh
555h/80h
555h/10h
2AAh/55h
555h/AAh
2AAh/55h
555h/AAh
555h/80h
2AAh/55h
Additional sector
erase commands
are optional.
Write Erase Command
Sequence
(See Below)
Data Polling or Toggle Bit I
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Sector Address/30h
Sector Address/30h
Sector Address/30h
Note : To insure the command has been accepted, the system software should check the status
of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on
the second status check, the command may not have been accepted.
MBM29F080A
-55/-70/-90
35
(3) Data Polling Algorithm
Fail
DQ
7
= Data?
No
No
DQ
7
= Data?
DQ
5
= 1?
Pass
Yes
Yes
No
Start
Read Byte
(DQ
0
to DQ
7
)
Addr. = VA
Read Byte
(DQ
0
to DQ
7
)
Addr. = VA
Yes
Note : DQ
7
is rechecked even if DQ
5
= "1" because DQ
7
may change simultaneously with DQ
5
.
VA
= Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
= Any of the sector group
addresses within the sector not
being protected during sector
erase or multiple sector erases
operation.
MBM29F080A
-55/-70/-90
36
(4) Toggle Bit I Algorithm
Fail
DQ
6
= Toggle
?
Yes
No
DQ
6
= Toggle
DQ
5
= 1
Pass
Yes
No
Yes
Start
Read
?
(DQ
7
to DQ
0
)
Addr. = "H" or "L"
No
Read
(DQ
7
to DQ
0
)
Addr. = "H" or "L"
?
Read
(DQ
7
to DQ
0
)
Addr. = "H" or "L"
Read
(DQ
7
to DQ
0
)
Addr. = "H" or "L"
*1
*1, *2
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : DQ
6
is rechecked even if DQ
5
= "1" because DQ
6
may stop toggling at the same time as DQ
5
changing to "1".
*1, *2
MBM29F080A
-55/-70/-90
37
(5) Sector Group Protection Algorithm
Setup Sector Group Addr.
Activate WE Pulse
WE = V
IH,
CE = OE = V
IL,
(A
9
should remain V
ID
)
Yes
Yes
No
No
PLSCNT = 1
Time out 100
s
Read from Sector Group
Increment PLSCNT
No
Yes
Protect Another Sector
Start
Sector Protection
Data = 01h?
PLSCNT = 25?
Device Failed
Remove V
ID
from A
9
Completed
Remove
V
ID
from A
9
Write Reset Command
Addr. (A
19
, A
18
, A
17
)
A
1
= 1, A
0
= A
6
= 0
OE = V
ID
, A
9
= V
ID
,
CE = V
IL
, RESET = V
IH
(
A
19
, A
18
, A
17
)
Write Reset Command
Group?
MBM29F080A
-55/-70/-90
38
(6) Temporary Sector Group Unprotection Algorithm
RESET = V
ID
*
1
Perform Erase or
Program Operations
RESET = V
IH
Start
Temporary Sector Group
Unprotection Completed
*
2
*1 : All Protected sector groups unprotected.
*2 : All previously protected sector groups are protected once again.
MBM29F080A
-55/-70/-90
39
s
s
s
s
ORDERING INFORMATION
Part No.
Package
Access Time
Remarks
MBM29F080A-55PTN
MBM29F080A-70PTN
MBM29F080A-90PTN
40-pin plastic TSOP(1)
(FPT-40P-M06)
(Normal Bend)
55
70
90
MBM29F080A-55PTR
MBM29F080A-70PTR
MBM29F080A-90PTR
40-pin plastic TSOP(1)
(FPT-40P-M07)
(Reverse Bend)
55
70
90
MBM29F080A-55PFTN
MBM29F080A-70PFTN
MBM29F080A-90PFTN
48-pin plastic TSOP(1)
(FPT-48P-M19)
(Normal Bend)
55
70
90
MBM29F080A-55PFTR
MBM29F080A-70PFTR
MBM29F080A-90PFTR
48-pin plastic TSOP(1)
(FPT-48P-M20)
(Reverse Bend)
55
70
90
MBM29F080A-55PF
MBM29F080A-70PF
MBM29F080A-90PF
44-pin plastic SOP
(FPT-44P-M16)
55
70
90
MBM29F080A -55
PFTN
DEVICE NUMBER/DESCRIPTION
MBM29F080A
8 Mega-bit (1 M
8-Bit) CMOS Flash Memory
5.0 V-only Read, Write, and Erase
64 K Byte (16 Sectors)
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP(1) Standard Pinout )
PFTR = 48-Pin Thin Small Outline Package
(TSOP(1) Reverse Pinout)
PTN
= 40-Pin Thin Small Outline Package
(TSOP(1) Standard Pinout )
PTR
= 40-Pin Thin Small Outline Package
(TSOP(1) Reverse Pinout)
PF
= 44-Pin Small Outline Package
(SOP Standard Pinout)
SPEED OPTION
See Product Selector Guide
MBM29F080A
-55/-70/-90
40
s
s
s
s
PACKAGE DIMENSIONS
(Continued)
40-pin plastic TSOP (1)
(FPT-40P-M06)
Note 1) * : Resin protrusion. (Each side :
+
0.15 (.006) Max) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
40-pin plastic TSOP (1)
(FPT-40P-M07)
Note 1) * : Resin protrusion. (Each side :
+
0.15 (.006) Max) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
.007
.003
+.001
0.08
+0.03
0.17
"A"
0.10(.004)
(Mounting height)
1.10
+0.10
0.05
+.004
.002
.043
(Stand off)
0.100.05(.004.002)
(.394.008)
*10.000.20
0.10(.004)
M
(.009.002)
0.220.05
(.724.008)
*18.400.20
(.787.008)
20.000.20
LEAD No.
INDEX
21
20
40
1
2003 FUJITSU LIMITED F40007S-c-3-4
C
0~8
0.25(.010)
0.60
0.15
(.024
.006)
Details of "A" part
0.50(.020)
.003
+.001
.007
0.08
+0.03
0.17
"A"
0.10(.004)
(Mounting height)
1.10
+0.10
0.05
+.004
.002
.043
(Stand off)
0.100.05(.004.002)
0.10(.004)
M
(.009.002)
0.220.05
(.394.008)
*10.000.20
(.724.008)
*18.400.20
(.787.008)
20.000.20
LEAD No.
INDEX
21
20
40
1
2003 FUJITSU LIMITED F40008S-c-3-4
C
0~8
0.25(.010)
0.600.15
(.024.006)
Details of "A" part
0.50(.020)
MBM29F080A
-55/-70/-90
41
(Continued)
48-pin plastic TSOP (1)
(FPT-48P-M19)
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are
+
0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
48-pin plastic TSOP (1)
(FPT-48P-M20)
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are
+
0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
.003
+.001
0.08
+0.03
.007
0.17
"A"
(Stand off height)
0.10(.004)
(Mounting
height)
(.472
.008)
12.00
0.20
LEAD No.
48
25
24
1
(.004
.002)
0.10(.004)
M
1.10
+0.10
0.05
+.004
.002
.043
0.10
0.05
(.009
.002)
0.22
0.05
(.787
.008)
20.00
0.20
(.724
.008)
18.40
0.20
INDEX
2003 FUJITSU LIMITED F48029S-c-6-7
C
0~8
0.25(.010)
0.50(.020)
0.60
0.15
(.024
.006)
Details of "A" part
*
*
.003
+.001
.007
0.08
+0.03
0.17
"A"
(Stand off height)
(.004
.002)
0.10
0.05
0.10(.004)
(Mounting height)
12.00
0.20(.472.008)
LEAD No.
48
25
24
1
0.10(.004)
M
1.10
+0.10
0.05
+.004
.002
.043
(.009
.002)
0.22
0.05
(.787
.008)
20.00
0.20
(.724
.008)
18.40
0.20
INDEX
2003 FUJITSU LIMITED F48030S-c-6-7
C
0~8
0.25(.010)
0.600.15
(.024.006)
Details of "A" part
*
*
0.50(.020)
MBM29F080A
-55/-70/-90
42
(Continued)
44-pin plastic SOP
(FPT-44P-M16)
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F44023S-c-6-6
M
0.13(.005)
1.27(.050)
13.000.10
16.000.20
(.512.004)
(.630.008)
1
1.120
.008
+.010
0.20
+0.25
28.45
0.10(.004)
22
23
44
0.07
+0.08
0.42
.017
+.0031
.0028
INDEX
0~8
0.25(.010)
(Mounting height)
Details of "A" part
2.350.15
(.093.006)
0.15
+0.10
0.20
.008
+.004
.006
(Stand off)
0.800.20
(.031.008)
0.880.15
(.035.006)
0.04
+0.03
0.17
.007
+.001
.002
"A"
*
1
*
2
MBM29F080A
-55/-70/-90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
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device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
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function and schematic diagrams, shall not be construed as license
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Fujitsu assumes no liability for any infringement of the intellectual
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The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
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and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
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reaction control in nuclear facility, aircraft flight control, air traffic
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Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
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If any products described in this document represent goods or
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Foreign Exchange and Foreign Trade Law of Japan, the prior
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F0305
FUJITSU LIMITED Printed in Japan
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