DS05-20879-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

16M (2M

8/1M

16) BIT

MBM29F160TE/BE

-55/-70/-90

GENERAL DESCRIPTION

The MBM29F160TE/BE is a 16M-bit, 5.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words
of 16 bits each. The MBM29F160TE/BE is offered in a 48-pin TSOP (I) package. The device is designed to be
programmed in-system with the standard system 5.0 V V

supply. 12.0 V V

is not required for write or erase

operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F160TE/BE offers access times of 55 ns, 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F160TE/BE is pin and command set compatible with JEDEC standard E

PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 12.0 V Flash or EPROM devices.

(Continued)

PRODUCT LINE UP

PACKAGES

Part No.

MBM29F160TE/160BE

Ordering Part No.

= 5.0 V

5% -55

= 5.0 V

10%

-70

-90

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

(Continued)

The MBM29F160TE/BE is programmed by executing the program command sequence. This will invoke the
Embedded Program

* Algorithm which is an internal algorithm that automatically times the program pulse

widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5
seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded
Erase

* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already

programmed before executing the erase operation. During erase, the device automatically times the erase pulse
widths and verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F160TE/BE is erased when shipped from the factory.
The device features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

comleted, the device internally resets to the read mode.
The MBM29F160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system's microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29F160TE/BE memory electrically erases all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.

* :

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

FEATURES

· 0.23

m Process Technology

· Single 5.0 V read, program and erase

Minimizes system level power requirements

· Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

· Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)

· Minimum 100,000 program/erase cycles
· High performance

55 ns maximum access time

· Sector erase architecture

One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase

· Boot Code Sector Architecture

T = Top sector
B = Bottom sector

· Embedded Erase Algorithms

Automatically pre-programs and erases the chip or any sector

· Embedded Program Algorithms

Automatically programs and verifies data at specified address

· Data Polling and Toggle Bit feature for detection of program or erase cycle completion
· Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

· Low V

write inhibit

4.2 V

· Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same devic

· Hardware RESET pin

Resets internal state machine to the read mode

· Sector protection

Hardware method disables any combination of sectors from program or erase operations

· Temporary sector unprotection

Temporary sector unprotection via the RESET pin

· In accordance with CFI (Common Flash Memory Interface)
· WP Input pin (Hardware Protect)

At V

, allows protection of boot sectors, regardless of sector protection/unprotection status

At V

, allows removal of boot sector protection

At open, allows removal of boot sector protection (MBM29F160TE/BE)

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

PIN ASSIGNMENT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

N.C.

RESET

N.C.
N.C.

RY/BY

BYTE
V

-1

OE
V

CE
A

Standard Pinout

TSOP(I)

(Marking Side)

(FPT-48P-M19)

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
45
45
46
47
48

Reverse Pinout

(Marking Side)

(FPT-48P-M20)

RY/BY

N.C.
N.C.

RESET

N.C.

CE
V

OE
DQ

-1

BYTE
A

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

FLEXIBLE SECTOR-ERASE ARCHITECTURE

· One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode.
· One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode.
· Individual-sector, multiple-sector, or bulk-erase capability.
· Individual or multiple-sector protection is user definable.

MBM29F160TE Top Boot Sector Architecture

Sector

Sector Size

(

8) Address Range

(

16) Address Range

SA0

64 Kbytes or 32 Kwords

00000H to 0FFFFH

00000H to 07FFFH

SA1

64 Kbytes or 32 Kwords

10000H to 1FFFFH

08000H to 0FFFFH

SA2

64 Kbytes or 32 Kwords

20000H to 2FFFFH

10000H to 17FFFH

SA3

64 Kbytes or 32 Kwords

30000H to 3FFFFH

18000H to 1FFFFH

SA4

64 Kbytes or 32 Kwords

40000H to 4FFFFH

20000H to 27FFFH

SA5

64 Kbytes or 32 Kwords

50000H to 5FFFFH

28000H to 2FFFFH

SA6

64 Kbytes or 32 Kwords

60000H to 6FFFFH

30000H to 37FFFH

SA7

64 Kbytes or 32 Kwords

70000H to 7FFFFH

38000H to 3FFFFH

SA8

64 Kbytes or 32 Kwords

80000H to 8FFFFH

40000H to 47FFFH

SA9

64 Kbytes or 32 Kwords

90000H to 9FFFFH

48000H to 4FFFFH

SA10

64 Kbytes or 32 Kwords

A0000H to AFFFFH

50000H to 57FFFH

SA11

64 Kbytes or 32 Kwords

B0000H to BFFFFH

58000H to 5FFFFH

SA12

64 Kbytes or 32 Kwords

C0000H to CFFFFH

60000H to 67FFFH

SA13

64 Kbytes or 32 Kwords

D0000H to DFFFFH

68000H to 6FFFFH

SA14

64 Kbytes or 32 Kwords

E0000H to EFFFFH

70000H to 77FFFH

SA15

64 Kbytes or 32 Kwords

F0000H to FFFFFH

78000H to 7FFFFH

SA16

64 Kbytes or 32 Kwords

100000H to 10FFFFH

80000H to 87FFFH

SA17

64 Kbytes or 32 Kwords

110000H to 11FFFFH

88000H to 8FFFFH

SA18

64 Kbytes or 32 Kwords

120000H to 12FFFFH

90000H to 97FFFH

SA19

64 Kbytes or 32 Kwords

130000H to 13FFFFH

98000H to 9FFFFH

SA20

64 Kbytes or 32 Kwords

140000H to 14FFFFH

A0000H to A7FFFH

SA21

64 Kbytes or 32 Kwords

150000H to 15FFFFH

A8000H to AFFFFH

SA22

64 Kbytes or 32 Kwords

160000H to 16FFFFH

B0000H to B7FFFH

SA23

64 Kbytes or 32 Kwords

170000H to 17FFFFH

B8000H to BFFFFH

SA24

64 Kbytes or 32 Kwords

180000H to 18FFFFH

C0000H to C7FFFH

SA25

64 Kbytes or 32 Kwords

190000H to 19FFFFH

C8000H to CFFFFH

SA26

64 Kbytes or 32 Kwords

1A0000H to 1AFFFFH

D0000H to D7FFFH

SA27

64 Kbytes or 32 Kwords

1B0000H to 1BFFFFH

D8000H to DFFFFH

SA28

64 Kbytes or 32 Kwords

1C0000H to 1CFFFFH

E0000H to E7FFFH

SA29

64 Kbytes or 32 Kwords

1D0000H to 1DFFFFH

E8000H to EFFFFH

SA30

64 Kbytes or 32 Kwords

1E0000H to 1EFFFFH

F0000H to F7FFFH

SA31

32 Kbytes or 16 Kwords

1F0000H to 1F7FFFH

F8000H to FBFFFH

SA32

8 Kbytes or 4 Kwords

1F8000H to 1F9FFFH

FC000H to FCFFFH

SA33

8 Kbytes or 4 Kwords

1FA000H to 1FBFFFH

FD000H to FDFFFH

SA34

16 Kbytes or 8 Kwords

1FC000H to 1FFFFFH

FE000H to FFFFFH

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

MBM29F160BE Bottom Boot Sector Architecture

Sector

Sector Size

(

8) Address Range

(

16) Address Range

SA0

16 Kbytes or 8 Kwords

00000H to 03FFFH

00000H to 01FFFH

SA1

8 Kbytes or 4 Kwords

04000H to 05FFFH

02000H to 02FFFH

SA2

8 Kbytes or 4 Kwords

06000H to 07FFFH

03000H to 03FFFH

SA3

32 Kbytes or 16 Kwords

08000H to 0FFFFH

04000H to 07FFFH

SA4

64 Kbytes or 32 Kwords

10000H to 1FFFFH

08000H to 0FFFFH

SA5

64 Kbytes or 32 Kwords

20000H to 2FFFFH

10000H to 17FFFH

SA6

64 Kbytes or 32 Kwords

30000H to 3FFFFH

18000H to 1FFFFH

SA7

64 Kbytes or 32 Kwords

40000H to 4FFFFH

20000H to 27FFFH

SA8

64 Kbytes or 32 Kwords

50000H to 5FFFFH

28000H to 2FFFFH

SA9

64 Kbytes or 32 Kwords

60000H to 6FFFFH

30000H to 37FFFH

SA10

64 Kbytes or 32 Kwords

70000H to 7FFFFH

38000H to 3FFFFH

SA11

64 Kbytes or 32 Kwords

80000H to 8FFFFH

40000H to 47FFFH

SA12

64 Kbytes or 32 Kwords

90000H to 9FFFFH

48000H to 4FFFFH

SA13

64 Kbytes or 32 Kwords

A0000H to AFFFFH

50000H to 57FFFH

SA14

64 Kbytes or 32 Kwords

B0000H to BFFFFH

58000H to 5FFFFH

SA15

64 Kbytes or 32 Kwords

C0000H to CFFFFH

60000H to 67FFFH

SA16

64 Kbytes or 32 Kwords

D0000H to DFFFFH

68000H to 6FFFFH

SA17

64 Kbytes or 32 Kwords

E0000H to EFFFFH

70000H to 77FFFH

SA18

64 Kbytes or 32 Kwords

F0000H to FFFFFH

78000H to 7FFFFH

SA19

64 Kbytes or 32 Kwords

100000H to 10FFFFH

80000H to 87FFFH

SA20

64 Kbytes or 32 Kwords

110000H to 11FFFFH

88000H to 8FFFFH

SA21

64 Kbytes or 32 Kwords

120000H to 12FFFFH

90000H to 97FFFH

SA22

64 Kbytes or 32 Kwords

130000H to 13FFFFH

98000H to 9FFFFH

SA23

64 Kbytes or 32 Kwords

140000H to 14FFFFH

A0000H to A7FFFH

SA24

64 Kbytes or 32 Kwords

150000H to 15FFFFH

A8000H to AFFFFH

SA25

64 Kbytes or 32 Kwords

160000H to 16FFFFH

B0000H to B7FFFH

SA26

64 Kbytes or 32 Kwords

170000H to 17FFFFH

B8000H to BFFFFH

SA27

64 Kbytes or 32 Kwords

180000H to 18FFFFH

C0000H to C7FFFH

SA28

64 Kbytes or 32 Kwords

190000H to 19FFFFH

C8000H to CFFFFH

SA29

64 Kbytes or 32 Kwords

1A0000H to 1AFFFFH

D0000H to D7FFFH

SA30

64 Kbytes or 32 Kwords

1B0000H to 1BFFFFH

D8000H to DFFFFH

SA31

64 Kbytes or 32 Kwords

1C0000H to 1CFFFFH

E0000H to E7FFFH

SA32

64 Kbytes or 32 Kwords

1D0000H to 1DFFFFH

E8000H to EFFFFH

SA33

64 Kbytes or 32 Kwords

1E0000H to 1EFFFFH

F0000H to F7FFFH

SA34

64 Kbytes or 32 Kwords

1F0000H to 1FFFFFH

F8000H to FFFFFH

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

DEVICE BUS OPERATIONS

Legend: L = V

, H = V

, X = V

or V

= pulse input. See DC Characteristics for voltage levels.

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 7.

2. Refer to the section on Sector Protection.

3. WE can be V

if OE is V

, OE at V

initiates the write operations.

4. V

=5.0 V ±10%

Table 2 MBM29F160TE/BE User Bus Operation (BYTE = V

)

Operation

RESET

Auto-Select Manufacture Code (1)

Code

Auto-Select Device Code (1)

Code

Read (3)

OUT

Standby

HIGH-Z

Output Disable

HIGH-Z

Write (Program/Erase)

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

Code

Temporary Sector Unprotection

Reset (Hardware)/Standby

HIGH-Z

Boot Block Write Protection

Table 3 MBM29F160TE/BE User Bus Operation (BYTE = V

)

Operation

WE DQ

-1

to DQ

RESET

Auto-Select Manufacture Code (1)

Code

Auto-Select Device Code (1)

Code

Read (3)

-1

OUT

Standby

HIGH-Z

Output Disable

HIGH-Z

Write (Program/Erase)

-1

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

Code

Temporary Sector Unprotection

Reset (Hardware)/Standby

HIGH-Z

Boot Block Write Protection

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

FUNCTIONAL DESCRIPTION

Read Mode

The MBM29F160TE/BE has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.

Address access time (t

ACC

) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t

ACC

- t

time.) When reading out a data without changing addresses

after power-u, it is necessary to input hardware reset or change CE pin from "H" tp "L".

Standby Mode

There are two ways to implement the standby mode on the MBM29F160TE/BE devices. One is by using both
the CE and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V

±0.3 V.

Under this condition the current consumed is less than 5

A max. During Embedded Algorithm operation, V

Active current (I

CC2

) is required even CE = "H". The device can be read with standard access time (t

) from

either of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at V

±0.3 V

(CE = "H" or "L"). Under this condition the current consumed is less than 5

A max. Once the RESET pin is

taken high, the device requires t

of wake up time before outputs are valid for read access.

In the standby mode, the outputs are in the high-impedance state, independent of the OE input.

Output Disable

If the OE input is at a logic high level (V

), output from the device is disabled. This will cause the output pins to

be in a high-impedance state.

Autoselect

The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. The intent is to allow programming equipment to automatically match the device to be programmed
with its corresponding programming algorithm. The Autoselect command may also be used to check the status
of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional over the entire temperature range
of the device.

To activate this mode, the programming equipment must force V

(11.5 V to 12.5 V) on address pin A

. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A

from V

to V

. All

addresses are DON'T CARES except A

, A

, and A

-1

). (See Table 2 or Table 3.)

The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F160TE/BE is erased or programmed in a system without access to high voltage on the A

pin. The

command sequence is illustrated in Table 6, Command Definitions.

Byte 0 (A

= V

) represents the manufacture's code (Fujitsu = 04H) and byte 1 (A

= V

) represents the device

identifier code (MBM29F160TE = D2H and MBM29F160BE = D8H for x 8 mode; MBM29F160TE = 22D2H and
MBM29F160BE = 22D8H for x 16 mode). These two bytes/words are given in the Table 4.1 and 4.2. All identifiers
for manufactures and device will exhibit odd parity with DQ

defined as the parity bit. In order to read the proper

device codes when executing the Autoselect, A

must be V

. (See Tables 4.1 and 4.2.)

MBM29F160TE

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/MBM29F160BE

-55/-70/-90

*1: A

-1

is for Byte mode.

*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

(B): Byte mode
(W): Word mode

Table 4.1 MBM29F160TE/BE Sector Protection Verify Autoselect Code

Type

to A

-1

Code

(HEX)

Manufacture's Code

04H

Device Code

MBM29F160TE

Byte

D2H

Word

22D2H

MBM29F160BE

Byte

D8H

Word

22D8H

Sector Protection

Sector

Addresses

01H*

Table 4.2 Expanded Autoselect Code Table

Type

Code DQ

Manufacture's Code

04H A

-1

Device
Code

MBM29F160TE

(B)

D2H A

-1

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

(W) 22D2H

MBM29F160BE

(B)

D8H A

-1

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

(W) 22D8H

Sector Protection

01H A

-1

MBM29F160TE

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/MBM29F160BE

-55/-70/-90

Table 5 Sector Address Tables (MBM29F160TE)

Sector

Address

(

8) Address Range

(

16) Address Range

SA0

00000H to 0FFFFH

00000H to 07FFFH

SA1

10000H to 1FFFFH

08000H to 0FFFFH

SA2

20000H to 2FFFFH

10000H to 17FFFH

SA3

30000H to 3FFFFH

18000H to 1FFFFH

SA4

40000H to 4FFFFH

20000H to 27FFFH

SA5

50000H to 5FFFFH

28000H to 2FFFFH

SA6

60000H to 6FFFFH

30000H to 37FFFH

SA7

70000H to 7FFFFH

38000H to 3FFFFH

SA8

80000H to 8FFFFH

40000H to 47FFFH

SA9

90000H to 9FFFFH

48000H to 4FFFFH

SA10

A0000H to AFFFFH

50000H to 57FFFH

SA11

B0000H to BFFFFH

58000H to 5FFFFH

SA12

C0000H to CFFFFH

60000H to 67FFFH

SA13

D0000H to DFFFFH

68000H to 6FFFFH

SA14

E0000H to EFFFFH

70000H to 77FFFH

SA15

F0000H to FFFFFH

78000H to 7FFFFH

SA16

100000H to 10FFFFH

80000H to 87FFFH

SA17

110000H to 11FFFFH

88000H to 8FFFFH

SA18

120000H to 12FFFFH

90000H to 97FFFH

SA19

130000H to 13FFFFH

98000H to 9FFFFH

SA20

140000H to 14FFFFH

A0000H to A7FFFH

SA21

150000H to 15FFFFH

A8000H to AFFFFH

SA22

160000H to 16FFFFH

B0000H to B7FFFH

SA23

170000H to 17FFFFH

B8000H to BFFFFH

SA24

180000H to 18FFFFH

C0000H to C7FFFH

SA25

190000H to 19FFFFH

C8000H to CFFFFH

SA26

1A0000H to 1AFFFFH

D0000H to D7FFFH

SA27

1B0000H to 1BFFFFH

D8000H to DFFFFH

SA28

1C0000H to 1CFFFFH

E0000H to E7FFFH

SA29

1D0000H to 1DFFFFH

E8000H to EFFFFH

SA30

1E0000H to 1EFFFFH

F0000H to F7FFFH

SA31

1F0000H to 1F7FFFH

F8000H to FBFFFH

SA32

1F8000H to 1F9FFFH

FC000H to FCFFFH

SA33

1FA000H to 1FBFFFH

FD000H to FDFFFH

SA34

1FC000H to 1FFFFFH

FE000H to FFFFFH

MBM29F160TE

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/MBM29F160BE

-55/-70/-90

Table 6 Sector Address Tables (MBM29F160BE)

Sector

Address

(

8) Address Range

(

16) Address Range

SA0

00000H to 03FFFH

00000H to 01FFFH

SA1

04000H to 05FFFH

02000H to 02FFFH

SA2

06000H to 07FFFH

03000H to 03FFFH

SA3

08000H to 0FFFFH

04000H to 07FFFH

SA4

10000H to 1FFFFH

08000H to 0FFFFH

SA5

20000H to 2FFFFH

10000H to 17FFFH

SA6

30000H to 3FFFFH

18000H to 1FFFFH

SA7

40000H to 4FFFFH

20000H to 27FFFH

SA8

50000H to 5FFFFH

28000H to 2FFFFH

SA9

60000H to 6FFFFH

30000H to 37FFFH

SA10

70000H to 7FFFFH

38000H to 3FFFFH

SA11

80000H to 8FFFFH

40000H to 47FFFH

SA12

90000H to 9FFFFH

48000H to 4FFFFH

SA13

A0000H to AFFFFH

50000H to 57FFFH

SA14

B0000H to BFFFFH

58000H to 5FFFFH

SA15

C0000H to CFFFFH

60000H to 67FFFH

SA16

D0000H to DFFFFH

68000H to 6FFFFH

SA17

E0000H to EFFFFH

70000H to 77FFFH

SA18

F0000H to FFFFFH

78000H to 7FFFFH

SA19

100000H to 1FFFFFH

80000H to 87FFFH

SA20

110000H to 11FFFFH

88000H to 8FFFFH

SA21

120000H to 12FFFFH

90000H to 97FFFH

SA22

130000H to 13FFFFH

98000H to 9FFFFH

SA23

140000H to 14FFFFH

A0000H to A7FFFH

SA24

150000H to 15FFFFH

A8000H to 8FFFFH

SA25

160000H to 16FFFFH

B0000H to B7FFFH

SA26

170000H to 17FFFFH

B8000H to BFFFFH

SA27

180000H to 18FFFFH

C0000H to C7FFFH

SA28

190000H to 19FFFFH

C8000H to CFFFFH

SA29

1A0000H to 1AFFFFH

D0000H to D7FFFH

SA30

1B0000H to 1BFFFFH

D8000H to DFFFFH

SA31

1C0000H to 1CFFFFH

E0000H to E7FFFH

SA32

1D0000H to 1DFFFFH

E8000H to EFFFFH

SA33

1E0000H to 1EFFFFH

F0000H to F7FFFH

SA34

1F0000H to 1FFFFFH

F8000H to FFFFFH

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

Write

Device erasure and programming are accomplished via the command register. The command register serve as
inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V

, while CE is at V

and OE is at V

. Addresses are latched on

the falling edge of CE or WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse,
whichever occurs first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Write Protect (WP)

The write Protect function provides a hardware method of protecting certain boot sectors without using V

If the system asserts V

on the WP pin, the device disables program and erase functions in the "outermost" 16K

byte boot sectors independently of whether this sector was protected or unprotected using the method described
in "Sector / Sector Block Protection and Unprotection". The outmost 16K byte boot sector is the sector containing
the lowest addresses in a bottom-boot-configured devices, or the sector containing the highest addresses in a
top-boot-configured device.

If the system asserts V

on the WP pin, the devices reverts to whether the outmost 16K byte boot sector was

last set to be protected or unprotected. That is, sector protection or unprotection for this sector depends on
whether it was last protected or unprotected using the method describe in "Sector / Sector Block Protection and
Unprotection".

Sector Protection

The MBM29F160TE/BE features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming
equipment at the user's site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V

on address pin A

and control pin OE, (suggest

= 11.5V), CE = V

, and A

= V

. The sector addresses (A

, A

, and A

) should be set

to the sector to be protected. Tables 5 and 6 define the sector address for each of the thirty five (35) individual
sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated
with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 16
and 24 for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V

on address pin A

with CE and OE at V

and WE at V

. Scanning the sector addresses (A

, A

, and A

)

while (A

, A

) = (0, 1, 0) will produce a logical "1" code at device output DQ

for a protected sector. Otherwise

the devices will read 00H for unprotected sector. In this mode, the lower order addresses, except for A

, A

, and

are DON'T CARES. Address locations with A

= V

are reserved for Autoselect manufacturer and device

codes. A

-1

requires to apply to V

in byte mode.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses pins (A

, A

, and A

) represents the sector address will produce a logical "1" at DQ

for a protected sector. See

Tables 4.1 and 4.2 for Autoselect codes.

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29F160TE/BE devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. Refer to Figures 18 and 25.

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

Notes: 1. Address bits A

to A

= X = "H" or "L" for all address commands except or Program Address (PA) and

Sector Address (SA).

2. Bus operations are defined in Tables 2 and 3.

3. RA =Address of the memory location to be read.

PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE pulse.

SA =Address of the sector to be erased. The combination of A

, A

, and A

will

uniquely select any sector.

4. RD =Data read from location RA during read operation.

PD =Data to be programmed at location PA. Data is latched on the rising edge of WE.

5. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A

to A

Byte Mode: AAAH or 555H to addresses A

-1

to A

6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

Table 7 MBM29F160TE/BE Standard Command Definitions

Command

Sequence

(Notes 1, 2, 3, 5)

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Second

Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset
(Note 6)

Word

/Byte

XXXH F0H

Read/Reset
(Note 6)

Word

555H

AAH

2AAH

55H

555H

F0H

Byte

AAAH

555H

AAAH

Autoselect

Word

555H

AAH

2AAH

55H

555H

90H

Byte

AAAH

555H

AAAH

Byte/Word
Program
(Notes 3, 4)

Word

555H

AAH

2AAH

55H

555H

A0H

Byte

AAAH

555H

AAAH

Chip Erase

Word

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

10H

Byte

AAAH

555H

AAAH

555H

AAH

Sector Erase
(Note 3)

Word

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

30H

Byte

AAAH

555H

AAAH

555H

Sector Erase
Suspend

Word

/Byte

Erase can be suspended during sector erase with addr. ("H" or "L"). Data (B0H)

Sector Erase
Resume

Word

/Byte

Erase can be resumed after suspend with addr. ("H" or "L"). Data (30H)

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

SPA : Sector Address to be protected. Set sector address (SA) and (A

, A

) = (0, 1, 0).

SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector

addresses.

Notes: 1. This command is valid while fast mode.

2. Addresses from system set to A

to A

. The other addresses are "Don't Care".

3. The data "00H" is also acceptable.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ

to DQ

and DQ

to DQ

bits are ignored.

Read/Reset Command

The read or reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrive array data from the memory. The devices remain enabled for reads until the
command register contents are altered.

The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufactures and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A

to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A
read cycle from address XX01H for

16 (XX02H for

8) retrieves the device code (MBM29F160TE = D2H and

Table 8 MBM29F160TE/BE Extended Command Definitions

Command

Sequence

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Set to Fast Mode

Word

555H

AAH

2AAH

55H

555H

20H

Byte

AAAH

555H

AAAH

Fast Program
(Note 1)

Word

XXXH

A0H

Byte

XXXH

Reset from Fast
Mode (Note 1)

Word

XXXH

90H

XXXH

F0H

(Note 3)

Byte

XXXH

Query Command
(Note 2)

Word

55H

98H

Byte

AAH

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

MBM29F160BE = D8H for

8 mode; MBM29F160TE = 22D2H and MBM29F160BE = 22D8H for

16 mode).

(See Tables 4.1 and 4.2.)

All manufactures and device codes will exhibit odd parity with DQ

defined as the parity bit.

The sector state (protection or unprotection) will be indicated by address XX02H for

16 (XX04H for

8).

Scanning the sector addresses (A

, A

, and A

) while (A

, A

) = (0, 1, 0) will produce

a logical "1" at device output DQ

for a protected sector. The programming verification should be perform margin

mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,
also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command
sequence.

Byte/Word Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens
first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system
is not required to provide further controls or timings. The device will automatically provide adequate internally
generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

The automatic programming operation is completed when the data on DQ

is equivalent to data written to this

bit at which time the device return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the device requires that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still "0". Only
erase operations can convert "0"s to "1"s.

Figure 19 illustrates the Embedded Program

Algorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded
Erase

Algorithm command sequence the device will automatically program and verify the entire memory for

an all zero data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide
any controls or timings during these operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ

is "1" (See Write Operation Status section.) at which time the device returns to read mode.

(See Figure 8.)

Figure 20 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six-bus cycle operation. There are two "unlock" write cycles, followed by writing the "set-up"
command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

= 30H) is latched on the rising edge of WE. After a time-out of 50

s from the rising edge of the last sector erase

command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing six-bus cycle operations on Table 7. This sequence is
followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50

s otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50

from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the 50

s time-out window the timer is reset. Monitor DQ

to determine if the sector

erase timer window is still open. (See section DQ

, Sector Erase Timer.) Any command other than Sector Erase

or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous
command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case,
restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for
Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 34).

Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations. (See Figure 8.)

The automatic sector erase begins after the 50

s time out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the data on DQ

is "1" (See Write Operation Status section)

at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase
Time]

Number of Sector Erase.

Figure 20 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are "DON'T CARES" when
writing the Erase Suspend or Erase Resume commands.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20

s to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/

BY output pin and the DQ

bit will be at logic "1", and DQ

will stop toggling. The user must use the address of

the erasing sector for reading DQ

and DQ

to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ

to toggle. (See the section on DQ

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ

to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ

, or the Toggle Bit (DQ

)

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

which is the same as the regular Program operation. Note that DQ

must be read from the Program address

while DQ

can be read from any address.

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.

Extended Command

(1) Fast Mode

MBM29F160TE/BE has Fast Mode function. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence writing Fast Mode command into the command register. In
this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard
program command. (Do not write erase command in this mode.) The read operation is also executed after
exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. (Refer to the Figure 25 Extended algorithm.) The V

active current is required even CE = V

during

Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 25 Extended algorithm.)

(3) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-
compatible software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98H) into the command register. Following the
command write, a read cycle from specific address retrives device information. Please note that output data
of upper byte (DQ

to DQ

) is "0" in word mode (16 bit) read. Refer to the CFI code table. To terminate

operation, it is necessary to write the read/reset command sequence into the register.

Write Operation Status

Notes: 1. Performing successive read operations from any address will cause DQ

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at

the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ

to toggle.

Table 9 Hardware Sequence Flags

Status

In
Progress

Embedded Program Algorithm

Toggle

Embedded/Erase Algorithm

Toggle

Erase
Suspend
Mode

Erase Suspend Read
(Erase Suspended Sector)

Toggle

Erase Suspend Read
(Non-Erase Suspended Sector)

Data

Erase Suspend Program
(Non-Erase Suspended Sector)

Toggle

(Note 1)

(Note 2)

Exceeded
Time Limits

Embedded Program Algorithm

Toggle

Embedded/Erase Algorithm

Toggle

N/A

Erase Suspend Program
(Non-Erase Suspended Sector)

Toggle

N/A

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

3. DQ

and DQ

are reserve pins for future use.

4. DQ

is Fujitsu internal use only.

Data Polling

The MBM29F160TE/BE device features Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
devices will produce the complement of the data last written to DQ

. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ

. During the Embedded

Erase Algorithm, an attempt to read the device will produce a "0" at the DQ

output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ

output. The flowchart

for Data Polling (DQ

) is shown in Figure 21.

For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write
pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and
not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29F160TE/BE data pins (DQ

) may change asynchronously while the output

enable (OE) is asserted low. This means that the device is driving status information on DQ

at one instant of

time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ

output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm
operation and DQ

has a valid data, the data outputs on DQ

to DQ

may be still invalid. The valid data on DQ

to DQ

will be read on successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm or sector erase time-out.

See Figure 9 for the Data Polling timing specifications and diagrams.

Toggle Bit I

The MBM29F160TE/BE also feature the "Toggle Bit I" as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ

toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ

will stop toggling and valid data can be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-
write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2

s and then stop

toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100

s and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ

to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ

to toggle.

See Figure 10 and Figure 22 for the Toggle Bit I timing specifications and diagrams.

Exceeded Timing Limits

will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ

will produce a "1". This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the device under this

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 2 and 3.

The DQ

failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ

and DQ

never stops toggling. Once the device has exceeded timing limits, the DQ

bit will indicate a "1." Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset the device with command sequence.

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ

will

remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ

may

be used to determine if the sector erase timer window is still open. If DQ

is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ

is low ("0"), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ

prior to and following each subsequent sector erase command. If DQ

is high on the

second status check, the command may not have been accepted.

See Table 9: Hardware Sequence Flags.

Toggle Bit II

This Toggle Bit II, along with DQ

, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ

to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ

to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic "1" at DQ

is different from DQ

in that DQ

toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress.

Notes: 1. Performing successive read operations from any address will cause DQ

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic "1" at the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ

toggle.

For example, DQ

and DQ

can be used together to determine if the erase-suspend-read mode is in progress.

(DQ

toggles while DQ

does not.) See also Table 10 and Figure 18.

Table 10 Toggle Bit Status

Mode

Program

Toggle

Erase

Toggle

Erase Suspend Read
(Erase Suspended Sector)
(Note 1)

Toggle

Erase-Suspend Program

Toggle (Note 1)

1 (Note 2)

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

Furthermore, DQ

can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ

toggles if this bit is read from an erasing sector.

RY/BY

Ready/Busy Pin

The MBM29F160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy
with either a program or erase operation. If the output is high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29F160TE/BE is placed in an Erase Suspend mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V

RESET

Hardware Reset Pin

The MBM29F160TE/BE device may be reset by driving the RESET pin to V

. The RESET pin has a pulse

requirement and has to be kept low (V

) for at least t

in order to properly reset the internal state machine. Any

operation in the process of being executed will be terminated and the internal state machine will be reset to the
read mode t

READY

after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device

requires an additional t

before it allows read access. When the RESET pin is low, the device will be in the

standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.

If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will
need to be erased again before they can be programmed.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F160TE/BE device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ

. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ

-1

becomes the lowest address bit and DQ

to DQ

bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ

to DQ

and DQ

to DQ

bits are ignored. Refer to

Figures 13 and 14 for the timing diagrams.

Data Protection

The MBM29F160TE/BE is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.

The device also incorporates several features to prevent inadvertent write cycles resulting form V

power-up

and power-down transitions or system noise.

Low V

Write Inhibit

To avoid initiation of a write cycle during V

power-up and power-down, a write cycle is locked out for V

less

than 3.2 V (typically 3.7 V). If V

< V

LKO

, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V

level is greater than V

LKO

. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when V

is above 3.2 V.

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

Description

to A

to DQ

Query-unique ASCII string
"QRY"

10h
11h
12h

0051h
0052h
0059h

Primary OEM Command Set
2h: AMD/FJ standard type

13h
14h

0002h
0000h

Address for Primary
Extended Table

15h
16h

0040h
0000h

Alternate OEM Command
Set (00h = not applicable)

17h
18h

0000h
0000h

Address for Alternate OEM
Extended Table

19h

1Ah

0000h
0000h

Min. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Bh

0045h

Max. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Ch

0055h

Min. voltage

1Dh

0000h

Max. voltage

1Eh

0000h

Typical timeout per single
byte/word write 2

1Fh

0004h

Typical timeout for Min. size
buffer write 2

20h

0000h

Typical timeout per
individual block erase 2

21h

000Ah

Typical timeout for full chip
erase 2

22h

0000h

Max. timeout for byte/word
write 2

times typical

23h

0005h

Max. timeout for buffer write
2

times typical

24h

0000h

Max. timeout per individual
block erase 2

times typical

25h

0004h

Max. timeout for full chip
erase 2

times typical

26h

0000h

Device Size = 2

byte

27h

0015h

Flash Device Interface
description

28h
29h

0002h
0000h

Max. number of byte in
multi-byte write = 2

2Ah
2Bh

0000h
0000h

Number of Erase Block
Regions within device

2Ch

0004h

Erase Block Region 1
Information

2Dh

2Eh

2Fh

30h

0000h
0000h
0040h
0000h

Table 11 Common Flash Memory Interface Code

Description

to A

to DQ

Erase Block Region 2
Information

31h
32h
33h
34h

0001h
0000h
0020h
0000h

Erase Block Region 3
Information

35h
36h
37h
38h

0000h
0000h
0080h
0000h

Erase Block Region 4
Information

39h

3Ah
3Bh

3Ch

001Eh

0000h
0000h
0001h

Query-unique ASCII string
"PRI"

40h
41h
42h

0050h
0052h
0049h

Major version number, ASCII

43h

0031h

Minor version number, ASCII

44h

0030h

Address Sensitive Unlock
0 = Required
1 = Not Required

45h

0000h

Erase Suspend
0 = Not Supported
1 = To Read Only
2 = To Read & Write

46h

0002h

Sector Protect
0 = Not Supported
X = Number of sectors in per
group

47h

0001h

Sector Temporary Unprotect
00 = Not Supported
01 = Supported

48h

0001h

Sector Protection Algorithm

49h

0004h

Number of Sector for Bank 2
00h = Not Supported

4Ah

0000h

Burst Mode Type
00h = Not Supported

4Bh

0000h

Page Mode Type
00h = Not Supported

0000h

ACC

Min.(Acceleration) Supply

00h = Not Supported
D7-4: volt, D3-0: 100 mvolt

4Dh

0000h

ACC

Max.(Acceleration) Supply

00h = Not Supported
D7-4: volt, D3-0: 100 mvolt

4Eh

0000h

Boot Type
02h = MBM29F160BE
03h = MBM29F160TE

4Fh

00XXh

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

ABSOLUTE MAXIMUM RATINGS

Notes: 1. Minimum DC voltage on input or l/O pins are 0.5 V. During voltage transitions, inputs may negative

overshoot V

to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are V

+0.5 V. During voltage transitions,outputs may positive overshoot to V

+2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A

, OE, and RESET pins are 0.5 V. During voltage transitions, A

, OE,

and RESET pins may negative overshoot V

to 2.0 V for periods of up to 20 ns. Maximum DC input

voltage on A

, OE, and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of

up to 20 ns. Voltage difference between input voltage and supply voltage (V

) do not exceed 9 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING RANGES

Operating ranges define those limits between which the functionality of the device is quaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating conditionranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Rating

Unit

Min.

Max.

Storage Temperature

Tstg

+125

°C

Ambient Temperature with Power Applied

+85

°C

Voltage with Respect to Ground All pins
except A

, OE, RESET (Note 1)

, V

OUT

2.0

+7.0

, OE, and RESET

(Note 2)

2.0

+14.0

Power Supply Voltage (Note 1)

2.0

+7.0

Parameter

Symbol

Value

Unit

Min.

Max.

Ambient Temperature

(-55)

+70

°C

(-70/90)

+85

°C

Power Supply Voltage

(-55)

+4.75

+5.25

(-70/90)

+4.50

+5.50

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

DC CHARACTERISTICS

Notes: 1. The l

current listed includes both the DC operating current and the frequency dependent component.

2. l

active while Embedded Erase or Embedded Program is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. (V

) do not exceed 9 V.

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Max.

Unit

Input Leakage Current

= V

to V

, V

= V

Max.

1.0

+1.0

µA

Output Leakage Current

OUT

= V

to V

, V

= V

Max.

1.0

+1.0

µA

LIT

, OE, RESET Inputs Leakage

Current

= V

Max.,

, OE, RESET = 12.5 V

µA

CC1

Active Current (Note 1)

CE = V

, OE = V

f = 5 MHz

Byte

Word

CC2

Active Current (Note 2)

CE = V

, OE = V

CC3

Current (Standby)

= V

Max., CE = V

RESET = V

= V

Max., CE = V

0.3 V,

RESET = WP = V

0.3 V

µA

CC4

Current (Standby, RESET)

= V

Max.,

RESET = V

Max., RESET=V

0.3 V

WP = V

0.3 V

µA

Input Low Level

0.5

0.8

Input High Level

2.0

+ 0.5

Voltage for Autoselect,Sector
Protection, and Temporary
Sector Unprotection
(A

, OE, RESET) (Note 4)

11.5

12.5

Output Low Voltage Level

= 5.8 mA, V

= V

Min.

0.45

OH1

Output High Voltage Level

= 2.5 mA, V

= V

Min.

2.4

OH2

= 100 µA

0.4

LKO

Low V

Lock-Out Voltage

3.2

4.2

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

AC CHARACTERISTICS

· Read Only Operations Characteristics

Note 1:)

Note 2:

Output Load: 1 TTL gate and 30 pF

Output Load: 1 TTL gate and 100 pF

Input rise and fall times: 5 ns

Input pulse levels: 0 V to 3.0 V

Input pulse levels: 0.45 V to 2.4 V

Timing measurement reference level

Input: 1.5 V

Input: 0.8 V and 2.0 V

Output: 1.5 V

Output: 0.8 V and 2.0 V

Parameter

Symbols

Description

Test Setup

-55

(Note 1)

-70

(Note 1)

-90

(Note 2) Unit

JEDEC

Standard

AVAV

Read Cycle Time

Min.

AVQV

ACC

Address to Output Delay

CE = V

OE = V

Max.

ELQV

Chip Enable to Output Delay

OE = V

Max.

GLQV

Output Enable to Output Delay

Max.

EHQZ

Chip Enable to Output HIGH-Z

Max.

GHQZ

Output Enable to Output HIGH-Z

Max.

AXQX

Output Hold Time From Address,
CE or OE, Whichever Occurs First

Min.

READY

RESET Pin Low to Read Mode

Max.

ELFL

ELFH

CE or BYTE Switching Low or High

Max.

2.7 k

5.0 V

IN3064
or Equivalent

6.2 k

Device

Under

Test

Diodes = IN3064
or Equivalent

Figure 4 Test Conditions

Notes : C

= 30 pF including jig capacitance (MBM29F160TE/BE-55/-70)

= 100 pF including jig capacitance (MBM29F160TE/BE-55/-70)

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

· Write (Erase/Program) Operations

(Continued)

Parameter Symbols

Description

MBM29F160TE/BE

Unit

JEDEC

Standard

-55

-70

-90

AVAV

Write Cycle Time

Min.

AVWL

Address Setup Time

Min.

WLAX

Address Hold Time

Min.

DVWH

Data Setup Time

Min.

WHDX

Data Hold Time

Min.

OES

Output Enable Setup Time

Min.

OEH

Output Enable
Hold Time

Read

Min.

Toggle and Data Polling

Min.

GHWL

Read Recover Time Before Write

Min.

GHEL

Read Recover Time Before Write
(OE High to CE Low)

Min.

ELWL

CE Setup Time

Min.

WLEL

WE Setup Time

Min.

WHEH

CE Hold Time

Min.

EHWH

WE Hold Time

Min.

WLWH

Write Pulse Width

Min.

ELEH

CE Pulse Width

Min.

WHWL

WPH

Write Pulse Width High

Min.

EHEL

CPH

CE Pulse Width High

Min.

WHWH1

Programming Operation

Byte

Typ.

µs

Word

WHWH2

Sector Erase Operation (Note 1)

Typ.

EOE

Delay Time from Embedded Output Enable

Max.

VCS

Setup Time

Min.

µs

VLHT

Voltage Transition Time (Note 2)

Min.

µs

WPP

Write Pulse Width (Note 2)

Min.

100

µs

OESP

OE Setup Time to WE Active (Note 2)

Min.

µs

CSP

CE Setup Time to WE Active (Note 2)

Min.

µs

Recover Time From RY/BY

Min.

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

FUJITSU LIMITED

For further information please contact:

Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329

http://www.fujitsu.co.jp/

North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
Fax: +1-408-922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608
Fax: +1-408-922-9179

http://www.fujitsumicro.com/

Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220

http://www.fmap.com.sg/

F0001

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.

The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.

Document Outline

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Document Outline

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