DS05-20851-4E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
4M (512K
8/256K
16) BIT
MBM29F400TC
-55/-70/-90
/MBM29F400BC
-55/-70/-90
s
FEATURES
Single 5.0 V read, write, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type)
44-pin SOP (Package suffix: PF)
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Low Vcc write inhibit
3.2 V
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
Hardware RESET pin
Resets internal state machine to the read mode
Sector protection
Hardware method disables any combination of sectors from write or erase operations
Temporary sector unprotection
Temporary sector unprotection via the RESET pin.
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MBM29F400TC
-55/-70/-90
/MBM29F400BC
-55/-70/-90
s
GENERAL DESCRIPTION
The MBM29F400TC/BC is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K
words of 16 bits each. The MBM29F400TC/BC is offered in a 48-pin TSOP and 44-pin SOP packages. This
device is designed to be programmed in-system with the standard system 5.0 V V
CC
supply. 12.0 V V
PP
is not
required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29F400TC/BC offers access times 55 ns and 90 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F400TC/BC is pin and command set compatible with JEDEC standard. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar
to reading from12.0 V Flash or EPROM devices.
The MBM29F400TC/BC is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).
The devices also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F400TC/BC is erased when shipped from the factory.
The devices features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu's Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F400TC/BC memory electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
4
MBM29F400TC
-55/-70/-90
/MBM29F400BC
-55/-70/-90
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes.
Individual-sector, multiple-sector, or bulk-erase capability.
Individual or multiple-sector protection is user definable.
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
3FFFFH
2FFFFH
1FFFFH
0FFFFH
00000H
16K byte
8K byte
8K byte
32K byte
64K byte
64K byte
64K byte
7FFFFH
7BFFFH
79FFFH
77FFFH
6FFFFH
5FFFFH
4FFFFH
MBM29F400TC Sector Architecture
MBM29F400BC Sector Architecture
64K byte
32K byte
8K byte
8K byte
16K byte
7FFFFH
6FFFFH
5FFFFH
4FFFFH
3FFFFH
2FFFFH
1FFFFH
0FFFFH
07FFFH
05FFFH
03FFFH
00000H
3FFFFH
37FFFH
2FFFFH
27FFFH
1FFFFH
17FFFH
0FFFFH
07FFFH
03FFFH
02FFFH
01FFFH
00000H
(
8)
(
16)
1FFFFH
17FFFH
0FFFFH
07FFFH
00000H
3FFFFH
3DFFFH
3CFFFH
3BFFFH
37FFFH
2FFFFH
27FFFH
(
8)
(
16)
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