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Электронный компонент: AD1315KZ

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REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD1315
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
High Speed Active Load
with Inhibit Mode
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD1315 is a complete, high speed, current switching load
designed for use in linear, digital or mixed signal test systems.
By combining a high speed monolithic process with a unique
surface mount package, this product attains superb electrical
performance while preserving optimum packaging densities in
an ultrasmall 16-lead, hermetically sealed gull wing package.
Featuring current programmability of up to +50 mA, the
AD1315 is designed to force the device under test to source or
sink the programmed I
OHPROG
and I
OLPROG
currents. The I
OH
and I
OL
currents are determined by applying a corresponding
voltage (5 V = 50 mA) to the I
OH
and I
OL
pins. The voltage-
to-current conversion is performed within the AD1315 thus
allowing the current levels to be set by a standard voltage out
digital-to-analog converter.
The AD1315's transition from IOH to IOL occurs when the
output voltage of the device under test slews above or below the
programmed threshold, or commutation voltage. The commuta-
tion voltage is programmable from 2 V to +7 V, covering the
large spectrum of logic devices while able to support the large
current specifications (48 mA) typically associated with line
drivers. To test I/O devices, the active load can be switched into
a high impedance state (Inhibit mode) electrically removing the
active load from the path through the Inhibit mode feature. The
active load leakage current in Inhibit is typically 20 nA.
The Inhibit input circuitry is implemented utilizing high speed
differential inputs with a common-mode voltage range of 7 volts
and a maximum differential voltage of 4 volts. This allows for
the direct interface to the precision of differential ECL timing or
the simplicity of switching the Active Load from a single ended
TTL or CMOS logic source. With switching speeds from IOH
or Io~ into Inhibit of less than 1.5 ns, the AD1315 can be
electrically removed from the signal path "on-the-fly."
The AD1315 is available in a 16-lead, hermetically sealed gull
wing package and is specified to operate over the ambient com-
mercial temperature range from 0
C to +70
C.
FEATURES
+50 mA Voltage Programmable Current Range
1.5 ns Propagation Delay
Inhibit Mode Function
High Speed Differential Inputs for Maximum Flexibility
Hermetically Sealed Small Gull Wing Package
Compatible with AD1321, AD1324 Pin Drivers
APPLICATIONS
Automatic Test Equipment
Semiconductor Test System
Board Level Test System
2
REV. A
AD1315SPECIFICATIONS
(All measurements made in free air at +25 C. +V
S
= +10 V, V
S
= 5.2 V, unless
otherwise noted.)
AD1315KZ
Parameter
Min
Typ
Max
Units
Comments
DIFFERENTIAL INPUT CHARACTERISTICS
INH to
INH
Input Voltage, Any One Input
3.0
4.0
Volts
Differential Input Range
0.4
ECL
4.0
Volts
Bias Current
2.0
1.0
2.0
mA
Current Program Voltage Range
I
OH
, 0 mA to +50 mA (Sink)
1
0
+5.0
Volts
I
OL
, 0 mA to 50 mA (Source)
1
0
+5.0
Volts
Input Resistance
50
k
I
OHRTN
, I
OCRTN
Range
2
2.0
+7.0
Volts
V
COM
, V
DUT
Range
2.0
+7.0
Volts
I
OH
, 0 mA to +50 mA
0.5
+7.0
Volts
V
DUT
V
COM
>1 V
I
OL
, 0 mA to 50 mA
2.0
+4.0
Volts
V
COM
V
DUT
>1 V
OUTPUT CHARACTERISTICS
3
Active (Sink/Source) Mode
Transfer Function
10
mA/V
See Figure 1
Accuracy
See Figure 1
Linearity Error
0.12
+0.12
% FSR
Gain Error
2.0
+2.0
% FSR
Offset Error
1.0
+1.0
mA
Output Current TC
10
A/
C
Inhibit Mode
Output Capacitance
3.0
pF
Inhibit Leakage
200
20
200
nA
DYNAMIC PERFORMANCE
3
Propagation Delay
See Figure 2
I
MAX
to INHIBIT (t
PD1
)
4
0.5
1.5
ns
INHIBIT to
I
MAX
(t
PD2
)
4
1.5
3.0
ns
POWER SUPPLIES
V
S
to +V
S
Difference
15.2
15.4
Volts
Supply Range
Positive Supply
+9.5
+10
+10.5
Volts
Negative Supply
5.45
5.2
4.95
Volts
Current
Positive Supply
5
+70
5
+85
+100
mA
Negative Supply
5
100
5
85
70
mA
Power Dissipation
6
1.3
1.54
PSRR
7
0.05
%/%
NOTES
1
I
OHPROG
/I
OLPROG
voltage range may be extended to 100 mV due to a possible 1 mA offset current.
2
I
OHRTN
/I
OLRTN
should be connected to V
COM
to minimize power dissipation.
3
V
DUT
= 2 V to +7 V, C
TOTAL
= 10 pF, R
DUT
= 10
. For inhibit leakage tests, V
DUT
= 0 V to +5.9 V, I
OH
= 4 mA, I
OL
= +4 mA, T
CASE
= +36
C.
4
Measured from the ECL crossing to the 10% change in the output current.
5
I
PROGRAM
=
50 mA.
6
Maximum power dissipation with +V
S
= +10 V, V
S
= 5.2 V, I
PROGRAM
50 mA, V
COM
= V
DUT
= 0 V.
7
For a 1% change in +V
S
or V
S
, the output current may change a maximum of 0.05% of Full Scale Range (FSR).
Specifications subject to change without notice.
AD1315
3
REV. A
ABSOLUTE MAXIMUM RATINGS
1
Power Supply Voltage
+V
S
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V
V
S
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V
Difference from +V
S
to V
S
. . . . . . . . . . . . . . . . . . . . . 16 V
Inputs
Difference from INH to
INH . . . . . . . . . . . . . . . . . . . . . 5 V
INH,
INH . . . . . . . . . . . . . . . . . . +V
S
13.4 V, V
S
+ 11 V
V
COM
, V
DUT
. . . . . . . . . . . . . . . +V
S
13.1 V, V
S
+ 13.2 V
I
OL
, I
OH
Program Voltage . . . . . . . . +V
S
15 V, V
S
+ 15 V
Operating Temperature Range . . . . . . . . . . . . . . . 0 to +70
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +125
C
Lead Temperature Range (Soldering 20 sec)
2
. . . . . . . +300
C
Pin
No.
Symbol
Function
1
I
OLRTN
Logic Low Current Return
2
V
COM
Communication Voltage
3
V
DUT
Load/Dot Connection
4
V
S
Negative Supply
5
I
OHRTN
Logic High Current Return
6
I
OLPROG
Logic Low Current Program Voltage
7
LID
Lid Connection (Internal)
8
GND
Ground
9
I
OHPROG
Logic High Current Program Voltage
10
N/C
No Connection
11
N/C
No Connection
12
N/C
No Connection
13
+V
S
Positive Supply
14
INH
Inhibit
15
INH
Inhibit
16
N/C
No Connection
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
To ensure lead coplanarity (
0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in an environment at
24
C,
5
C (75
F,
10
F) with relative humidity not to exceed 65%.
CONNECTION DIAGRAM
SUGGESTED PAD LOCATION
Dimensions shown in inches and (mm).
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option*
AD1315KZ
0 to +70
C
16-Lead Gull Wing
Z-16B
*Z = Leaded Chip Carrier (Ceramic).
AD1315
4
REV. A
DEFINITION OF TERMS
Gain
The measured transconductance.
Gain
=
I
OUT
(@ 5V Input )
-
I
OUT
(@ 0.2V Input )
V
PROG
(@ 5V )
-
V
PROG
(@ 0.2V )
where:
V
PROG
values are measured at I
OL
/I
OH
PROG
Gain Error
The difference between the measured transconductance and the
ideal expressed as a % of full-scale range.
Ideal Gain = 10 mA/V
Gain Error
=
Ideal Gain
-
Actual Gain
Ideal Gain
100
Offset Error
Offset Error is measured by setting the I
OHPROG
or I
OLPROG
inputs to 0.2 V and measuring I
OUT
. Since both I
OH
and I
OL
Figure 1. Definition of Terms
Figure 2. Timing Diagram for Inhibit Transition
outputs are unipolar, this small initial offset of 2 mA must be set
to allow for measurement of possible negative offset. With a gain
of 10 mA/V, a 0.2 V input should yield an output of
2 mA. The
difference between the observed output and the ideal
2 mA
output is the offset error.
Offset Error = I
OUT
(@ 0.2 V) Gain V
PROG
(@ 0.2 V)
Linearity Error
The deviation of the transfer function from a straight line de-
fined by Offset and Gain expressed as a % of FSR.
I
OUT
(calc) = Gain V
PROG
(@ set point) + Offset
where:
set point = V
PROG
(from 0.2 V to 5 V)
I
OUT
(FSR) = Gain V
PROG
(@ 5 V) + Offset
Linearity Error
I
OUT
(measured )
-
I
OUT
(calc)
I
OUT
( FSR )
100
Figure 3. I
OL
, I
OH
Offset Current vs.
Temperature
Figure 4. I
OL
, I
OH
Gain Error vs.
Temperature
Figure 5. I
OL
, I
OH
Linearity Error vs.
Current Program Voltage
AD1315
5
REV. A
Figure 6. +I
MAX
, I
MAX
to Inhibit
Propagation Delay vs. Temperature
Figure 7. Inhibit to +I
MAX
, I
MAX
Propagation Delay vs. Temperature
Figure 8. Inhibit Mode Leakage Current vs. Case Temperature
Figure 9. AD1315 DC Test Circuit
Figure 10. AD1315 Propagation Delay Test Circuit