HANBit HDD32M72B9
URL : www.hbe.co.kr 1 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
GENERAL DESCRIPTION
The HDD32M72B9 is a 32M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module.
The module consists of nine CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K
EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each DDR SDRAM. The HDD32M72B9 is a SO-DIMM(Small Outline Dual in line Memory
Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance m emory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
Part Identification
HDD32M72B9
16B : 166MHz (CL=2.5)
HDD32M72B9
13A : 133MHz (CL=2)
HDD32M72B9
13B : 133MHz (CL=2.5)
256MB(32Mx64) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRSM with ECC
2.5V
0.2V VDD and VDDQ power supply
Auto & self refresh capability (8192 Cycles/64ms)
All input and output are compatible with SSTL_2 interface
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Burst type : Sequential & Interleave
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
The used device is 8M x 8bit x 4Banks DDR SDRAM
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial Presence detect with EEPROM
DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks,
8K Ref., ECC Unbuffered SO-DIMM Part No. HDD32M72B9
HANBit HDD32M72B9
URL : www.hbe.co.kr 2 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
PIN ASSIGNMENT
*These pins should be NC in the system which does not support SPD
PIN
PIN DESCRIPTION
PIN
PIN DESCRIPTION
A0~A12
Address input
VDD
Power supply(2.5V)
BA0~BA1
Bank Select Address
VDDQ
Power supply for DQs(2.5V)
DQ0~DQ63(CB0~CB7)
Data input/output
(Check Bit Data In/Out)
VREF
Power supply for reference
DQS0~DQS8
Data Strobe input/output
VDDSPD
Serial EEPROM Power supply(2.3V~3.3V)
DM0~DM8
Data-in Mask
VSS
Ground
CK0~CK2,/CK0~/CK2
Clock input
SA0~SA2
Address in EEPROM
CKE0~CKE1
Clock enable input
SDA
Serial data I/O
/CS0
Chip Select input
SCL
Serial clock
/RAS, /CAS
Row / Column Address strobe
WP
Write protection
NC
No connection
VDDID
VDD identification flag
PIN
Front
PIN
Back
PIN
Frontl
PIN
Back
PIN
Front
PIN
Back
1
VREF
2
VREF
67
DQ27
68
DQ31
133
DQS4
134
DM4
3
VSS
4
VSS
69
VDD
70
VDD
135
DQ34
136
DQ38
5
DQ0
6
DQ4
71
CB0
72
CB4
137
VSS
138
VSS
7
DQ1
8
DQ5
73
CB1
74
CB5
139
DQ35
140
DQ39
9
VDD
10
VDD
75
Vss
76
Vss
141
DQ40
142
DQ44
11
DQS0
12
DM0
77
DQS8
78
DM8
143
VDD
144
VDD
13
DQ2
14
DQ6
79
CB2
80
CB6
145
DQ41
146
DQ45
15
VSS
16
VSS
81
VDD
82
VDD
147
DQS5
148
DM5
17
DQ3
18
DQ7
83
CB3
84
CB7
149
VSS
150
VSS
19
DQ8
20
DQ12
85
NC
86
NC(/RESET)
151
DQ42
152
DQ46
21
VDD
22
VDD
87
VSS
88
VSS
153
DQ43
154
DQ47
23
DQ9
24
DQ13
89
CK2
90
VSS
155
VDD
156
VDD
25
DQS1
26
DM1
91
/CK2
92
VDD
157
VDD
158
/CK1
27
VSS
28
VSS
93
VDD
94
VDD
159
VSS
160
CK1
29
DQ10
30
DQ14
95
CKE1
96
CKE0
161
VSS
162
VSS
31
DQ11
32
DQ15
97
NC(A13)
98
NC (BA2)
163
DQ48
164
DQ52
33
VDD
34
VDD
99
A12
100
A11
165
DQ49
166
DQ53
35
CK0
36
VDD
101
A9
102
A8
167
VDD
168
VDD
37
/CK0
38
VSS
103
VSS
104
VSS
169
DQS6
170
DM6
39
VSS
40
VSS
105
A7
106
A6
171
DQ50
172
DQ54
41
DQ16
42
DQ20
107
A5
108
A4
173
VSS
174
VSS
43
DQ17
44
DQ21
109
A3
110
A2
175
DQ51
176
DQ55
45
VDD
46
VDD
111
A1
112
A0
177
DQ56
178
DQ60
47
DQS2
48
DM2
113
VDD
114
VDD
179
VDD
180
VDD
49
DQ18
50
DQ22
115
A10/AP
116
BA1
181
DQ57
182
DQ61
51
VSS
52
VSS
117
BA0
118
/RAS
183
DQS7
184
DM7
53
DQ19
54
DQ23
119
/WE
120
/CAS
185
VSS
186
VSS
55
DQ24
56
DQ28
121
/CS0
122
NC
187
DQ58
188
DQ62
57
VDD
58
VDD
123
NC
124
NC
189
DQ59
190
DQ63
59
DQ25
60
DQ29
125
VSS
126
VSS
191
VDD
192
VDD
61
DQS3
62
DM3
127
DQ32
128
DQ36
193
SDA
194
*SA0
63
VSS
64
VSS
129
DQ33
130
DQ37
195
SCL
196
*SA1
65
DQ26
66
DQ30
131
VDD
132
VDD
197
VDDSPD 198
*SA2
199
VDDID
200
NC
HANBit HDD32M72B9
URL : www.hbe.co.kr 3 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
FUNCTIONAL BLOCK DIAGRAM
HANBit HDD32M72B9
URL : www.hbe.co.kr 4 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CK, /CK
Clock
CK and CK are differential clock inputs. All address and control input signals are
sam-pled on the positive edge of CK and negative edge of CK. Output (read) data
is referenced to both edges of CK. Internal clock signals are derived from CK/CK.
CKE
Clock Enable
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
except for disabling outputs, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE are disabled during power-down and self refresh modes,
providing low standby power. CKE will recognizean LVCMOS LOW level prior to
VREF being stable on power-up.
/CS
Chip Select
CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the
command code.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
command is being applied.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
Column
address
strobe
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
DQS0 ~ 8
Data Strobe
Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.
DM0~8
Input Data Mask
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. DM pins include dummy loading internally, to matches the
DQ and DQS load-ing.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
CB0 ~ 7
Check Bit
Check Bits for ECC data are multiplexed on the same pins.
VDDQ
Supply
DQ Power Supply : +2.5V
0.2V.
VDD
Supply
Power Supply : +2.5V
0.2V (device specific).
VSS
Supply
DQ Ground.
VREF
Supply
SSTL_2 reference voltage.
VDDSPD
Supply
Serial EEPROM Power Supply : 3.3v
VDDID
VDD identification Flag
HANBit HDD32M72B9
URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd.
REV 1.0 (July. 2003)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNTE
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DDQ
supply relative to Vss
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
8.0
W
Short circuit current
I
OS
50
mA
Notes : Permanent device damage may occur if ABSOLUTE MAXIUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 IN/OUT)
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70
C) )
PARAMETER
SYMBO
L
MIN
MAX
UNIT
NOTE
Supply Voltage
V
DD
2.3
2.7
V
I/O Supply Voltage
V
DDQ
2.3
2.7
V
I/O Reference Voltage
V
REF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination Voltage(system)
V
TT
V
REF
0.04
V
REF
+ 0.04
V
2
Input High Voltage
V
IH
(DC)
V
REF
+ 0.15
V
REF
+ 0.3
V
4
Input Low Voltage
V
IL
(DC)
-0.3
V
REF
- 0.15
V
4
Input Voltage Level, CK and /CK inputs
V
IN
(DC)
-0.3
V
DDQ
+ 0.3
V
Input Differential Voltage, CK and /CK inputs
V
ID
(DC)
0.3
V
DDQ
+ 0.6
V
3
Input leakage current
I
LI
-2
2
uA
5
Output leakage current
I
OZ
-5
5
uA
Output High current (Normal Strenth driver
(V
OUT
= V
TT
+ 0.84V)
I
OH
-16.8
mA
Output Low current (Normal Strenth driver
(V
OUT
= V
TT -
0.84V)
I
OL
16.8
Output High current (Normal Strenth driver
(V
OUT
= V
TT
+ 0.45V)
I
OH
-9
Output Low current (Normal Strenth driver
(V
OUT
= V
TT
- 0.45V)
I
OL
9
mA
Notes :
1. Includes
25mV margin for DC offset on VREF, and a combined total of
50mV margin for all AC noise and DC offset
on VREF,bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal
DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an
inductance of
3nH.
2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to
200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of
the same.
6. These charactericteristics obey the SSTL-2 class II standards.
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