S E M I C O N D U C T O R
5-74
Features
Low Power CMOS Circuitry. . . . . . . . . . 7.5mW (Typ) at
3.2MHz (Max Freq.) at V
DD
= 5V
Baud Rate
- DC to 200K Bits/s (Max) at. . . . . . . . . . . . . . 5V, 85
o
C
- DC to 400K Bits/s (Max) at. . . . . . . . . . . . . . 10V, 85
o
C
4V to 10.5 Operation
Automatic Data Formatting and Status Generation
Fully Programmable with Externally Selectable Word
Length (5 - 8 Bits), Parity Inhibit, Even/Odd Parity, and
1, 1-1/2, or 2 Stop Bits
Operating Temperature Range
- CDP6402D, CD . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
- CDP6402E, CE . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Replaces Industry Type IM6402 and Compatible with
HD6402
Description
The CDP6402 and CDP6402C are silicon gate CMOS
Universal Asynchronous Receiver/Transmitter (UART)
circuits for interfacing computers or microprocessors to
asynchronous serial data channels. They are designed to
provide the necessary formatting and control for interfacing
between serial and parallel data channels. The receiver
converts serial start, data, parity, and stop bits to parallel
data verifying proper code transmission, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds start parity and stop bits.
The data word can be 5, 6, 7 or 8 bits in length. Parity may
be odd, even or inhibited. Stop bits can be 1, 1-1/2, or 2
(when transmitting 5-bit code).
The CDP6402 and CDP6402C can be used in a wide range
of applications including modems, printers, peripherals,
video terminals, remote data acquisition systems, and serial
data links for distributed processing systems.
The CDP6402 and CDP6402C are functionally identical.
They differ in that the CDP6402 has a recommended
operating voltage range of 4V to 10.5V, and the CDP6402C
has a recommended operating voltage range of 4V to 6.5V.
Pinout
(40 LEAD PDIP, SBDIP)
TOP VIEW
Ordering Information
PACK-
AGE
TEMP. RANGE
5V/200K
BAUD
10V/400K
BAUD
PKG.
NO.
PDIP
-40
o
C to +85
o
C
CDP6402CE
CDP6402E
E40.6
Burn-In
CDP6402CEX
-
SBDIP
-40
o
C to +85
o
C
CDP6402CD
CDP6402D
D40.6
Burn-In
CDP6402CDX CDP6402DX
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V
DD
NC
GND
RRD
RBR8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
FE
OE
SFD
RRC
DRR
DR
RRI
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
TRC
EPE
CLS1
CLS2
SBS
PI
CRL
TBR8
TBR7
TBR6
TBR5
TBR4
TBR3
TBR2
TBR1
TRO
TRE
TBRL
TBRE
MR
August 1996
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1996
CDP6402,
CDP6402C
CMOS Universal Asynchronous
Receiver/Transmitter (UART)
File Number
1328.2
5-75
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
STOP
LOGIC
PARITY
LOGIC
THREE
STATE
BUFFERS
RECEIVER REGISTER
RECEIVER BUFFER REGISTER
MULTIPLEXER
RECEIVER
TIMING
AND
CONTROL
START
LOGIC
RRI
RRD
RBR1 (LSB)
RBR8 (MSB)
PE
FE
TBRE
OE
DR
SFD
CONTROL
REGISTER
TRANSMITTER
TIMING
AND
CONTROL
TRANSMITTER REGISTER
TRANSMITTER BUFFER REGISTER
MULTIPLEXER
START
STOP
PARITY
LOGIC
PI
EPE
SBS
TRO
TBR1 (LSB)
TBR8 (MSB)
DRR
RRC
MR
CRL
CLS2
CLS1
TRC
TBRL
TRE
CDP6402, CDP6402C
5-76
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range, (V
DD
)
CDP6402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11V
CDP6402C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
100
A
Device Dissipation Per Output Transistor
For T
A
= Full Package-Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating-Temperature Range (T
A
)
Package Type D (SBDIP) . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Type E (PDIP) . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
55
15
Maximum Storage Temperature Range (T
STG
) . . .-65
o
C to +150
o
C
Maximum Lead Temperature (Soldering 10s):
At Distance 1/16
1/32 inch (1.59
0.79mm) . . . . . . . . . . +265
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
At T
A
= Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so
that operatIon is always within the following ranges:
PARAMETER
LIMITS
UNITS
CDP6402
CDP6402C
MIN
MAX
MIN
MAX
DC Operating Voltage Range
4
10.5
4
6.5
V
Input Voltage Range
V
SS
V
DD
V
SS
V
DD
V
Static Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
10%, Except as noted
PARAMETER
CONDITIONS
LIMITS
UNITS
V
O
(V)
V
IN
(V)
V
DD
(V)
CDP6402
CDP6402C
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
Quiescent Device
Current
I
DD
-
0, 5
5
-
0.01
50
-
0.02
200
A
-
0,10
10
-
1
200
-
-
-
A
Output Low Drive
(Sink) Current
I
OL
0.4
0,5
5
2
4
-
1.2
2.4
-
mA
0.5
0,10
10
5
7
-
-
-
-
mA
Output High Drive
(Source) Current
I
OH
4.6
0, 5
5
-0.55
-1.1
-
-0.55
-1.1
-
mA
9.5
0,10
10
-1.3
-2.6
-
-
-
-
mA
Output Voltage Low-
Level (Note 2)
V
OL
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
Output Voltage
High Level (Note 2)
V
OH
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
Input Low Voltage
V
IL
0.5, 4.5
-
5
-
-
0.8
-
-
0.8
V
0.5, 9.5
-
10
-
-
0.2 V
DD
-
-
-
V
CDP6402, CDP6402C
5-77
Input High Voltage
V
IH
0.5, 4.5
-
5
V
DD
-2
-
-
V
DD
-2
-
-
V
0.5, 9.5
-
10
7
-
-
-
-
-
V
Input Leakage
Current
I
IN
Any
Input
0,5
5
-
10
-4
1
-
-
1
A
0,10
10
-
10
-4
2
-
-
-
A
Three-State Output
Leakage Current
I
OUT
0, 5
0, 5
5
-
10
-4
1
-
10
-4
1
A
0, 10
0,10
10
-
10
-4
10
-
-
-
A
Operating Current
(Note 2)
I
DD1
-
0, 5
5
-
1.5
-
-
1.5
-
mA
-
0,10
10
-
10
-
-
-
-
mA
Input Capacitance
C
IN
-
-
-
-
5
7.5
-
5
7.5
pF
Output Capacitance
C
OUT
-
-
-
-
10
15
-
10
15
pF
NOTES:
1. Typical values are for T
A
= 25
o
C and nominal V
DD
2. I
OL
= I
OH
= 1
A.
3. Operating current is measured at 200kHz or V
DD
= 5V and 400kHz for V
DD
= 10V, with open outputs (worst-case frequencies for
CDP1802A system operating at maximum speed of 3.2MHz).
Static Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
10%, Except as noted (Continued)
PARAMETER
CONDITIONS
LIMITS
UNITS
V
O
(V)
V
IN
(V)
V
DD
(V)
CDP6402
CDP6402C
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
CDP6402, CDP6402C
5-78
Description of Operation
Initialization and Controls
A positive pulse on the MASTER RESET (MR) input resets
the control, status, and receiver buffer registers, and sets the
serial output (TRO) High. Timing is generated from the clock
inputs RRC and TRC at a frequency equal to 16 times the
serial data bit rate. The RRC and TRC inputs may be driven
by a common clock, or may be driven independently by two
different clocks. The CONTROL REGISTER LOAD (CRL)
input is strobed to load control bits for PARITY INHIBIT (PI),
EVEN PARITY ENABLE (EPE), STOP BIT SELECTS (SBS),
and CHARACTER LENGTH SELECTS (CLS1 and CLS2).
These inputs may be hand wired to V
SS
or V
DD
with CRL to
V
DD
. When the initialization is completed, the UART is ready
for receiver and/or transmitter operations.
Transmitter Operation
The transmitter section accepts parallel data, formats it, and
transmits it in serial form (Figure 2) on the TRO terminal.
Transmitter timing is shown in Figure 3. (A) Data is loaded
into the transmitter buffer register from the inputs TBR1
through TBR8 by a logic low on the TBRL input. Valid data
must be present at least t
DT
prior to, and t
TD
following, the
rising edge of TBRL. If words less than 8-bits are used, only
the least significant bits are used. The character is right justi-
fied into the least significant bit, TBR1. (B) The rising edge of
TBRL clears TBRE. 1/2 to 11/2 cycles later, depending on
when the TBRL pulse occurs with respect to TRC, data is
transferred to the transmitter register and TRE is cleared.
TBRE is set to a logic High one cycle after that.
Output data is clocked by TRC. The clock rate is 16 times
the data rate. (C) A second pulse on TBRL loads data into
the transmitter buffer register. Data transfer to the transmitter
register is delayed until transmission of the current character
is complete. (D) Data is automatically transferred to the
transmitter register and transmission of that character
begins.
Receiver Operation
Data is received in serial form at the RRl input. When no
data is being received, RRI input must remain high. The data
is clocked through the RRC. The clock rate is 16 times the
data rate. Receiver timing is shown in Figure 4.
(A) A low level on DRR clears the DR line. (B) During the first
stop bit data is transferred from the receiver register to the
RB Register. If the word is less than 8 bits, the unused most
significant bits will be a logic low. The output character is
right justified to the least significant bit RBR1. A logic high on
OE indicates overruns. An overrun occurs when DR has not
been cleared before the present character was transferred to
the RBR. (C) 1/2 clock cycle later DR is set to a logic high
and FE is evaluated. A logic high on FE indicates an invalid
stop bit was received. A logic high on PE indicates a parity
error.
Start Bit Detection
The receiver uses a 16X clock for timing (Figure 5). The start
bit could have occurred as much as one clock cycle before it
was detected, as indicated by the shaded portion. The cen-
ter of the start bit is defined as clock count 7 1/2. If the
receiver clock is a symmetrical square wave, the center of
the start bit will be located within
1/2 clock cycle
1/32 bit or
3.125%. The receiver begins searching for the next start bit
at 9 clocks into the first stop bit.
FIGURE 2. SERIAL DATA FORMAT
5 - 8 DATA BITS
1, 1-1/2 OR
2 STOP BITS
START
BIT
LSB
MSB
PARITY
IF ENABLED
FIGURE 3. TRANSMITTER TIMING WAVEFORMS
END OF
LAST
STOP BIT
1/2 TO 1-1/2 CYCLES
A
1 TO 2 CYCLES
1-1/2 TO 2-1/2 CYCLES
1/2
CLOCK
B
C
D
TBRL
TBRE
TRE
TRO
DATA
FIGURE 4. RECEIVER TIMING WAVEFORMS
A
B
C
FE, PE
BEGINNING OF FIRST STOP BIT
8 1/2 TO 9 1/2
CLOCK CYCLES
DR
DRR
RBRI-8, OE
RRI
1/2 CLOCK
CYCLES
FIGURE 5. START BIT TIMING WAVEFORMS
A
START
7 1/2 CLOCK
CYCLES
8 1/2 CLOCK
CYCLES
RRI
INPUT
CLOCK
COUNT 7 1/2
DEFINED CENTER
OF START BIT
CDP6402, CDP6402C
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