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Электронный компонент: DG200AA/883B

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CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright
Harris Corporation 1993
9-13
S E M I C O N D U C T O R
DG200, DG201
CMOS Dual/Quad SPST Analog Switches
Description
The DG200 and DG201 solid state analog gates are
designed using an improved, high voltage CMOS monolithic
technology. They provide ease-of-use and performance
advantages not previously available from solid state
switches. Destructive latch-up of solid state analog gates
has been eliminated by Harris's CMOS technology.
The DG200 and DG201 are completely specification and
pinout compatible with the industry standard devices.
Ordering Information
PART NUMBER
TEMPERATURE
PACKAGE
DG200AA
-55
o
C to +125
o
C
10 Pin Metal Can
DG200AK
-55
o
C to +125
o
C
14 Lead Ceramic DIP
DG200BA
-25
o
C to +85
o
C
10 Pin Metal Can
DG200BK
-25
o
C to +85
o
C
14 Lead Ceramic DIP
DG200CJ
0
o
C to +70
o
C
14 Lead Plastic DIP
DG200AA/883B
-55
o
C to +125
o
C
10 Pin Metal Can
DG200AK/883B
-55
o
C to +125
o
C
14 Lead Ceramic DIP
DG201AK
-55
o
C to +125
o
C
16 Lead Ceramic DIP
DG201BK
-25
o
C to +85
o
C
16 Lead Ceramic DIP
DG201CJ
0
o
C to +70
o
C
16 Lead Plastic DIP
DG201AK/883B
-55
o
C to +125
o
C
16 Lead Ceramic DIP
Features
Switches Greater than 28V
P-P
Signals with
15 Supplies
Break-Before-Make Switching t
OFF
250ns, t
ON
700ns
Typical
TTL, DTL, CMOS, PMOS Compatible
Non-Latching with Supply Turn-Off
Complete Monolithic Construction
Industry Standard (DG200, DG201)
Applications
Data Acquisition
Sample and Hold Circuits
Operational Amplifier Gain Switching Networks
December 1993
Pinouts
DG200
(CDIP, PDIP)
TOP VIEW
DG200
(TO-100 METAL CAN)
TOP VIEW
DG201
(CDIP, PDIP)
TOP VIEW
IN
2
NC
GND
NC
S
2
D
2
V-
IN
1
NC
V+ (SUBSTRATE)
NC
S
1
D
1
V
REF
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
D
1
D
2
S
2
IN
2
2
5
1
3
10
4
8
9
7
6
S
1
V
REF
V-
GND
IN
1
(SUBSTRATE AND CASE)
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
1
D
1
S
1
V-
GND
S
4
IN
4
D
4
IN
2
S
2
V+(SUBSTRATE)
V
REF
S
3
D
3
IN
3
D
2
File Number
3115
9-14
DG200, DG201
Schematic Diagram
(
1
/
2
DG200,
1
/
4
DG201)
Functional Diagram
DG200, DG201 SWITCH CELL
Q3
V
REF
INPUT
GATE
PROTECTION
RESISTOR
Q4
V-
Q7
V+
Q8
Q5
Q10
Q12
V+
Q13
Q11
D
1
S
1
Q14
Q6
V-
Q9
Q15
Q1
Q2
N
P
IN
S
D
9-15
Specifications DG200
Absolute Maximum Ratings
Thermal Information
V+, V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ - V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
V
D
- V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
V
D
- V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V
V
IN
- GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
Thermal Resistance
JA
JC
Ceramic DIP Package . . . . . . . . . . . . . . .
95
o
C/W
24
o
C/W
Plastic DIP Package . . . . . . . . . . . . . . . .
100
o
C/W
-
Metal Can Package . . . . . . . . . . . . . . . . .
136
o
C/W
65
o
C/W
Operating Temperature Range
"A" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
"B" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25
o
C to +85
o
C
"C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
(T
A
= +25
o
C, V+ = +15V, V- = -15V)
PARAMETER
TEST CONDITIONS
MILITARY
COMMERCIAL / INDUSTRIAL
UNITS
-55
o
C
+25
o
C
+125
o
C
0
o
C TO
-25
o
C
+25
o
C
+70
o
C TO
+85
o
C
Input Logic Current,
I
IN(ON)
V
IN
= 0.8V (Notes 2, 3)
10
1
10
-
10
10
A
Input Logic Current,
I
N(OFF)
V
IN
= 2.4V (Notes 2, 3)
10
1
10
-
10
10
A
Drain-Source On Resis-
tance, r
DS(ON)
I
S
= 10mA, V
ANALOG
=
10V
70
70
100
80
80
100
Channel-to-Channel
r
DS(ON)
Match, r
DS(ON)
-
25 (Typ)
-
-
30 (Typ)
-
Minimum Analog Signal
Handling Capability,
V
ANALOG
-
15V
-
-
15V
-
V
Switch OFF Leakage
Current, I
D(OFF)
V
ANALOG
= -14V to +14V
-
2
100
-
5
100
nA
Switch OFF Leakage
Current, I
S(OFF)
V
ANALOG
= -14V to +14V
-
2
100
-
5
100
nA
Switch ON Leakage Cur-
rent, I
D(ON)
+ I
S(ON)
V
D
= V
S
= -14V to +14V
-
2
200
-
10
200
nA
Switch "ON" Time
(Note 1), t
ON
R
L
= 1k
, V
ANALOG
=
-10V to +10V (Figure 5)
-
1.0
-
-
1.0
-
s
Switch "OFF" Time, t
OFF
R
L
= 1k
, V
ANALOG
=
-10V to +10V (Figure 5)
-
0.5
-
-
0.5
-
s
Charge Injection, Q
(INJ.)
Figure 6
-
15 (Typ)
-
-
20 (Typ)
-
mV
Minimum Off Isolation
Rejection Ratio, OIRR
f = 1MHz, R
L
= 100
,
C
L
5pF
(Figure 7, Note 1)
-
54 (Typ)
-
-
50 (Typ)
-
dB
+Power Supply
Quiescent Current, I
V1
V
IN
= 0V or V
IN
= 5V
1000
1000
2000
1000
1000
2000
A
-Power Supply
Quiescent Current, I
V2
1000
1000
2000
1000
1000
2000
A
Minimum Channel to
Channel Cross Coupling
Rejection Ratio, CCRR
One Channel Off
-
54 (Typ)
-
-
50 (Typ)
-
dB
NOTES:
1. Pull Down Resistor must be
2k
.
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the
minimum range for switching properly. Peak input current required for transition is typically -120
A.
9-16
Specifications DG201
Absolute Maximum Ratings
Thermal Information
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ to V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
V
D
to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
V
D
to V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V
V
REF
to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V
V
REF
to V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
V
IN
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30mA
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
Thermal Resistance
JA
JC
Ceramic DIP Package . . . . . . . . . . . . . . .
80
o
C/W
24
o
C/W
Plastic DIP Package . . . . . . . . . . . . . . . .
145
o
C/W
-
Operating Temperature Range
"A" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
"B" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25
o
C to +85
o
C
"C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
(T
A
= +25
o
C, V+ = +15V, V- = -15V)
PARAMETER
TEST CONDITIONS
MILITARY
COMMERCIAL / INDUSTRIAL
UNITS
-55
o
C
+25
o
C
+125
o
C
0
o
C TO
-25
o
C
+25
o
C
+70
o
C TO
+85
o
C
Input Logic Current,
I
IN(ON)
V
IN
= 0.8V (Note 1)
10
1
10
1
1
10
A
Input Logic Current,
I
N(OFF)
V
IN
= 2.4V (Note 1)
10
1
10
1
1
10
A
Drain-Source On Resis-
tance, r
DS(ON)
I
S
= 10mA, V
ANALOG
=
10V
80
80
125
100
100
125
Channel-to-Channel
r
DS(ON)
Match, r
DS(ON)
-
25 (Typ)
-
-
30 (Typ)
-
Minimum Analog Signal
Handling Capability,
V
ANALOG
-
15 (Typ)
-
-
15 (Typ)
-
V
Switch OFF Leakage
Current, I
D(OFF)
V
ANALOG
= -14V to +14V
-
1
100
-
5
100
nA
Switch OFF Leakage
Current, I
S(OFF)
V
ANALOG
= -14V to +14V
-
1
100
-
5
100
nA
Switch ON Leakage Cur-
rent, I
D(ON)
+ I
S(ON)
V
D
= V
S
= -14V to +14V
-
2
200
-
5
200
nA
Switch "ON" Time
(Note 2), t
ON
R
L
= 1k
, V
ANALOG
=
-10V to +10V (Figure 5)
-
1.0
-
-
1.0
-
s
Switch "OFF" Time
(Note 2), t
OFF
R
L
= 1k
, V
ANALOG
=
-10V to +10V (Figure 5)
-
0.5
-
-
0.5
-
s
Charge Injection, Q
(INJ.)
Figure 6
-
15 (Typ)
-
-
20 (Typ)
-
mV
Minimum Off Isolation
Rejection Ratio, OIRR
f = 1MHz, R
L
= 100
,
C
L
5pF, (Figure 7)
-
54 (Typ)
-
-
50 (Typ)
-
dB
+Power Supply
Quiescent Current, I+
Q
V
IN
= 0V or V
IN
= 5V
2000
1000
2000
2000
1000
2000
A
-Power Supply
Quiescent Current, I-
Q
2000
1000
2000
2000
1000
2000
A
Minimum Channel to
Channel Cross Coupling
Rejection Ratio, CCRR
One Channel Off
-
54 (Typ)
-
-
50 (Typ)
-
dB
NOTES:
1. Typical values are for design aid only, not guaranteed and not subject to production testing.
2. All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the
minimum range for switching properly. Peak input current required for transition is typically -120
A.
9-17
DG200, DG201
Performance Curves
FIGURE 1. R
DS(ON)
vs V
D
AND TEMPERATURE
FIGURE 2. r
DS(ON)
vs V
D
AND POWER SUPPLY VOLTAGE
FIGURE 3. I
D(ON)
vs TEMPERATURE
FIGURE 4. I
S(OFF)
OR I
D(OFF)
vs TEMPERATURE
100
50
0
-15
-10
-5
0
5
10
15
DRAIN SOURCE ON RESIST
ANCE (
)
DRAIN VOLTAGE (V)
+125
o
C
+25
o
C
-55
o
C
V+ = +15V
V- = -15V
100
50
0
-15
-10
-5
0
5
10
15
DRAIN SOURCE ON RESIST
ANCE (
)
DRAIN VOLTAGE (V)
A
B
C
D
A: V+ = +15V, V- = -15V
B: V+ = +12V, V- = -12V
C: V+ = +10V, V- = -10V
D: V+ = +8V, V- = -8V
10
1
0.1
0.01
CHANNEL ON LEAKAGE CURRENT (nA)
25
45
65
85
105
125
TEMPERATURE (
o
C)
10
1
0.1
0.01
SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA)
25
45
65
85
105
125
TEMPERATURE (
o
C)
DG201 (16 LEAD DIP)
PIN
SYMBOL
DESCRIPTION
1
IN
1
Logic control for switch 1
2
D
1
Drain (output) terminal for switch 1
3
S
1
Source (input) terminal for switch 1
4
V-
Negative power supply terminal
5
GND
Ground terminal (Logic Common)
6
S
4
Source (input) terminal for switch 4
7
D
4
Drain (output) terminal for switch 4
8
IN
4
Logic control for switch 4
9
IN
3
Logic control for switch 3
10
D
3
Drain (output) terminal for switch 3
11
S
3
Source (input) terminal for switch 3
12
V
REF
Logic reference voltage
13
V+
Positive power supply terminal (substrate)
14
S
2
Source (input) terminal for switch 2
15
D
2
Drain (output) terminal for switch 2
16
IN
2
Logic control for switch 2
Pin Description
DG200 (14 LEAD DIP)
PIN
SYMBOL
DESCRIPTION
1
IN
2
Logic control for switch 2
2
NC
No Connection
3
GND
Ground Terminal (Logic Common)
4
NC
No Connection
5
S
2
Source (input) terminal for switch 2
6
D
2
Drain (output) terminal for switch 2
7
V-
Negative power supply terminal
8
V
REF
Logic reference voltage
9
D
1
Drain (output) terminal for switch 1
10
S
1
Source (input) terminal for switch 1
11
NC
No Connection
12
V+
Positive power supply terminal (substrate)
13
NC
No Connection
14
IN
1
Source (input) terminal for switch 1
9-18
DG200, DG201
Test Circuits
FIGURE 5.
FIGURE 6.
FIGURE 7.
0V
3V
LOGIC
INPUT
ANALOG
INPUT 10V
2k
10pF
V
OUT
1k
NOTE: All channels are turned off by high "1" logic inputs and
all channels are turned on by low "0" inputs; however 0.8V to
2.4V describes the minimum range for switching properly.
Peak input current required for transition is typically -120
A.
0V
3V
LOGIC
INPUT
ANALOG
INPUT 10V
10,000pF
V
OUT
V
OUT
100
2V
P-P
AT 1MHz
LOGIC
INPUT *
51
* Pull Down Resistor must be
2k
.
Typical Applications
Using the V
REF
Terminal
The DG200 and DG201 have an internal voltage divider set-
ting the TTL threshold on the input control lines for V+ equal
to +15V. The schematic shown in Figure 8 with nominal
resistor values, gives approximately 2.4V on the V
REF
pin.
As the TTL input signal goes from +0.8V to +2.4V, Q1 and
Q2 switch states to turn the switch ON and OFF.
FIGURE 8.
V+ (+15V)
Q1
31k
V
REF
6k
R
EXT
Q2
GATE
PROTECTION
RESISTOR
INPUT
If the power supply voltage is less than +15V, then a resistor
must be added between V+ and the V
REF
pin, to restore
+2.4V at V
REF
. The table shows the value of this resistor for
various supply voltages, to maintain TTL compatibility. If
CMOS logic levels on a +5V supply are being used, the
threshold shifts are less critical, but a separate column of
suitable values is given in the table. For logic swings of -5V
to + 5V, no resistor is needed.
In general, the "low" logic level should be <0.8V to prevent
Q1 and Q2 from both being ON together (this will cause
incorrect switch function).
TABLE 1.
V+ SUPPLY (V)
TTL RESISTOR
(k
)
CMOS RESISTOR
(k
)
+15
-
-
+12
100
-
+10
51
-
+9
(34)
34
+8
(27)
27
+7
18
18
9-19
DG200
Metallization Topology
DIE DIMENSIONS:
74 x 77 x 14
1mils
METALLIZATION:
Type: Al
Thickness: 10k
1k
GLASSIVATION:
Type: SiO
2
/Si
3
N
4
SiO
2
Thickness: 7k
1.4k
Si
3
N
4
Thickness: 8k
1.2k
WORST CASE CURRENT DENSITY:
1 x 10
5
A/cm
2
Metallization Mask Layout
DG200
S
1
(10)
V- (SUBSTRATE)* (12)
V-
(7)
D
1
(9)
(5) S
2
(6)
(14)
IN
1
(1)
IN
2
(3)
GND
D
2
* Backside of Chip is V+
9-20
DG201
Metallization Topology
DIE DIMENSIONS:
94 x 101 x 14
1mils
METALLIZATION:
Type: Al
Thickness: 10k
1k
GLASSIVATION:
Type: SiO
2
/Si
3
N
4
SiO
2
Thickness: 7k
1.4k
Si
3
N
4
Thickness: 8k
1.2k
WORST CASE CURRENT DENSITY:
1 x 10
5
A/cm
2
Metallization Mask Layout
DG201
S
1
(3)
V- (4)
GND (5)
S
4
(6)
IN
2
(16)
IN
1
(1)
D
1
(2)
(11) S
3
(13) V+ (SUBSTRATE)*
(14) S
2
(15)
(7)
D
4
(8)
IN
4
(9)
IN
3
(10)
D
3
D
2
* Backside of Chip is V+