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Электронный компонент: HM5117400BLTS-7

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This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
HM5117400B Series
4,194,304-word 4-bit Dynamic Random Access Memory
ADE-203-369A (Z)
Rev. 1.0
Nov. 15, 1995
Description
The Hitachi HM5117400B is a CMOS dynamic RAM organized 4,194,304 word 4 bit. It employs the most
advanced CMOS technology for high performance and low power. The HM5117400B offers Fast Page Mode
as a high speed access mode.
Features
Single 5 V ( 10%)
High speed
Access time : 60 ns/ 70 ns/ 80 ns (max)
Low power dissipation
Active mode
: 605 mW/550 mW/495 mW(max)
Standby mode : 11 mW (max)
: 0.83 mW (max) (L-version)
Fast page mode capability
Long refresh period
2048 refresh cycles : 32 ms
: 128 ms (L-version)
3 variations of refresh
-only refresh
-before-
refresh
Hidden refresh
Battery backup operation (L-version)
Test function
16-bit parallel test mode
HM5117400B Series
2
Ordering Information
Type No.
Access Time
Package
HM5117400BS-6
HM5117400BS-7
HM5117400BS-8
60 ns
70 ns
80 ns
300-mil 26-pin plastic SOJ (CP-26/24DB)
HM5117400BLS-6
HM5117400BLS-7
HM5117400BLS-8
60 ns
70 ns
80 ns
HM5117400BTS-6
HM5117400BTS-7
HM5117400BTS-8
60 ns
70 ns
80 ns
300-mil 26-pin plastic TSOP II (TTP-26/24DA)
HM5117400BLTS-6
HM5117400BLTS-7
HM5117400BLTS-8
60 ns
70 ns
80 ns
Pin Arrangement
26
25
24
23
22
21
19
18
17
16
15
14
1
2
3
4
5
6
8
9
10
11
12
13
V
I/O1
I/O2
NC
A10
A0
A1
A2
A3
V
CC
CC
V
I/O4
I/O3
A9
A8
A7
A6
A5
A4
V
SS
SS
V
I/O1
I/O2
NC
A10
A0
A1
A2
A3
V
CC
CC
V
I/O4
I/O3
A9
A8
A7
A6
A5
A4
V
SS
SS
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
HM5117400BS/BLS Series
HM5117400BTS/BLTS Series
(Top view)
(Top view)
HM5117400B Series
3
Pin Description
Pin Name
Function
A0 to A10
Address input
A0 to A10
Refresh address input
I/O1 to I/O4
Data input/data output
Row address strobe
Column address strobe
Write enable
Output enable
V
CC
Power supply (+5 V)
V
SS
Ground
NC
No connection
HM5117400B Series
4
Block Diagram
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
256k memory cell array
Sense amp. & I/O bus
Column decoder & driver
Column decoder & driver
I/O
Buffer 1
I/O 1
I/O
Buffer 2
I/O 2
I/O
Buffer 4
I/O 4
I/O
Buffer 3
I/O 3
Address A0 to A10
HM5117400B Series
5
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
T
1.0 to +7.0
V
Supply voltage relative to V
SS
V
CC
1.0 to +7.0
V
Short circuit output current
Iout
50
mA
Power dissipation
P
T
1.0
W
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Recommended DC Operating Conditions (Ta = 0 to +70 C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
CC
4.5
5.0
5.5
V
1
Input high voltage
V
IH
2.4
--
6.5
V
1
Input low voltage
V
IL
1.0
--
0.8
V
1
Note:
1. All voltage referred to V
SS
DC Characteristics (Ta = 0 to +70 C, V
CC
= 5 V 10%, V
SS
= 0 V)
HM5117400B
-6
-7
-8
Parameter
Symbol Min
Max Min
Max Min
Max Unit Test Conditions
Operating current
*1, *2
I
CC1
--
110
--
100
--
90
mA
t
RC
= min
Standby current
I
CC2
--
2
--
2
--
2
mA
TTL interface
,
= V
IH
Dout = High-Z
--
1
--
1
--
1
mA
CMOS interface
,
V
CC
0.2V
Dout = High-Z
Standby current
(L-version)
I
CC2
--
150
--
150
--
150
A
CMOS interface
,
V
CC
0.2V
Dout = High-Z