HM5118165 Series
16 M EDO DRAM (1-Mword
16-bit)
1 k Refresh
ADE-203-636D (Z)
Rev. 4.0
Nov. 1997
Description
The Hitachi HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word
16-bit. It employs the
most advanced 0.5
m CMOS technology for high performance and low power. The HM5118165 offers
Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ
and 50-pin plastic TSOP II.
Features
Single 5 V (
10%)
Access time : 50 ns/60 ns/70 ns (max)
Power dissipation
Active mode
: 1045 mW/935 mW/825 mW (max)
Standby mode : 11 mW (max)
: 0.83 mW (max) (L-version)
EDO page mode capability
Refresh cycles
1024 refresh cycles : 16 ms
: 128 ms (L-version)
4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
2CAS-byte control
Battery backup operation (L-version)
HM5118165 Series
2
Ordering Information
Type No.
Access time
Package
HM5118165J-5
HM5118165J-6
HM5118165J-7
50 ns
60 ns
70 ns
400-mil 42-pin plastic SOJ (CP-42D)
HM5118165LJ-5
HM5118165LJ-6
HM5118165LJ-7
50 ns
60 ns
70 ns
HM5118165TT-5
HM5118165TT-6
HM5118165TT-7
50 ns
60 ns
70 ns
400-mil 50-pin plastic TSOP II (TTP-50/44DC)
HM5118165LTT-5
HM5118165LTT-6
HM5118165LTT-7
50 ns
60 ns
70 ns
HM5118165 Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
I/O0
I/O1
I/O2
I/O3
V
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
CC
CC
V
I/O15
I/O14
I/O13
I/O12
V
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
SS
SS
HM5118165J/LJ Series
(Top view)
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
CC
CC
CC
SS
SS
SS
V
I/O15
I/O14
I/O13
I/O12
V
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
V
I/O0
I/O1
I/O2
I/O3
V
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
HM5118165TT/LTT Series
(Top view)
Pin Description
Pin name
Function
A0 to A9
Address input
-- Row/Refresh address
-- Column address
A0 to A9
A0 to A9
I/O0 to I/O15
Data input/Data output
RAS
Row address strobe
UCAS
,
LCAS
Column address strobe
WE
Read/Write enable
OE
Output enable
V
CC
Power supply
V
SS
Ground
NC
No connection
HM5118165 Series
4
Block Diagram
A0
A1
to
A9
Timing and control
Column
address
buffers
Row
address
buffers
I/O buffers
I/O0
to
I/O15
Column decoder
Row decoder
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
RAS
UCAS LCAS
WE
OE
HM5118165 Series
5
Truth Table
RAS
LCAS
UCAS
WE
OE
Output
Operation
H
D
D
D
D
Open
Standby
L
L
H
H
L
Valid
Lower byte Read cycle
L
H
L
H
L
Valid
Upper byte
L
L
L
H
L
Valid
Word
L
L
H
L
*2
D
Open
Lower byte Early write cycle
L
H
L
L*
2
D
Open
Upper byte
L
L
L
L*
2
D
Open
Word
L
L
H
L*
2
H
Undefined
Lower byte Delayed write cycle
L
H
L
L*
2
H
Undefined
Upper byte
L
L
L
L*
2
H
Undefined
Word
L
L
H
H to L
L to H
Valid
Lower byte Read-modify-write cycle
L
H
L
H to L
L to H
Valid
Upper byte
L
L
L
H to L
L to H
Valid
Word
L
H
H
D
D
Open
Word
RAS
-only refresh cycle
H to L
H
L
D
D
Open
Word
CAS
-before-
RAS
refresh cycle or
H to L
L
H
D
D
Open
Word
Self refresh cycle (L-version)
H to L
L
L
D
D
Open
Word
L
L
L
H
H
Open
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. t
WCS
0 ns Early write cycle
t
WCS
< 0 ns Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS
. (Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.)
However write OPERATION and output High-Z control are done independently by each
UCAS
,
LCAS
.
ex. if
RAS
= H to L,
UCAS
= H,
LCAS
= L, then
CAS
-before-
RAS
refresh cycle is selected.
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