HM5264165F-75/A60/B60
HM5264805F-75/A60/B60
HM5264405F-75/A60/B60
64M LVTTL interface SDRAM
133 MHz/100 MHz
1-Mword
16-bit
4-bank/2-Mword
8-bit
4-bank
/4-Mword
4-bit
4-bank
PC/133,
PC/100 SDRAM
ADE-203-940B (Z)
Rev. 1.0
Nov. 10, 1999
Description
The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word
16-bit
4 bank. The Hitachi
HM5264805F is a 64-Mbit SDRAM organized as 2097152-word
8-bit
4 bank. The Hitachi HM5264405F
is a 64-Mbit SDRAM organized as 4194304-word
4-bit
4 bank. All inputs and outputs are referred to the
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed
RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
2
Programmable
CAS latency: 2/3
Byte control by DQM: DQM (HM5264805F/HM5264405F)
DQMU/DQML (HM5264165F)
Refresh cycles: 4096 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No.
Frequency
CAS
latency
Package
HM5264165FTT-75*
1
HM5264165FTT-A60
HM5264165FTT-B60
*2
133 MHz
100 MHz
100 MHz
3
2/3
3
400-mil 54-pin plastic TSOP II (TTP-54D)
HM5264165FLTT-75
*1
HM5264165FLTT-A60
HM5264165FLTT-B60
*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264805FTT-75
*1
HM5264805FTT-A60
HM5264805FTT-B60
*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264805FLTT-75
*1
HM5264805FLTT-A60
HM5264805FLTT-B60
*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264405FTT-75
*1
HM5264405FTT-A60
HM5264405FTT-B60
*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264405FLTT-75
*1
HM5264405FLTT-A60
HM5264405FLTT-B60
*2
133 MHz
100 MHz
100 MHz
3
2/3
3
Note:
1. 100 MHz operation at
CAS
latency = 2.
2. 66 MHz operation at
CAS
latency = 2.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
3
Pin Arrangement (HM5264165F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
54-pin TSOP
(Top view)
Pin Description
Pin name
Function
Pin name
Function
A0 to A13
Address input
WE
Write enable
Row address A0 to A11
DQMU/DQML Input/output mask
Column address A0 to A7
CLK
Clock input
Bank select address A12/A13 (BS) CKE
Clock enable
DQ0 to DQ15
Data-input/output
V
CC
Power for internal circuit
CS
Chip select
V
SS
Ground for internal circuit
RAS
Row address strobe command
V
CC
Q
Power for DQ circuit
CAS
Column address strobe command
V
SS
Q
Ground for DQ circuit
NC
No connection
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
4
Pin Arrangement (HM5264805F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
54-pin TSOP
(Top view)
Pin Description
Pin name
Function
Pin name
Function
A0 to A13
Address input
WE
Write enable
Row address A0 to A11
DQM
Input/output mask
Column address A0 to A8
CLK
Clock input
Bank select address A12/A13 (BS) CKE
Clock enable
DQ0 to DQ7
Data-input/output
V
CC
Power for internal circuit
CS
Chip select
V
SS
Ground for internal circuit
RAS
Row address strobe command
V
CC
Q
Power for DQ circuit
CAS
Column address strobe command
V
SS
Q
Ground for DQ circuit
NC
No connection
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
5
Pin Arrangement (HM5264405F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SS
Q
NC
DQ3
V
CC
Q
NC
NC
V
SS
Q
NC
DQ2
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
54-pin TSOP
(Top view)
Pin Description
Pin name
Function
Pin name
Function
A0 to A13
Address input
WE
Write enable
Row address A0 to A11
DQM
Input/output mask
Column address A0 to A9
CLK
Clock input
Bank select address A12/A13 (BS) CKE
Clock enable
DQ0 to DQ3
Data-input/output
V
CC
Power for internal circuit
CS
Chip select
V
SS
Ground for internal circuit
RAS
Row address strobe command
V
CC
Q
Power for DQ circuit
CAS
Column address strobe command
V
SS
Q
Ground for DQ circuit
NC
No connection
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