HM628512B Series
4 M SRAM (512-kword
8-bit)
ADE-203-903D (Z)
Rev. 3.0
Aug. 24, 1999
Description
The Hitachi HM628512B is a 4-Mbit static RAM organized 512-kword
8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.35
m Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP,
is available for high density mounting. The HM628512B is suitable for battery backup system.
Features
Single 5 V supply
Access time: 55/70 ns (max)
Power dissipation
Active: 50 mW/MHz (typ)
Standby: 10
W (typ)
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly TTL compatible: All inputs and outputs
Battery backup operation
HM628512B Series
2
Ordering Information
Type No.
Access time
Package
HM628512BLP-5
HM628512BLP-7
55 ns
70 ns
600-mil 32-pin plastic DIP (DP-32)
HM628512BLP-5SL
HM628512BLP-7SL
55 ns
70 ns
HM628512BLP-5UL
HM628512BLP-7UL
55 ns
70 ns
HM628512BLFP-5
HM628512BLFP-7
55 ns
70 ns
525-mil 32-pin plastic SOP (FP-32D)
HM628512BLFP-5SL
HM628512BLFP-7SL
55 ns
70 ns
HM628512BLFP-5UL
HM628512BLFP-7UL
55 ns
70 ns
HM628512BLTT-5
HM628512BLTT-7
55 ns
70 ns
400-mil 32-pin plastic TSOP II (TTP-32D)
HM628512BLTT-5SL
HM628512BLTT-7SL
55 ns
70 ns
HM628512BLTT-5UL
HM628512BLTT-7UL
55 ns
70 ns
HM628512BLRR-5
HM628512BLRR-7
55 ns
70 ns
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
HM628512BLRR-5SL
HM628512BLRR-7SL
55 ns
70 ns
HM628512BLRR-5UL
HM628512BLRR-7UL
55 ns
70 ns
HM628512B Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SS
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
CC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SS
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
CC
(Top view)
HM628512BLP Series
HM628512BLFP Series
HM628512BLTT Series
HM628512BLRR Series
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A18
Address input
I/O0 to I/O7
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
V
CC
Power supply
V
SS
Ground
HM628512B Series
4
Block Diagram
I/O0
I/O7
CS
WE
OE
A13 A17A15A8
A10
A11
V
V
CC
SS
Row
Decoder
Memory Matrix
1,024 4,096
Column I/O
Column Decoder
Input
Data
Control
Timing Pulse Generator
Read/Write Control
A5
A9
A4
A18
A16
A1
A0
A2
A12
A14
A3
A7
A6
HM628512B Series
5
Function Table
WE
CS
OE
Mode
V
CC
current
Dout pin
Ref. cycle
H
Not selected
I
SB
, I
SB1
High-Z
--
H
L
H
Output disable
I
CC
High-Z
--
H
L
L
Read
I
CC
Dout
Read cycle
L
L
H
Write
I
CC
Din
Write cycle (1)
L
L
L
Write
I
CC
Din
Write cycle (2)
Note:
: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage
V
CC
0.5 to +7.0
V
Voltage on any pin relative to V
SS
V
T
0.5*
1
to V
CC
+ 0.3*
2
V
Power dissipation
P
T
1.0
W
Operating temperature
Topr
20 to +70
C
Storage temperature
Tstg
55 to +125
C
Storage temperature under bias
Tbias
20 to +85
C
Notes: 1. 3.0 V for pulse half-width
30 ns
2. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = 20 to +70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
4.5
5.0
5.5
V
V
SS
0
0
0
V
Input high voltage
V
IH
2.2
--
V
CC
+ 0.3
V
Input low voltage
V
IL
0.3
*1
--
0.8
V
Note:
1. 3.0 V for pulse half-width
30 ns
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