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Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi's Sales Dept. regarding specification.
HM628512C Series
4 M SRAM (512-kword
8-bit)
ADE-203-1212 (Z)
Preliminary
Rev. 0.0
Sep. 12, 2000
Description
The Hitachi HM628512C is a 4-Mbit static RAM organized 512-kword
8-bit. It realizes higher density,
higher performance and low power consumption by employing Hi-CMOS process technology. The device,
packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is
available for high density mounting. The HM628512C is suitable for battery backup system.
Features
Single 5 V supply
Access time: 55/70 ns (max)
Power dissipation
Active: 50 mW/MHz (typ)
Standby: 10
W (typ)
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly TTL compatible: All inputs and outputs
Battery backup operation
HM628512C Series
2
Ordering Information
Type No.
Access time
Package
HM628512CLP-5
HM628512CLP-7
55 ns
70 ns
600-mil 32-pin plastic DIP (DP-32)
HM628512CLP-5SL
HM628512CLP-7SL
55 ns
70 ns
HM628512CLFP-5
HM628512CLFP-7
55 ns
70 ns
525-mil 32-pin plastic SOP (FP-32D)
HM628512CLFP-5SL
HM628512CLFP-7SL
55 ns
70 ns
HM628512CLTT-5
HM628512CLTT-7
55 ns
70 ns
400-mil 32-pin plastic TSOP II (TTP-32D)
HM628512CLTT-5SL
HM628512CLTT-7SL
55 ns
70 ns
HM628512CLRR-5
HM628512CLRR-7
55 ns
70 ns
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
HM628512CLRR-5SL
HM628512CLRR-7SL
55 ns
70 ns
HM628512C Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SS
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
CC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SS
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
CC
(Top view)
32-pin DIP
32-pin SOP
32-pin TSOP
32-pin TSOP (reverse)
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A18
Address input
I/O0 to I/O7
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
V
CC
Power supply
V
SS
Ground
HM628512C Series
4
Block Diagram
I/O0
I/O7
CS
WE
OE
A3 A2A1A0
A6
A5
V
V
CC
SS
Row
Decoder
Memory Matrix
2,048 2,048
Column I/O
Column Decoder
Input
Data
Control
Timing Pulse Generator
Read/Write Control
A4
A7
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
LSB
MSB
LSB
MSB
HM628512C Series
5
Function Table
WE
CS
OE
Mode
V
CC
current
Dout pin
Ref. cycle
H
Not selected
I
SB
, I
SB1
High-Z
--
H
L
H
Output disable
I
CC
High-Z
--
H
L
L
Read
I
CC
Dout
Read cycle
L
L
H
Write
I
CC
Din
Write cycle (1)
L
L
L
Write
I
CC
Din
Write cycle (2)
Note:
: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage
V
CC
0.5 to +7.0
V
Voltage on any pin relative to V
SS
V
T
0.5*
1
to V
CC
+ 0.3*
2
V
Power dissipation
P
T
1.0
W
Operating temperature
Topr
20 to +70
C
Storage temperature
Tstg
55 to +125
C
Storage temperature under bias
Tbias
20 to +85
C
Notes: 1. V
T
min: 3.0 V for pulse half-width
30 ns.
2. Maximum voltage is 7.0 V.
Recommended DC Operating Conditions (Ta = 20 to +70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
4.5
5.0
5.5
V
V
SS
0
0
0
V
Input high voltage
V
IH
2.2
--
V
CC
+ 0.3
V
Input low voltage
V
IL
0.3
*1
--
0.8
V
Note:
1. V
IL
min: 3.0 V for pulse half-width
30 ns.
HM628512C Series
6
DC Characteristics (Ta = 20 to +70
C, V
CC
= 5 V
10% , V
SS
= 0 V)
Parameter
Symbol
Min
Typ*
1
Max
Unit
Test conditions
Input leakage current
|I
LI
|
--
--
1
A
Vin = V
SS
to V
CC
Output leakage current
|I
LO
|
--
--
1
A
CS
= V
IH
or
OE
= V
IH
or
WE
= V
IL
, V
I/O
= V
SS
to V
CC
Operating power supply current: DC
I
CC
--
8
15
mA
CS
= V
IL
,
others = V
IH
/V
IL
, I
I/O
= 0 mA
Operating power supply current
I
CC1
--
40
60
mA
Min cycle, duty = 100%
CS
= V
IL
, others = V
IH
/V
IL
I
I/O
= 0 mA
Operating power supply current
I
CC2
--
10
20
mA
Cycle time = 1
s,
duty = 100%
I
I/O
= 0 mA,
CS
0.2 V
V
IH
V
CC
0.2 V, V
IL
0.2 V
Standby power supply current: DC
I
SB
--
1
3
mA
CS
= V
IH
Standby power supply current (1): DC I
SB1
--
2*
2
100*
2
A
Vin
0 V,
CS
V
CC
0.2 V
--
2*
3
50*
3
A
Output low voltage
V
OL
--
--
0.4
V
I
OL
= 2.1 mA
Output high voltage
V
OH
2.4
--
--
V
I
OH
= 1.0 mA
Notes: 1. Typical values are at V
CC
= 5.0 V, Ta = +25
C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
Capacitance (Ta = +25
C, f = 1 MHz)
Parameter
Symbol
Typ
Max
Unit
Test conditions
Input capacitance*
1
Cin
--
8
pF
Vin = 0 V
Input/output capacitance*
1
C
I/O
--
10
pF
V
I/O
= 0 V
Note:
1. This parameter is sampled and not 100% tested.
HM628512C Series
7
AC Characteristics (Ta = 20 to +70
C, V
CC
= 5 V
10%, unless otherwise noted.)
Test Conditions
Input pulse levels: 0.8 V to 2.4 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.5 V
Output load: 1 TTL Gate + C
L
(100 pF) (HM628512C-7)
1 TTL Gate + C
L
(50 pF) (HM628512C-5)
(Including scope & jig)
Read Cycle
HM628512C
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
55
--
70
--
ns
Address access time
t
AA
--
55
--
70
ns
Chip select access time
t
CO
--
55
--
70
ns
Output enable to output valid
t
OE
--
25
--
35
ns
Chip selection to output in low-Z
t
LZ
10
--
10
--
ns
2
Output enable to output in low-Z
t
OLZ
5
--
5
--
ns
2
Chip deselection to output in high-Z
t
HZ
0
20
0
25
ns
1, 2
Output disable to output in high-Z
t
OHZ
0
20
0
25
ns
1, 2
Output hold from address change
t
OH
10
--
10
--
ns
HM628512C Series
8
Write Cycle
HM628512C
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
55
--
70
--
ns
Chip selection to end of write
t
CW
50
--
60
--
ns
4
Address setup time
t
AS
0
--
0
--
ns
5
Address valid to end of write
t
AW
50
--
60
--
ns
Write pulse width
t
WP
40
--
50
--
ns
3, 12
Write recovery time
t
WR
0
--
0
--
ns
6
WE
to output in high-Z
t
WHZ
0
20
0
25
ns
1, 2, 7
Data to write time overlap
t
DW
25
--
30
--
ns
Data hold from write time
t
DH
0
--
0
--
ns
Output active from output in high-Z
t
OW
5
--
5
--
ns
2
Output disable to output in high-Z
t
OHZ
0
20
0
25
ns
1, 2, 7
Notes: 1. t
HZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
WP
) of a low
CS
and a low
WE
. A write begins at the later
transition of
CS
going low or
WE
going low. A write ends at the earlier transition of
CS
going high
or
WE
going high. t
WP
is measured from the beginning of write to the end of write.
4. t
CW
is measured from
CS
going low to the end of write.
5. t
AS
is measured from the address valid to the beginning of write.
6. t
WR
is measured from the earlier of
WE
or
CS
going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the
CS
low transition occurs simultaneously with the
WE
low transition or after the
WE
transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If
CS
is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with
OE
low fixed, t
WP
must satisfy the following equation to avoid a problem of
data bus contention. t
WP
t
DW
min + t
WHZ
max
HM628512C Series
9
Timing Waveforms
Read Timing Waveform (
WE = V
IH
)
t
AA
t
CO
t
RC
t
LZ
t
OE
t
OLZ
t
HZ
t
OHZ
Valid Data
Address
CS
OE
Dout
t
OH
HM628512C Series
10
Write Timing Waveform (1) (
OE Clock)
t
WC
t
CW
t
WP
t
AS
t
OHZ
t
DW
t
DH
t
AW
t
WR
*8
Address
OE
CS
WE
Dout
Din
Valid Data
HM628512C Series
11
Write Timing Waveform (2) (
OE Low Fixed)
Address
CS
WE
Dout
Din
t
WC
t
CW
t
WR
t
AW
t
WP
t
AS
t
WHZ
t
OW
t
OH
t
DW
t
DH
*11
*9
*10
*8
Valid Data
HM628512C Series
12
Low V
CC
Data Retention Characteristics (Ta = 20 to +70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*
3
V
CC
for data retention
V
DR
2
--
--
V
CS
V
CC
0.2 V, Vin
0 V
Data retention current
I
CCDR
--
1*
4
50*
1
A
V
CC
= 3.0 V, Vin
0 V
CS
V
CC
0.2 V
--
1*
4
15*
2
A
Chip deselect to data retention time
t
CDR
0
--
--
ns
See retention waveform
Operation recovery time
t
R
t
RC
*
5
--
--
ns
Notes: 1. For L-version and 20
A (max.) at Ta = 20 to +40
C.
2. For L-SL-version and 3
A (max.) at Ta = 20 to +40
C.
3.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. In data retention mode, Vin
levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
4. Typical values are at V
CC
= 3.0 V, Ta = +25
C and specified loading, and not guaranteed.
5. t
RC
= read cycle time.
Low V
CC
Data Retention Timing Waveform (
CS Controlled)
V
CC
4.5 V
2.2 V
0 V
CS
t
CDR
t
R
CS
V
CC
0.2 V
V
DR
Data retention mode
HM628512C Series
13
Package Dimensions
HM628512CLP Series (DP-32)
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
DP-32
--
Conforms
5.1 g
Unit: mm
0.51 Min
2.54 Min
5.08 Max
0.25
+ 0.11
0.05
2.54
0.25
0.48
0.10
0
15
41.90
42.50 Max
13.4
13.7 Max
15.24
32
17
1
16
2.30 Max
1.20
HM628512C Series
14
Package Dimensions (cont.)
HM628512CLFP Series (FP-32D)
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
FP-32D
Conforms
--
1.3 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.15
M
*0.40
0.08
20.45
1.00 Max
1.27
11.30
1.42
3.00 Max
*0.22
0.05
20.95 Max
32
17
1
16
0
8
0.80
0.20
14.14
0.30
0.10
0.38
0.06
+ 0.12
0.10
0.15
0.20
0.04
HM628512C Series
15
Package Dimensions (cont.)
HM628512CLTT Series (TTP-32D)
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-32D
Conforms
--
0.51 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
1.27
0.21
M
*0.42
0.08
0.10
10.16
20.95
21.35 Max
17
16
32
1
1.20 Max
0
5
0.13
0.05
*0.17
0.05
11.76
0.20
0.50
0.10
1.15 Max
0.80
0.40
0.06
0.125
0.04
HM628512C Series
16
Package Dimensions (cont.)
HM628512CLRR Series (TTP-32DR)
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-32DR
Conforms
--
0.51 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
1.27
0.21
M
*0.42
0.08
0.10
10.16
20.95
21.35 Max
16
17
1
32
1.20 Max
0
5
0.13
0.05
*0.17
0.05
11.76
0.20
0.50
0.10
1.15 Max
0.80
0.40
0.06
0.125
0.04
HM628512C Series
17
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
Hitachi Asia Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
URL
NorthAmerica
: http://semiconductor.hitachi.com/
Europe
: http://www.hitachi-eu.com/hel/ecg
Asia
: http://www.hitachi.com.sg/grp3/sicd
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd.
Taipei Branch Office
3rd Flr, Hung Kuo Building, No.167,
Tun Hwa North Road, Taipei (105)
Taiwan
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 23222 HAS-TP
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Group III (Electronic Components)
7th Flr, North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
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Electronic Components Group.
Whitebrook Park
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Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 585160
Hitachi Europe GmbH
Electronic Components Group
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D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
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(America) Inc.
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San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
For further information write to:
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