Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi's Sales Dept. regarding specifications.
HM62G18512 Series
8M Synchronous Fast Static RAM
(512k-word
18-bit)
ADE-203-1185 (Z)
Preliminary
Rev. 0.0
Jun. 12, 2000
Description
The HM62G18512 is a synchronous fast static RAM organized as 512-kword
18-bit. It has realized high
speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-
bump BGA.
Note:
All power supply and ground pins must be connected for proper operation of the device.
Features
Power supply: 3.3 V +10%, 5%
Clock frequency: 200 MHz to 250 MHz
Internal self-timed late write
Byte write control (2 byte write selects, one for each 9-bit)
Optional
36 configuration
HSTL compatible I/O
Programmable impedance output drivers
User selective input trip-point
Differential, HSTL clock inputs
Asynchronous
G output control
Asynchronous sleep mode
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Protocol: Single clock register-register mode
HM62G18512 Series
2
Ordering Information
Type No.
Access time
Cycle time
Package
HM62G18512BP-4
HM62G18512BP-5
2.1 ns
2.5 ns
4.0 ns
5.0 ns
119-bump 1. 27 mm
14 mm
22 mm BGA (BP-119A)
Pin Arrangement
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ SA0
SA6
NC
SA4
SA2 VDDQ
NC
NC
SA7
NC
SA8 SA18 NC
NC SA13 SA3 VDD SA5
SA1
NC
DQb0 NC
VSS
ZQ
VSS DQa4 NC
NC DQb1 VSS
SS
VSS
NC DQa5
VDDQ NC
VSS
G
VSS DQa6 VDDQ
NC DQb2
SWEb
NC
NC DQa7
DQb3 NC
VSS
NC
VSS DQa8 NC
VDDQ VDD VREF VDD VREF VDD VDDQ
NC DQb8 VSS
K
VSS
NC DQa3
DQb7 NC
K SWEa
DQa2 NC
VDDQ DQb6 VSS
SWE
VSS
NC VDDQ
DQb5 NC
VSS SA16 VSS DQa1 NC
NC DQb4 VSS SA14 VSS
NC DQa0
NC
SA9
M1
VDD
M2 SA10 NC
NC SA17 SA11 NC SA12 SA15
ZZ
VDDQ TMS
TDI
TCK TDO
NC VDDQ
(Top view)
VSS
VSS
119-bumps BGA
HM62G18512 Series
3
Pin Description
Name
I/O type
Descriptions
Notes
V
DD
Supply
Core power supply
V
SS
Supply
Ground
V
DDQ
Supply
Output power supply
V
REF
Supply
Input reference: provides input reference voltage
K
Input
Clock input. Active high.
K
Input
Clock input. Active low.
SS
Input
Synchronous chip select
SWE
Input
Synchronous write enable
SAn
Input
Synchronous address input
n = 0, 1, 2...18
SWEx
Input
Synchronous byte write enables
x = a, b
G
Input
Asynchronous output enable
ZZ
Input
Power down mode select
ZQ
Input
Output impedance control
1
DQxn
I/O
Synchronous data input/output
x = a, b
n = 0, 1, 2...8
M1, M2
Input
Output protocol mode select
TMS
Input
Boundary scan test mode select
TCK
Input
Boundary scan test clock
TDI
Input
Boundary scan test data input
TDO
Output
Boundary scan test data output
NC
--
No connection
M1
M2
Protocol
Notes
V
SS
V
DD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to V
SS
via a resistance RQ where 150
RQ
300
, if ZQ = V
DDQ
or
open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120
between ZQ and V
SS
.
2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either V
DD
or V
SS
respectively. The state of the Mode control inputs must be set before power-up and must not
change during device operation. Mode control inputs are not standard inputs and may not meet
V
IH
or V
IL
specification. This SRAM is tested only in the synchronous register to register
operation.
HM62G18512 Series
4
Block Diagram
A0 to A18
JTAG
register
JTAG
register
JTAG
register
JTAG
register
JTAG
register
JTAG
register
JTAG
register
JTAG
register
JTAG
register
JTAG tap
controller
R-Add
register
SS
register
SWE
register
SWEx
register
W-Add
register
SS
SWE
SWEx
G
ZZ
V
REF
ZQ
TDI
TCK
TMS
TDO
DQa0-8
DQb0-8
K
K
MUX
Row decoder
Multiplex
19
2
18
2
19
19
1
WRC
DOC
D-out
register
OB
D-in
register
WA
SA
Match
Column decoder
Memory
cell array
(512k
18)
CLK
control
Impedance
contorol logic
HM62G18512 Series
5
Operation Table
ZZ
SS
G
SWE SWEa SWEb
K
K
Operation
DQ (n)
DQ (n + 1)
H
sleep mode
High-Z
High-Z
L
H
L-H
H-L
Dead
(not selected)
High-Z
L
H
Dead
(Dummy read)
High-Z
High-Z
L
L
L
H
L-H
H-L
Read
Dout
(a,b)0-8
L
L
L
L
L
L-H
H-L
Write a, b byte
High-Z
Din (a,b)0-8
L
L
L
L
H
L-H
H-L
Write a byte
High-Z
Din (a)0-8
L
L
L
H
L
L-H
H-L
Write b byte
High-Z
Din (b)0-8
Notes: 1.
means don't care for synchronous inputs, and H or L for asynchronous inputs.
2.
SWE
,
SS
,
SWEa
to
SWEb
, SA are sampled at the rising edge of K clock.
3. Although differential clock operation is implied, this SRAM will operate properly with one clock
phase (either K or
K
) tied to V
REF
. Under such single-ended clock operation, all parameters
specified within this document will be met.
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