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HM658512A Series

4 M PSRAM (512-kword

8-bit)

2 k Refresh

ADE-203-218C(Z)

Rev. 3.0

Nov. 1997

Description

The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword

8-bit. It realizes higher

density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process
technology.

It offers low power data retention by self refresh mode. It also offers easy non multiplexed address
interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery
back-up systems.

The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8

20 mm TSOP with thickness

of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also
available.

Features

Single 5 V (±10%)

High speed

Access time

CE access time: 70/80/100 ns (max)

Cycle time

Random read/write cycle time:

115/130/160 ns (min)

Low power

Active: 250 mW (typ)

Standby: 200 µW (typ)

Directly TTL compatible

All inputs and outputs

Simple address configuration

Non multiplexed address

Refresh cycle

2048 refresh cycles: 32 ms

HM658512A Series

Easy refresh functions

Address refresh

Automatic refresh

Self refresh

Ordering Information

Type No.

Access time

Package

HM658512ALP-7
HM658512ALP-8
HM658512ALP-10

70 ns
80 ns
100 ns

600-mil 32-pin plastic DIP (DP-32)

HM658512ALP-7V
HM658512ALP-8V
HM658512ALP-10V

70 ns
80 ns
100 ns

HM658512ALFP-7
HM658512ALFP-8
HM658512ALFP-10

70 ns
80 ns
100 ns

525-mil 32-pin plastic SOP (FP-32D)

HM658512ALFP-7V
HM658512ALFP-8V
HM658512ALFP-10V

70 ns
80 ns
100 ns

HM658512ALTT-7
HM658512ALTT-8
HM658512ALTT-10

70 ns
80 ns
100 ns

400-mil 32-pin plastic TSOP (TTP-32D)

HM658512ALTT-7V
HM658512ALTT-8V
HM658512ALTT-10V

70 ns
80 ns
100 ns

HM658512ALRR-7
HM658512ALRR-8
HM658512ALRR-10

70 ns
80 ns
100 ns

400-mil 32-pin plastic TSOP (TTP-32DR)

HM658512ALRR-7V
HM658512ALRR-8V
HM658512ALRR-10V

70 ns
80 ns
100 ns

HM658512A Series

Pin Arrangement

A18

A16

A14

A12

I/O0

I/O1

I/O2

A15

A17

A13

A11

OE/RFSH

A10

I/O7

I/O6

I/O5

I/O4

I/O3

HM658512ALP/ALFP Series

(Top view)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V
A15
A17
WE
A13
A8
A9
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V

HM658512ALTT Series

(Top view)

HM658512A Series

Pin Functions

CE: Chip Enable (Input)

CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high.

A0 to A18: Address Inputs (Input)

A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of

CE.

OE/RFSH: Output Enable/Refresh (Input)

This pin has two functions. Basically it works as

OE when CE is low, and as RFSH when CE is high

(in standby mode). After a read or write cycle finishes, refresh does not start if

CE goes high while

OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when

OE/RFSH goes

low.

I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.

WE: Write Enable (Input)

RAM is in write mode when

WE is low, and is in read mode when WE is high. I/O data is fetched into

RAM by the rising edge of

WE or CE (earlier timing) and the data is written into memory cells.

Refresh

There are three refresh modes : address refresh, automatic refresh and self refresh.

(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one

method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at
least once every 32 ms. In address refresh mode,

OE/RFSH can remain high. In this case, the I/O pins

remain at high impedance, but the refresh is done within RAM.

(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic

refresh mode if

OE/RFSH falls while CE is high and it remains low for at least t

FAP

. One automatic

refresh cycle is executed by one low pulse of

OE/RFSH. It is not necessary to input the refresh

address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.

(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh

starts automatically when

OE/RFSH stays low for more than 8 µs. Refresh addresses are automatically

specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.

Automatic refresh and self refresh are distinguished from each other by the width of the

OE/RFSH low

pulse in standby mode. If the

OE/RFSH low pulse is wider than 8 µs, RAM becomes into self refresh

mode; if the

OE/RFSH low pulse is less than 8 µs, it is recognized as an automatic refresh instruction.

HM658512A Series

At the end of self refresh, refresh reset time (t

RFS

) is required to reset the internal self refresh operation of

the RAM. During t

RFS

CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low

transition of

OE/RFSH at the beginning of automatic refresh must not occur during t

RFS

period.

Notes on Using the HM658512A

Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM's.

(1) If a short

CE pulse of a width less than t

min is applied to RAM, an incomplete read occurs and

stored data may be destroyed. Make sure that

CE low pulses of less than t

min are inhibited. Note

that a 10 ns

CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is

generated by the decoding of higher address signals on the board. Avoid these short pulses.

(2)

OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an

incomplete refresh that will destroy data. Make sure that

OE/RFSH low pulse of less than t

FAP

min are

also inhibited.

(3) t

OHC

and t

OCD

are the timing specs which distinguish the

OE function of OE/RFSH from the RFSH

function. The t

OHC

and t

OCD

specs must be strictly maintained.

(4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100

µs after the power voltage reaches 4.5 V-5.5 V after power-on.

Function Table

RFSH

I/O pin

Mode

Dout

Read

High-Z

Write

High-Z

Refresh

High-Z

Standby

Note:

X means H or L.

HM658512A Series

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Note

Terminal voltage with respect to V

1.0 to +7.0

Power dissipation

1.0

Operating temperature

Topr

0 to +70

Storage temperature

Tstg

55 to +125

Storage temperature under bias

Tbias

10 to +85

Note:

1. With respect to V

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Supply voltage

4.5

5.0

5.5

Input voltage

2.4

6.0

1.0

0.8

Note:

1. V

min = 3.0 V for pulse width 30 ns

HM658512A Series

DC Characteristics (Ta = 0 to +70°C, V

= 5 V ± 10 %, V

= 0 V)

Parameter

Symbol Min

Typ

Max Unit Test conditions

Notes

Operating power supply current I

CC1

I/O

= 0 mA

cyc

= min

Standby power supply current

SB1

= V

, Vin

0 V

RFSH

= V

SB2

200

0.2 V, Vin

0 V,

RFSH

0.2 V

100

0.2 V, Vin

0 V,

RFSH

0.2 V

Operating power supply current
in self refresh mode

CC2

= V

, Vin

0 V,

RFSH

= V

CC3

200

0.2 V, Vin

0 V,

RFSH

0.2 V

100

0.2 V, Vin

0 V,

RFSH

0.2 V

Input leakage current

= 5.5 V, Vin = V

to V

Output leakage current

RFSH

= V

I/O

= V

to V

Output voltage

0.4

= 2.1 mA

2.4

= 1 mA

Notes: 1. Only for L-version.

2. Only for V-version.

Capacitance (Ta = 25°C, f = 1 MHz)

Parameter

Symbol

Typ

Max

Unit

Test conditions

Input capacitance

= 0 V

Input /output capacitance

I/O

= 0 V

Note : This parameter is sampled and not 100% tested.

HM658512A Series

AC Characteristics (Ta = 0 to +70°C, V

= 5 V ± 10%, unless otherwise noted.)

Test Conditions

Input pulse levels: 0.4 V, 2.4 V

Input rise and fall time: 5 ns

Timing measurement level: 0.8 V, 2.2 V

Reference levels: V

= 2.0 V, V

= 0.8 V

Output load: 1 TTL Gate and C

(100 pF) (Including scope and jig)

HM658512A

-7

-8

-10

Parameter

Symbol Min

Max

Min

Max

Min

Max

Unit

Notes

Random read or write cycle time

115

130

160

Chip enable access time

CEA

100

Read-modify- write cycle time

RWC

160

180

220

Output enable access time

OEA

Chip disable to output in high-Z

CHZ

1, 2

Chip enable to output in low-Z

CLZ

Output disable to output in high-Z

OHZ

1, 2

Output enable to output in low-Z

OLZ

Chip enable pulse width

70 n

80 n

100 n 10

Chip enable precharge time

Address setup time

Address hold time

Read command setup time

RCS

Read command hold time

RCH

Write command pulse width

Chip enable to end of write

100

Chip enable to output enable delay
time

OCD

Output enable hold time

OHC

HM658512A Series

AC Characteristics (Ta = 0 to +70°C, V

= 5 V ± 10%, unless otherwise noted.) (cont.)

HM658512A

-7

-8

-10

Parameter

Symbol Min

Max

Min

Max

Min

Max

Unit

Notes

Data in to end of write

Data in hold time for write

Output active from end of write

Write to output in high-Z

WHZ

1, 2

Transition time (rise and fall)

Refresh command delay time

RFD

Refresh precharge time

Refresh command pulse width for
automatic refresh

FAP

70 n

80 n

Automatic refresh cycle time

115

130

160

Refresh command pulse width for
self refresh

FAS

Refresh reset time from self refresh t

RFS

600

Refresh period

REF

2048
cycle

Notes: 1. t

CHZ

, t

OHZ

, t

WHZ

are defined as the time at which the output achieves the open circuit condition.

2. t

CHZ

, t

CLZ

, t

OHZ

, t

OLZ

, t

WHZ

and t

are sampled under the condition of t

= 5 ns and not 100% tested.

3. A write occurs during the overlap of low

and low

. Write end is defined at the earlier of

going high or

going high.

4. If the

low transition occurs simultaneously with or from the

low transition, the output

buffers remain in high impedance state.

5. In write cycle,

must disable output buffers prior to applying data to the device and at

the end of write cycle data inputs must be floated prior to

turning on output buffers.

During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.

6. Transition time t

is measured between V

(min) and V

(max). V

(min) and V

(max) are

reference levels for measuring timing of input signals.

7. After power-up, pause for more than 100

s and execute at least 8 initialization cycles.

8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed

within 15

s after self refresh, in order to meet the refresh specification of 32 ms and 2048

cycles.

9. At the end of self refresh, refresh reset time (t

RFS

) is required to reset the internal self refresh

operation of the RAM. During t

RFS

and

RFSH

must be kept high. If automatic refresh

follows self refresh, low transition of

RFSH

at the beginning of automatic refresh must not

occur during t

RFS

period.

HM658512A Series

Self Refresh Cycle

OE/RFSH

RFD

FAS

RFS

Low V

Data Retention Characteristics (Ta = 0 to +70

This characteristics is guaranteed only for V-version.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

for data retention

3.0

5.5

Self refresh current

CCDR

= 3.0 V,

0.2 V

RFSH

0.2

Vin

0 V

100

= 5.5 V,

0.2 V

RFSH

0.2

Vin

0 V

Refresh setup time

Operation recovery time

HM658512A Series

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of

this document without Hitachi's permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any

other reasons during operation of the user's unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics and

performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.

5. No license is granted by implication or otherwise under any patents or other rights of any third party or

Hitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL

APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.

Hitachi, Ltd.

Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109

For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
U S A
Tel: 800-285-1601
Fax:303-297-0447

Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00

Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160

Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533

Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HM658512ALP-7V