HN29W25611T-50H

256M AND type Flash Memory

More than 16,057-sector (271,299,072-bit)

ADE-203-1178A (Z)

Rev. 1.0

May. 10, 2000

Description

The Hitachi HN29W25611T is a CMOS Flash Memory with AND type multi-level memory cells. It has fully
automatic programming and erase capabilities with a single 3.3 V power supply. The functions are controlled
by simple external commands. To fit the I/O card applications, the unit of programming and erase is as small
as (2048 + 64) bytes. Initial available sectors of HN29W25611T are more than 16,057 (98% of all sector
address) and less than 16,384 sectors.

Features

On-board single power supply (V

): V

= 3.3 V

0.3 V

Organization

AND Flash Memory: (2048 + 64) bytes

(More than 16,057 sectors)

Data register: (2048 + 64) bytes

Multi-level memory cell

2 bit/per memory cell

Automatic programming

Sector program time: 3.0 ms (typ)

System bus free

Address, data latch function

Internal automatic program verify function

Status data polling function

Automatic erase

Single sector erase time: 1.5 ms (typ)

System bus free

Internal automatic erase verify function

Status data polling function

HN29W25611T-50H

Erase mode

Single sector erase ((2048 + 64) byte unit)

Fast serial read access time:

First access time: 50

s (max)

Serial access time: 50 ns (max)

Low power dissipation:

CC2

= 50 mA (max) (Read)

SB2

= 50

A (max) (Standby)

CC3

CC4

= 40 mA (max) (Erase/Program)

SB3

= 5

A (max) (Deep standby)

The following architecture is required for data reliability.

Error correction: more than 3-bit error correction per each sector read

Spare sectors: 1.8% (290 sectors) within usable sectors

Ordering Information

Type No.

Available sector

Package

HN29W25611T-50H

More than 16,057 sectors

12.0

18.40 mm

0.5 mm pitch

48-pin plastic TSOP I (TFP-48D)

HN29W25611T-50H

Pin Arrangement

CDE

RES

RDY/

Busy

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

(Top view)

48-pin TSOP

Pin Description

Pin name

Function

I/O0 to I/O7

Input/output

Chip enable

Output enable

Write enable

CDE

Command data enable

Power supply

Ground

RDY/

Busy

Ready/

Busy

RES

Reset

Serial clock

No connection

Note:

1. All V

and V

pins should be connected to a common power supply and a ground, respectively.

HN29W25611T-50H

Memory Map and Address

3FFFH

3FFEH

3FFDH

0002H

0001H

0000H

000H

2048 bytes

64 bytes

16057 - 16384 sectors *

800H

83FH

Control bytes

2048 + 64 bytes

Column address

Sector address

Address
Sector address

Column address

Cycles
SA (1): First cycle
SA (2): Second cycle
CA (1): First cycle
CA (2): Second cycle

I/O0

A0
A8
A0
A8

I/O1

A1
A9
A1
A9

I/O2

A10

I/O3

A11

I/O4

A12

I/O5

A13

I/O6

I/O7

Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized

by reading the sector valid data written in a part of the column address 800 to 83F
(The specific address is TBD.). The sector valid data must be read and kept outside
of the sector before the sector erase. When the sector is programmed, the sector
valid data should be written back to the sector.

2. An

means "Don't care". The pin level can be set to either V

or V

, referred

to DC characteristics.

HN29W25611T-50H

Pin Function

CE: CE is used to select the device. The status returns to the standby at the rising edge of CE in the reading
operation. However, the status does not return to the standby at the rising edge of

CE in the busy state in

programming and erase operation.

OE: Memory data and status register data can be read, when OE is V

WE: Commands and address are latched at the rising edge of WE.

SC: Programming and reading data is latched at the rising edge of SC.

RES: RES pin must be kept at the V

ILR

0.2 V) level when V

is turned on and off. In this way, data

in the memory is protected against unintentional erase and programming.

RES must be kept at the V

IHR

0.2 V) level during any operations such as programming, erase and read.

CDE: Commands and data are latched when CDE is V

and address is latched when

CDE is V

RDY/

Busy: The RDY/Busy indicates the program/erase status of the flash memory. The RDY/Busy signal

is initially at a high impedance state. It turns to a V

O L

level after the (40H) command in programming

operation or the (B0H) command in erase operation. After the erase or programming operation finishes, the
RDY/

Busy signal turns back to the high impedance state.

I/O0 to I/O7: The I/O pins are used to input data, address and command, and are used to output memory data
and status register data.

Mode Selection

Mode

RES CDE

RDY/

Busy

I/O0 to I/O7

Deep standby

ILR

High-Z

Standby

IHR

High-Z

Output disable

IHR

High-Z

Status register read*

IHR

Status register outputs

Command write*

IHR

Din

Notes: 1. Default mode after the power on is the status register read mode (refer to status transition). From

I/O0 to I/O7 pins output the status, when

= V

and

= V

(conventional read operation

condition).

2. Refer to the command definition. Data can be read, programmed and erased after commands are

written in this mode.

3. The RDY/

Busy

bus should be pulled up to V

to maintain the V

level while the RDY/

Busy

outputs a high impedance.

4. An

means "Don't care". The pin level can be set to either V

or V

referred to DC characteristics.

HN29W25611T-50H

Command Definition*

1, 2

First bus cycle

Second bus cycle

Command

Bus
cycles

Operation
mode*

Data in

Operation
mode

Data in

Data out

Read

Serial read (1) (Without CA)

Write

00H

Write

SA (1)*

(With CA)

3 + 2h*

Write

00H

Write

SA (1)*

Serial read (2)

Write

F0H

Write

SA (1)*

Read identifier codes

Write

90H

Read

ID*

8, 9

Data recovery read

Write

01H

Read

Recovery
data

Auto erase

Single sector

Write

20H

Write

SA (1)*

Auto program Program (1)

(Without
CA*

)

Write

10H

Write

SA (1)*

(With CA*

)

4 + 2h*

Write

10H

Write

SA (1)*

Program (2)*

Write

1FH

Write

SA (1)*

Program (3) (Control bytes)*

Write

0FH

Write

SA (1)*

Program (4)

(WithoutCA*

) 4

Write

11H

Write

SA (1)*

(With CA*

)

4 + 2h*

Write

11H

Write

SA (1)*

Reset

Write

FFH

Clear status register

Write

50H

Data recovery write

Write

12H

Write

SA (1)*

HN29W25611T-50H

Third bus cycle

Fourth bus cycle

Command

Bus
cycles

Operation
mode

Data in

Operation
mode

Data in

Read

Serial read (1) (Without CA)

Write

SA (2)*

(With CA)

3 + 2h*

Write

SA (2)*

Write

CA (1)*

Serial read (2)

Write

SA (2)*

Read identifier codes

Data recovery read

Auto erase

Single sector

Write

SA (2)*

Write

B0H*

Auto program Program (1)

(Without
CA*

)

Write

SA (2)*

Write

40H

*11, 12

(With CA*

)

4 + 2h*

Write

SA (2)*

Write

CA (1)

Program (2)*

Write

SA (2)*

Write

40H

*11, 12

Program (3) (Control bytes)*

Write

SA (2)*

Write

40H

*11, 12

Program (4)

(WithoutCA*

) 4

Write

SA (2)*

Write

40H

*11, 12

(With CA*

)

4 + 2h*

Write

SA (2)*

Write

CA (1)

Reset

Clear status register

Data recovery write

Write

SA (2)*

Write

40H

*11, 12

HN29W25611T-50H

Fifth bus cycle

Sixth bus cycle

Command

Bus
cycles

Operation
mode

Data in

Operation
mode

Data in

Read

Serial read (1) (Without CA)

(With CA)

3 + 2h*

Write

CA (2)*

Serial read (2)

Read identifier codes

Data recovery read

Auto erase

Single sector

Auto program Program (1)

(Without
CA*

)

(With CA*

)

4 + 2h*

Write

CA (2)*

Write

40H

*11, 12

Program (2)*

Program (3) (Control bytes)*

Program (4)

(WithoutCA*

) 4

(With CA*

)

4 + 2h*

Write

CA (2)

Write

40H

*11, 12

Reset

Clear status register

Data recovery write

Notes: 1. Commands and sector address are latched at rising edge of

pulses. Program data is latched

at rising edge of SC pulses.

2. The chip is in the read status register mode when

RES

is set to V

IHR

first time after the power up.

3. Refer to the command read and write mode in mode selection.

4. SA (1) = Sector address (A0 to A7), SA (2) = Sector address (A8 to A13).

5. CA (1) = Column address (A0 to A7), CA (2) = Column address (A8 to A11).

A11 to A0

83FH)

6. The variable h is the input number of times of set of CA (1) and CA (2) (1

2048 + 64).

Set of CA (1) and CA (2) can be input not only one time but free times.

7. By using program (1) and (3), data can additionally be programmed for each sector before erase.

8. ID = Identifier code; Manufacturer code (07H), Device code (99H).

9. The manufacturer identifier code is output when

CDE

is low and the device identifier code is output

when

CDE

is high.

10. Before program (2) operations, data in the programmed sector must be erased.

11. No commands can be written during auto program and erase (when the RDY/

Busy

pin outputs a

12. The fourth or sixth cycle of the auto program comes after the program data input is complete.

HN29W25611T-50H

Mode Description

Read

Serial Read (1): Memory data D0 to D2111 in the sector of address SA is sequentially read. Output data is
not valid after the number of the SC pulse exceeds 2112. When CA is input, memory data D (m) to D (m + j)
in the sector of address SA is sequentially read. Then output data is not valid after the number of the SC pulse
exceeds (2112 to m). The mode turns back to the standby mode at any time when

CE is V

Serial Read (2): Memory data D2048 to D2111 in the sector of address SA is sequentially read. Output data
is not valid after the number of the SC pulse exceeds 64. The mode turns back to the standby mode at any
time when

CE is V

Automatic Erase

Single Sector Erase: Memory data D0 to D2111 in the sector of address SA is erased automatically by
internal control circuits. After the sector erase starts, the erasure completion can be checked through the
RDY/

Busy signal and status data polling. All the bits in the sector are "1" after the erase. The sector valid

data stored in a part of memory data D2048 to D2111 must be read and kept outside of the sector before the
sector erase.

Automatic Program

Program (1): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by
internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into
the sector of address SA automatically by internal control circuits. By using program (1), data can
additionally be programed for each sector before the following erase. When the column is programmed, the
data of the column must be [FF]. After the programming starts, the program completion can be checked
through the RDY/

Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0"

when they are programmed. The sector valid data should be included in the program data PD2048 to PD2111.

Program (2): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by
internal control circuits. After the programming starts, the program completion can be checked through the
RDY/

Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are

programmed. The sector must be erased before programming. The sector valid data should be included in the
program data PD2048 to PD2111.

Program (3): Program data PD2048 to PD2111 is programmed into the sector of address SA automatically
by internal control circuits. By using program (3), data can additionally be programed for each sector befor
the following erase. When the column is programmed, the data of the column must be [FF]. After the
programming starts, the program completion can be checked through the RDY/

Busy signal and status data

polling. Programmed bits in the sector turn from "1" to "0" when they are programmed.

HN29W25611T-50H

Program (4): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by
internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into
the sector of address SA automatically by internal control circuits. By using program (4), data can be
rewritten for each sector before the following erase. So the column data before programming operation are
either "1" or "0". In this mode, E/W number of times must be counted whenever program (4) execute. After
the programming starts, the program completion can be checked through the RDY/

Busy signal and status data

polling. The sector valid data should be included in the program data PD2048 to PD2111.

Memory array

16383

Sector
address

2111

Serial read (1) (Without CA)
Program (1) (Without CA)
Program (2)

16383

Sector
address

2111

Serial read (2)
Program (3)

2048

Memory array

16383

Sector
address

2111

Serial read (1) (With CA)
Program (1) (With CA)

Column address

Memory array

Status Register Read

The status returns to the status register read mode from standby mode, when

CE and OE is V

. In the status

register read mode, I/O pins output the same operation status as in the status data polling defined in the
function description.

Identifier Read

The manufacturer and device identifier code can be read in the identifier read mode. The manufacturer and
device identifier code is selected with

CDE V

and V

, respectively.

HN29W25611T-50H

Data Recovery Read

When the programming was an error, the program data can be read by using data recovery read. When an
additional programming was an error, the data compounded of the program data and the origin data in the
sector address SA can be read. Output data are not valid after the number of SA pulse exeeds 2112. The
mode turns back to the standby mode at any time when

CE is V

. The read data are invalid when addresses

are latched at a rising edge of

WE pulse after the data recovery read command is written.

Data Recovery Write

When the programming into a sector of address SA was an error, the program data can be rewritten
automatically by internal control circuit into the other selected sector of address SA'. In this case, top address
[SA13] of sector of address SA' must be the same as SA. Since the data recovery write mode is internally
Program (4) mode, rewritten sector of address SA' needs no sector erase before rewrite. After the data
recovery write mode starts, the program completion can be checked through the RDY/

Busy signal and the

status data polling.

HN29W25611T-50H

Status Transition

Deep

standby

Power off

Status register

read

Status register

read

Status register

read

00H/F0H

FFH

SA (1), SA (2)

, SC

SC,

CDE

SC,

CDE

SC,

CDE

CA(1)
CA(2)

CA(1)'
CA(2)'

CA(1)
CA(2)

RES

ID read

90H

CDE

Output
disable

Standby

Error

standby

FFH

Sector

Erase setup

Sector

address input

20H

SA (1), SA (2)

Erase

start

B0H

FFH

Erase finish

Status register

read

Program

(1)/(4) setup

Sector address

input

Column address

input

10H
/11H

SA (1),

SA (2)

Program

start

Program

data input

PD0 to
PD2111

PD(m)
to
PD(m+j)

FFH

Program finish

Data recovery

read setup

01H*

Program retry

setup

Sector address

input

12H*

FFH

40H

SA(1)
SA(2)

Data recovery

read

, SC

Read (1) / (2)

setup

Sector address

input

Read (1) / (2)

Column address

input

ID read setup

Status register

read

Program (2)/(3)

setup

Sector address

input

1FH
/0FH

SA (1),

SA (2)

Program

start

Program

data input

PD0 to
PD2111*3

FFH

FFH*

Program finish

BUSY

40H

Output
disable

Status register clear

50H

ERROR

Program error or
Erase error

Notes: 1. (01H)/(12H) Data recovery read/write can be used only for Program (1), (2), (3), (4) errors.

2. When reset is done by

or FFH, error status flag is cleared.

3. When Program (3) mode, input data is PD2048 to PD2111.
4. When Error standby, I

CC3

level is current.

HN29W25611T-50H

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Notes

voltage

0.6 to +7

voltage

All input and output voltages

Vin, Vout

0.6 to +7

1, 2

Operating temperature range

Topr

0 to +70

°C

Storage temperature range

Tstg

65 to +125

°C

Storage temperature under bias

Tbias

10 to +80

°C

Notes: 1. Relative to V

2. Vin, Vout = 2.0 V for pulse width

20 ns.

3. Device storage temperature range before programming.

Capacitance (Ta = 25°C, f = 1 MHz)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Input capacitance

Cin

Vin = 0 V

Output capacitance

Cout

Vout = 0 V

HN29W25611T-50H

DC Characteristics (V

= 3.3 V

0.3 V, Ta = 0 to +70°C)

Parameter

Symbol Min

Typ

Max

Unit

Test conditions

Input leakage current

Vin = V

to V

Output leakage current

Vout = V

to V

Standby V

current

SB1

0.3

= V

SB2

= V

0.2 V,

RES

= V

0.2 V

Deep standby V

current

SB3

RES

= V

0.2 V

Operating V

current

CC1

Iout = 0 mA, f = 0.2 MHz

CC2

Iout = 0 mA, f = 20 MHz

Operating V

current (Program) I

CC3

In programming

Operating V

current (Erase)

CC4

In erase

Input voltage

0.3*

1, 2

0.8

2.0

+ 0.3*

Input voltage (

RES

pin)

ILR

0.2

IHR

0.2 --

+ 0.2

Output voltage

0.4

= 2 mA

2.4

= 2 mA

Notes: 1. V

min = 1.0 V for pulse width

50 ns in the read operation. V

min = 2.0 V for pulse width

ns in the read operation.

2. V

min = 0.6 V for pulse width

20 ns in the erase/data programming operation.

3. V

max = V

+ 1.5 V for pulse width

20 ns. If V

is over the specified maximum value, the

operations are not guaranteed.

AC Characteristics (V

= 3.3 V

0.3 V, Ta = 0 to +70°C)

Test Conditions

Input pulse levels: 0.4 V/2.4 V

Input pulse levels for

RES: 0.2 V/V

0.2 V

Input rise and fall time:

5 ns

Output load: 1 TTL gate + 100 pF (Including scope and jig.)

Reference levels for measuring timing: 0.8 V, 1.8 V

HN29W25611T-50H

Power on and off, Serial Read Mode

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Notes

Write cycle time

CWC

120

Serial clock cycle time

SCC

setup time

CES

hold time

CEH

Write pulse time

= V

Write pulse high time

WPH

Address setup time

Address hold time

Data setup time

Data hold time

SC to output delay

SAC

= V

setup time for SC

OES

low to output low-Z

OEL

setup time before read

OER

250

setup time before

command write

OEWS

SC to output hold

= V

high to output float

= V

to SC delay time

WSD

RES

setup time

SC to

hold time

SOH

SC pulse width

SC pulse low time

SPL

SC setup time for

SCS

CDE

setup time for

CDS

CDE

hold time for

CDH

setup time for

RES

VRS

= V

RES

to V

hold time

VRH

= V

setup time for

RES

CESR

RDY/

Busy

undefined for V

off

DFP

RES

high to device ready

BSY

pulse high time

CPH

200

setup time for

RES

CWRS

RES

hold time

CWRH

HN29W25611T-50H

Program, Erase and Erase Verify

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Note

Write cycle time

CWC

120

Serial clock cycle time

SCC

setup time

CES

hold time

CEH

Write pulse time

Write pulse high time

WPH

Address setup time

Address hold time

Data setup time

Data hold time

setup time before command

write

OEWS

setup time before status

polling

OEPS

setup time before read

OER

250

Time to device busy

150

Time to device busy on read
mode

DBR

Auto erase time

ASE

1.5

10.0

Auto program time
Program(1), (3)

ASP

3.0

20.0

Program(2)

ASP

2.5

20.0

Program(4),
Data recovery write

ASP

3.5

30.0

to SC delay time

WSD

to SC delay time on

recovery read mode

WSDR

pulse high time

CPH

200

SC pulse width

SC pulse low time

SPL

Data setup time for SC

SDS

Data hold time for SC

SDH

CDE

= V

SC setup for

SCS

SC hold time for

SCHW

HN29W25611T-50H

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Note

to output delay

120

to output delay

high to output float

RES

setup time

CDE

setup time for

CDS

CDE

hold time for

CDH

CDE

setup time for SC

CDSS

1.5

CDE

hold time for SC

CDSH

Next cycle ready time

RDY

CDE

hold time

CDOH

CDE

to output delay

CDAC

CDE

to output invalid

CDF

100

setup time for

COS

hold time for

COH

CDE

setup time

CDOS

setup time for SC

OES

low to output low-Z

OEL

SC to output delay

SAC

SC to output hold

RDY/

Busy

setup for SC

200

hold time for

CWH

1.0

hold time for

recovery read mode

CWHR

hold time for

WWH

Busy time on read mode

RBSY

Note:

1. t

is a time after which the I/O pins become open.

HN29W25611T-50H

Serial Read (1) (2) Timing Waveform

CDE

RES

CES

CWC

CEH

CPH

WPH

OER

WPH

SAC

OES

WSD

SCC

SOH

I/O0 to I/O7

SCS

DBR

RBSY

CDS

SAC

CDH

COH

OEL

High-Z

RDY

Busy

D0out/D2048out

D1out/D2049out

D2111out/D2111out

00H
/F0H

SA(1)

Notes: 1. The status returns to the standby at the rising edge of

2. Output data is not valid after the number of the SC pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectively.
3. After any commands are written, the status can return to the standby after the command FFH is input and

turns to the V

level.

OEWS

CDS

CDH

SPL

FFH

SA(2)

Serial Read (1) with CA before SC Timing Waveform

CDE

RES

CES

CWC

CDS

CPH

CEH

CDH

WPH

OER

WPH

SCD

WSD

SCC

OES

WPH

CWC

OEWS

I/O0 to I/O7

SCS

OEL

SAC

RBSY

DBR

OER

SPL

COH

h-1 cycle

High-Z

RDY

Busy

D(n)out

D(n+1)out

D(n+i)out

00H

SA(1)

CA(1)

CA(2)

CA(2)'

CA(1)'

D(m)out

D(m+1)out

D(m+j)out

FFH

Notes: 1. The status returns to the Standby at the rising edge of

2. Output data is not valid after the number of the SC pulse exceeds (2112-n). (i

2111-n, 0

2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j

2111-m, 0

2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and

turns

to the V

level.

5. This interval can be repeated (h-1) cycle. (1

2048 + 64)

OEWS

CDS

CDH

SOH

SPL

OEL

SAC

SA(2)

HN29W25611T-50H

Serial Read (1) with CA after SC Timing Waveform

CDE

RES

CES

CWC

CDS

CPH

CEH

CDH

WPH

OER

SCC

WSD

OES

SCC

OES

OEL

WPH

CWC

OEWS

I/O0 to I/O7

SCS

SAC

SPL

SAC

DBR

RBSY

OER

SPL

COH

h cycle

High-Z

RDY

Busy

D0out

D1out

D(k)out

00H

SA(1)

CA(2)

CA(1)

D(m)out

D(m+1)out

D(m+j)out

FFH

Notes: 1. The status returns to the Standby at the rising edge of

2. Output data is not valid after the number of the SC pulse exceeds 2112. (0

2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j

2111-m, 0

2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and

turns to the V

level.

5. This interval can be repeated h cycle. (1

2048 + 64)

OEWS

CDS

CDH

SOH

OEL

SAC

SA(2)

Erase and Status Data Polling Timing Waveform (Sector Erase)

CDE

RES

CES

CWC

CEH

OEPS

COS

RDY

ASE

WPH

CDH

SCHW

I/O0 to I/O7

SCS

CDS

High-Z

RDY

Busy

IO7 = V

20H

SA(1)

SA(2)

Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/

Busy

outputs a V

2. The status returns to the standby status after RDY/

Busy

returns to High-Z.

OEWS

CDS

CDH

B0H

HN29W25611T-50H

Program (1) and Status Data Polling Timing Waveform

RES

RDY

Busy

CDE

I/O0 to I/O7

CES

OEWS

CWC

WPH

CDS

SCS

CDH

CDSS

SCHW

CDH

SPL

SCC

WPH

CEH

COS

RDY

CWC

OEPS

ASP

40H

10H

PD0

PD1

PD2111

I/O7 = V

SA (1)

SA (2)

High-Z

CDS

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

3. The status returns to the standby status after RDY/

Busy

returns to High-Z.

4. By using program (1), data can be programmed additionally for each sector before erase.

SDH

SDS

HN29W25611T-50H

Program (1) with CA before SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 n).(i

2111 n, 0

2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 m).(j

2111 m, 0

2111)

3. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

4. The status returns to the standby status after RDY/

Busy

returns to High-Z.

5. By using program (1), data can be programmed additionally for each sector before erase.
6. This interval can be repeated (h 1) cycle.(1

2048 + 64)

CES

CDS

CDH

CDSS

CDH

CDSH

SDS

SCC

SDH

CDS

CDSS

SDS

SCS

CEH

COS

CDH

SCHW

OEPS

RDY

CDS

WPH

CWC

OEWS

CWC

WPH

High-Z

High-Z*

10H

SA(1)

SA(2)

CA(1)

CA(2)

CA(1)'

CA(2)'

PD(n) PD(n+1) PD(n+i)*

PD(m) PD(m+1)PD(m+j)*

h1 cycle*

I/O7=V

SDH

SPL

SCC

40H

ASP

Program (1) with CA after SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0

2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 m).(j

2111 m, 0

2111)

3. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

4. The status returns to the standby status after RDY/

Busy

returns to High-Z.

5. By using program (1), data can be programmed additionally for each sector before erase.
6. This interval can be repeated h cycle.(1

2048 + 64)

CES

CDS

CDH

CDSS

CDH

CDSH

SDS

SCC

SDH

CDS

CDSS

SDS

SDH

SCS

CEH

COS

CDH

SCHW

OEPS

RDY

CDS

WPH

CWC

OEWS

CWC

WPH

High-Z

High-Z*

10H

SA(1)

SA(2)

PD0

PD1

CA(1)

CA(2)

PD(k)*

PD(m) PD(m+1)PD(m+j)*

h cycle*

I/O7=V

SPL

SCC

40H

ASP

HN29W25611T-50H

Program (2) and Status Data Polling Timing Waveform

RES

RDY

Busy

CDE

I/O0 to I/O7

CES

OEWS

CWC

WPH

CDS

SCS

CDH

CDSS

SCHW

CDH

SPL

SCC

WPH

CEH

COS

CDS

RDY

CWC

OEPS

ASP

40H

1FH

PD0

PD1

PD2111

I/O7 = V

SA (1)

SA (2)

High-Z

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

3. The status returns to the standby status after RDY/

Busy

returns to High-Z.

4. By using program (2), the programmed data of each sector must be erased before programming next data.

SDH

SDS

HN29W25611T-50H

Program (3) and Status Data Polling Timing Waveform

RES

RDY

Busy

CDE

I/O0 to I/O7

CES

OEWS

CWC

WPH

CDS

SCS

CDH

CDSS

SCHW

CDH

SPL

SCC

CEH

COS

CDS

RDY

CWC

OEPS

ASP

40H

0FH

PD2048 PD2049 PD2111

I/O7 = V

SA (1)

SA (2)

High-Z

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 64.

2. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

3. The status returns to the standby status after RDY/

Busy

returns to High-Z.

4. By using program (3), the data can be programmed additionally for each sector before erase.

SDH

SDS

HN29W25611T-50H

Program (4) and Status Data Polling Timing Waveform

RES

RDY

Busy

CDE

I/O0 to I/O7

CES

OEWS

CWC

WPH

CDS

SCS

DBR

RBSY

CDH

WSD

CDSS

SCHW

CDH

CDS

SPL

SCC

WPH

CEH

COS

RDY

CWC

OEPS

ASP

40H

11H

PD0

PD1

PD2111

I/O7 = V

SA (1)

SA (2)

High-Z

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

3. The status returns to the standby status after RDY/

Busy

returns to High-Z.

4. By using program (4), data can be rewritten for each sector.

SDH

SDS

HN29W25611T-50H

Program (4) with CA before SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 n).(i

2111 n, 0

2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 m).(j

2111 m, 0

2111)

3. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

4. The status returns to the standby status after RDY/

Busy

returns to High-Z.

5. By using program (4), data can be rewritten for each sector.
6. This interval can be repeated (h 1) cycle.(1

2048 + 64)

CES

CDS

CDH

WSD

CDSS

CDH

CDSH

SDS

SCC

SDH

CDS

CDSS

SDS

SCS

DBR

RBSY

CEH

COS

CDH

SCHW

OEPS

RDY

CDS

WPH

CWC

OEWS

CWC

WPH

High-Z

High-Z*

11H

SA(1)

CA(1)

CA(2)

CA(1)'

CA(2)'

PD(n+1) PD(n+i)*

PD(m) PD(m+1)PD(m+j)*

h1 cycle*

I/O7=V

SDH

SPL

SCC

40H

SA(2)

PD(n)

ASP

Program (4) with CA after SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0

2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 m).(j

2111 m, 0

2111)

3. Any commands, including reset command FFH, cannot be input while RDY/

Busy

is V

4. The status returns to the standby status after RDY/

Busy

returns to High-Z.

5. By using program (4), data can be rewritten for each sector.
6. This interval can be repeated h cycle.(1

2048 + 64)

CES

CDS

CDH

WSD

CDSS

CDH

CDSH

SDS

SCC

SDH

CDS

CDSS

SDS

SDH

SCS

DBR

RBSY

CEH

COS

CDH

SCHW

OEPS

RDY

CDS

WPH

CWC

OEWS

CWC

WPH

High-Z

High-Z*

11H

SA(1)

PD1

CA(1)

CA(2)

PD(k)*

PD(m) PD(m+1)PD(m+j)*

h cycle*

I/O7=V

SPL

SCC

40H

SA(2)

PD0

ASP

HN29W25611T-50H

Data Recovery Read Timing Waveform

CDE

RES

CES

CPH

COH

CEH

CDH

WSDR

SCC

SAC

SCC

SOH

I/O0 to I/O7

SCS

OEL

OES

CDS

High-Z

High

RDY

Busy

01H

FFH

D0out

D1out

D2111out

Notes: 1. The status returns to the standby at the rising edge of

2. Output data is not valid after the number of the SC pulse exceed 2112 in the recovery data read mode.
3. After any commands are written, the status can turns to the standby after the command FFH is input

and

turns to the V

level.

OEWS

OER

CWHR

SAC

CDS

CDOS

CDH

SPL

HN29W25611T-50H

Function Description

Status Register: The HN29W25611T outputs the operation status data as follows: I/O7 pin outputs a V

indicate that the memory is in either erase or program operation. The level of I/O7 pin turns to a V

when

the operation finishes. I/O5 and I/O4 pins output V

s to indicate that the erase and program operations

complete in a finite time, respectively. If these pins output V

s, it indicates that these operations have timed

out. When these pins monitor, I/O7 pin must turn to a V

. To execute other erase and program operation,

the status data must be cleared after a time out occurs. From I/O0 to I/O3 pins are reserved for future use.
The pins output V

s and should be masked out during the status data read mode. The function of the status

I/O

Flag definition

Definition

I/O7

Ready/

Busy

= Ready, V

= Busy

I/O6

Reserved

Outputs a V

and should be masked out during the status data poling mode.

I/O5

Erase check

= Fail, V

= Pass

I/O4

Program check

= Fail, V

= Pass

I/O3

Reserved

Outputs a V

and should be masked out during the status data poling mode.

I/O2

Reserved

I/O1

Reserved

I/O0

Reserved

Requirement for System

Specifications

Item

Min

Typ

Max

Unit

Usable sectors (initially)

16,057

16,384

sector

Spare sectors

290

sector

ECC (Error Correction Code)

bit/sector

Program/Erase endurance

cycle

HN29W25611T-50H

Unusable Sector

Initially, the HN29W25611T includes unusable sectors. The unusable sectors must be distinguished from the
usable sectors by the system as follows.

1. Check the partial invalid sectors in the devices on the system. The usable sectors were programmed the
following data. Refer to the flowchart "Indication of unusable sectors".

Initial Data of Usable Sectors

Column address

0H to 81FH

820H

821H

822H

823H

824H

825H

826H to 83FH

Data

FFH

1CH

71H

C7H

1CH

71H

C7H

FFH

2. Do not erase and program to the partial invalid sectors by the system.

Sector number = 0

Read data

Bad sector*

Sector number =

Sector number + 1

Column address = 820H to 825H

Yes

Check data*

Sector number = 16,383

START

END

Notes: 1. Refer to table "Initial data of usable sectors".

2. Bad sectors are installed in system.

Indication of Unusable Sectors

HN29W25611T-50H

Requirements for High System Reliability

The device may fail during a program, erase or read operation due to write or erase cycles. The following
architecture will enable high system reliability if a failure occurs.

1. For an error in read operation: An error correction more than 3-bit error correction per each sector read is

required for data reliability.

2. For errors in program or erase operations: The device may fail during a program or erase operation due to

write or erase cycles. The status register indicates if the erase and program operation complete in a finite
time. When an error happens in the sector, try to reprogram the data into another sector. Avoid further
system access to the sector that error happens. Typically, recommended number of a spare sectors are
1.8% of initial usable 16,057 sectors by each device. If the number of failed sectors exceeds the number
of the spare sectors, usable data area in the device decreases. For the reprogramming, do not use the data
from the failed sectors, because the data from the failed sectors are not fixed. So the reprogram data must
be the data reloaded from outer buffer, or use the Data recovery read mode or the Data recovery write
mode (see the "Mode Description" and under figure "Spare Sectors in Program Error"). To avoid
consecutive sector failures, choose addresses of spare sectors as far as possible from the failed sectors.

HN29W25611T-50H

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual
property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for

maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

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: http://www.hitachi.co.jp/Sicd/index.htm

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Tel: <1> (408) 433-1990
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For further information write to:

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