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Электронный компонент: HN58V1001P-25

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HN58V1001 Series
1M EEPROM (128-kword
8-bit)
Ready/
Busy and RES function
ADE-203-314G (Z)
Rev. 7.0
Oct. 31, 1997
Description
The Hitachi HN58V1001 is a electrically erasable and programmable ROM organized as 131072-word
8-
bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming
function to make the write operations faster.
Features
Single 3 V supply: 2.7 V to 5.5 V
Access time: 250 ns (max)
Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110 W (max)
On-chip latches: address, data,
CE, OE, WE
Automatic byte write: 15 ms (max)
Automatic page write (128 bytes): 15 ms (max)
Data polling and RDY/Busy
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
10
4
erase/write cycles (in page mode)
10 years data retention
Software data protection
Write protection by
RES pin
HN58V1001 Series
2
Ordering Information
Type No.
Access time
Package
HN58V1001P-25
250 ns
600 mil 32-pin plastic DIP (DP-32)
HN58V1001FP-25
250 ns
525 mil 32-pin plastic SOP (FP-32D)
HN58V1001T-25
250 ns
8
14 mm 32-pin plastic TSOP (TFP-32DA)
Pin Arrangement
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
OE
A4
A5
A6
A7
A12
A14
A16
RDY/
Busy
V
CC
A15
RES
WE
A13
A8
A9
A11
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
RES
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/
Busy
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
HN58V1001T Series
HN58V1001P/FP Series
Pin Description
Pin name
Function
A0 to A16
Address input
I/O0 to I/O7
Data input/output
OE
Output enable
CE
Chip enable
WE
Write enable
V
CC
Power supply
V
SS
Ground
RDY/
Busy
Ready busy
RES
Reset
HN58V1001 Series
3
Block Diagram
V
V
OE
CE
A6
A0
A7
A16
WE
CC
SS
I/O0
I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/
Busy
RES
to
to
to
Operation Table
Operation
CE
OE
WE
RES
RDY/
Busy
I/O
Read
V
IL
V
IL
V
IH
V
H
*
1
High-Z
Dout
Standby
V
IH
*
2
High-Z
High-Z
Write
V
IL
V
IH
V
IL
V
H
High-Z to V
OL
Din
Deselect
V
IL
V
IH
V
IH
V
H
High-Z
High-Z
Write Inhibit
V
IH
--
--
V
IL
--
--
Data
Polling
V
IL
V
IL
V
IH
V
H
V
OL
Dout (I/O7)
Program reset
V
IL
High-Z
High-Z
Notes: 1. Refer to the recommended DC operating conditions.
2.
: Don't care
HN58V1001 Series
4
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply voltage relative to V
SS
V
CC
0.6 to +7.0
V
Input voltage relative to V
SS
Vin
0.5*
1
to +7.0
V
Operating temperature range*
2
Topr
0 to +70
C
Storage temperature range
Tstg
55 to +125
C
Notes: 1. Vin min = 3.0 V for pulse width
50 ns
2. Including electrical characteristics and data retention
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
2.7
3.0
5.5
V
V
SS
0
0
0
V
Input voltage
V
IL
0.3*
1
--
0.8
V
V
IH
1.9*
2
--
V
CC
+ 0.3
V
V
H
Vcc
0.5
--
V
CC
+ 1.0
V
Operating temperature
Topr
0
--
70
C
Notes: 1. V
IL
(min): 1.0 V for pulse width
50 ns
2. V
IH
(min): 2.2 V for V
CC
= 3.6 to 5.5 V
DC Characteristics (Ta = 0 to +70 C, V
CC
= 2.7 V to 5.5 V)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
I
LI
--
--
2*
1
A
V
CC
= 3.6 V, Vin =3.6 V
Output leakage current
I
LO
--
--
2
A
V
CC
= 3.6 V, Vout = 3.6/0.4 V
Standby V
CC
current
I
CC1
--
--
20
A
CE
= V
CC
I
CC2
--
--
1
mA
CE
= V
IH
Operating V
CC
current
I
CC3
--
--
6
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1
s at V
CC
= 3.3 V
--
--
15
mA
Iout = 0 mA, Duty = 100%,
Cycle = 250 ns at V
CC
= 3.3 V
Output low voltage
V
OL
--
--
0.4
V
I
OL
= 2.1 mA
Output high voltage
V
OH
V
CC
0.8
--
--
V
I
OH
= 400
A
Notes: 1. I
LI
on
RES
: 100
A (max)
HN58V1001 Series
5
Capacitance (Ta = 25C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input capacitance*
1
Cin
--
--
6
pF
Vin = 0 V
Output capacitance*
1
Cout
--
--
12
pF
Vout = 0 V
Note:
1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70 C, V
CC
= 2.7 V to 5.5 V)
Test Conditions
Input pulse levels: 0.4 V to 2.4 V
0 V to V
CC
(
RES pin)
Input rise and fall time: 20 ns
Output load: 1TTL Gate +100 pF
Reference levels for measuring timing: 0.8 V, 1.8 V
Read Cycle
HN58V1001-25
Parameter
Symbol
Min
Max
Unit
Test conditions
Address to output delay
t
ACC
--
250
ns
CE
=
OE
= V
IL
,
WE
= V
IH
CE
to output delay
t
CE
--
250
ns
OE
= V
IL
,
WE
= V
IH
OE
to output delay
t
OE
10
120
ns
CE
= V
IL
,
WE
= V
IH
Address to output hold
t
OH
0
--
ns
CE
=
OE
= V
IL
,
WE
= V
IH
OE
(
CE
) high to output float*
1
t
DF
0
50
ns
CE
= V
IL
,
WE
= V
IH
RES
low to output float
*1
t
DFR
0
350
ns
CE
=
OE
= V
IL
,
WE
= V
IH
RES
to output delay
t
RR
0
600
ns
CE
=
OE
= V
IL
,
WE
= V
IH
HN58V1001 Series
6
Write Cycle
Parameter
Symbol
Min*
2
Typ
Max
Unit
Test conditions
Address setup time
t
AS
0
--
--
ns
Address hold time
t
AH
150
--
--
ns
CE
to write setup time (
WE
controlled)
t
CS
0
--
--
ns
CE
hold time (
WE
controlled)
t
CH
0
--
--
ns
WE
to write setup time (
CE
controlled)
t
WS
0
--
--
ns
WE
hold time (
CE
controlled)
t
WH
0
--
--
ns
OE
to write setup time
t
OES
0
--
--
ns
OE
hold time
t
OEH
0
--
--
ns
Data setup time
t
DS
100
--
--
ns
Data hold time
t
DH
10
--
--
ns
WE
pulse width (
WE
controlled)
t
WP
250
--
--
ns
CE
pulse width (
CE
controlled)
t
CW
250
--
--
ns
Data latch time
t
DL
750
--
--
ns
Byte load cycle
t
BLC
1.0
--
30
s
Byte load window
t
BL
100
--
--
s
Write cycle time
t
WC
--
--
15*
3
ms
Time to device busy
t
DB
120
--
--
ns
Write start time
t
DW
250*
4
--
--
ns
Reset protect time
t
RP
100
--
--
s
Reset high time*
5
t
RES
1
--
--
s
Notes: 1. t
DF
and t
DFR
are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. Use this device in longer cycle than this value.
3. t
WC
must be longer than this value unless polling techniques or RDY/
Busy
are used. This device
automatically completes the internal write operation within this value.
4. Next read or write operation can be initiated after t
DW
if polling techniques or RDY/
Busy
are used.
5. This parameter is sampled and not 100% tested.
6. A7 to A16 are page addresses and must be same within the page write operation.
7. See AC read characteristics.
HN58V1001 Series
7
Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
t
ACC
t
CE
t
OE
t
OH
t
DF
t
RR
t
DFR
RES
HN58V1001 Series
8
Byte Write Timing Waveform (1) (
WE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
t
WC
t
CH
t
AH
t
CS
t
AS
t
WP
t
OEH
t
BL
t
OES
t
DS
t
DH
t
DB
t
RP
RES
V
CC
t
RES
High-Z
High-Z
t
DW
HN58V1001 Series
9
Byte Write Timing Waveform (2) (
CE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
t
WC
t
AH
t
WS
t
AS
t
OEH
t
WH
t
OES
t
DS
t
DH
t
DB
t
RP
RES
V
CC
t
CW
t
BL
t
DW
t
RES
High-Z
High-Z
HN58V1001 Series
10
Page Write Timing Waveform (1) (
WE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/
Busy
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
V
CC
t
CH
t
CS
t
WP
t
DL
t
BLC
t
DS
t
DW
High-Z
High-Z
*6
HN58V1001 Series
11
Page Write Timing Waveform (2) (
CE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/
Busy
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
V
CC
t
WH
t
WS
t
CW
t
DL
t
BLC
t
DS
t
DW
High-Z
High-Z
*6
HN58V1001 Series
12
Data Polling Timing Waveform
t
CE
t
OEH
t
WC
t
DW
t
OES
Address
CE
WE
OE
I/O7
t
OE
Din X
An
An
Dout
X
Dout X
*7
*7
HN58V1001 Series
13
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read.
When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible
for next read or program.
Notes: 1. I/O6 beginning state is "1".
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any location can be used, but the address must be fixed.
Toggle bit Waveform
WE
t
OES
OE
CE
Dout
I/O6
Dout
Dout
Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1
*2
*2
Address
*3
*3
*4
Din
HN58V1001 Series
14
Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data
5555
AA
AAAA or
2AAA
55
5555
A0
t
BLC
t
WC
CC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
5555

AA
AAAA
or
2AAA
55
5555

80
5555

AA
AAAA
or
2AAA
55
5555

20
HN58V1001 Series
15
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 s from the preceding falling edge of
WE or CE. When
CE or W E is kept high for 100 s after data input, the EEPROM enters write mode automatically and the
input data are written into the EEPROM.
Data Polling
Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM
is performing a write operation.
RDY/
Busy Signal
RDY/
Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to V
OL
after the first write signal. At the end of write cycle,
the RDY/
Busy signal changes state to high impedance.
RES Signal
When
RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when V
CC
is switched.
RES should be high during read and programming because it doesn't provide
a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit
Read inhibit
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of
WE or CE, and data is latched by the rising
edge of
WE or CE.
HN58V1001 Series
16
Write/Erase Endurance and Data Retention Time
The endurance is 10
4
cycles in case of the page programming and 10
3
cycles in case of the byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is page-
programmed less than 10
4
cycles.
Data Protection
1. Data Protection against Noise on Control Pins (
CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake.
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns
or less in program mode.
Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
HN58V1001 Series
17
2. Data Protection at V
CC
On/Off
When V
CC
is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the
EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.
Note:
The EEPROM should be kept in unprogrammable state during V
CC
on/off by using CPU RESET
signal.
V
CC
CPU
RESET
Unprogrammable
Unprogrammable
*
*
(1) Protection by
RES
The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the EEPROM's
RES pin. RES should be kept V
SS
level during V
CC
on/off.
The EEPROM brakes off programming operation when
RES becomes low, programming operation doesn't
finish correctly in case that
RES falls low during programming operation. RES should be kept high for 15 ms
after the last data input.
V
CC
RES
WE
or
CE
100
s min
15 ms min
1
s min
Program inhibit
Program inhibit
HN58V1001 Series
18
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is
enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is
input. To program data in the SDP enable mode, 3 bytes code must be input before write data.
Data
AA
55
A0
Write data }
Address
5555
AAAA or 2AAA
5555
Write address
Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be written.
Data
AA
55
80
AA
55
20
Address
5555
AAAA or 2AAA
5555
5555
AAAA or 2AAA
5555
The software data protection is not enabled at the shipment.
Note:
There are some differences between Hitachi's and other company's for enable/disable sequence of
software data protection. If there are any questions , please contact with Hitachi sales offices.
HN58V1001 Series
19
Package Dimensions
HN58V1001P Series (DP-32)
0.51 Min
2.54 Min
5.08 Max
0.25
+ 0.11
0.05
2.54
0.25
0.48
0.10
0
15
41.90
42.50 Max
13.4
13.7 Max
15.24
32
17
1
16
2.30 Max
1.20
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-32
--
Conforms
5.1 g
Unit: mm
HN58V1001 Series
20
Package Dimensions (cont.)
HN58V1001FP Series (FP-32D)
0.15
M
0.40
0.08
20.45
1.00 Max
1.27
11.30
1.42
3.00 Max
0.22
0.05
20.95 Max
32
17
1
16
0
8
0.80
0.20
14.14
0.30
0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-32D
Conforms
--
1.3 g
0.38
0.06
+ 0.12
0.10
0.15
0.20
0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58V1001 Series
21
Package Dimensions (cont.)
HN58V1001T Series (TFP-32DA)
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TFP-32DA
Conforms
Conforms
0.26 g
0.10
0.08
M
0.50
8.00
0.22
0.08
14.00
0.20
1.20 Max
12.40
32
1
16
17
0.17
0.05
0.13
0.05
0
5
8.20 Max
0.45 Max
0.50
0.10
0.80
0.20
0.06
0.125
0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58V1001 Series
22
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user's unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Continental Europe
Dornacher Strae 3
D-85622 Feldkirchen
Mnchen
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
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Singapore 049318
Tel: 535-2100
Fax: 535-1533
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Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.