Document Outline
- D e s c r i p t i o n
- F e a t u r e s
- O r d e r i n g I n f o r m a t i o n
- P i n A r r a n g e m e n t
- P i n D e s c r i p t i o n
- B l o c k D i a g r a m
- O p e r a t i o n T a b l e
- A b s o l u t e M a x i m u m R a t i n g s
- R e c o m m e n d e d D C O p e r a t i n g C o n d i t i o n s
- D C C h a r a c t e r i s t i c s
- C a p a c i t a n c e
- A C C h a r a c t e r i s t i c s
- R e a d T i m i n g W a v e f o r m
- B y t e W r i t e T i m i n g W a v e f o r m ( 1 ) ( W E C o n t r o l l e d )
- B y t e W r i t e T i m i n g W a v e f o r m ( 2 ) ( C E C o n t r o l l e d )
- P a g e W r i t e T i m i n g W a v e f o r m ( 1 ) ( W E C o n t r o l l e d )
- P a g e W r i t e T i m i n g W a v e f o r m ( 2 ) ( C E C o n t r o l l e d )
- D a t a P o l l i n g T i m i n g W a v e f o r m
- T o g g l e B i t W a v e f o r m
- S o f t w a r e D a t a P r o t e c t i o n T i m i n g W a v e f o r m ( 1 ) ( i n p r o t e c t i o n m o d e
- S o f t w a r e D a t a P r o t e c t i o n T i m i n g W a v e f o r m ( 2 ) ( i n n o n - p r o t e c t i o n
- F u n c t i o n a l D e s c r i p t i o n
- P a c k a g e D i m e n s i o n s
- H N 5 8 V 6 5 A P S e r i e s
H N 5 8 V 6 6 A P S e r i e s ( D P - 2 8 )
- H N 5 8 V 6 5 A F P S e r i e s
H N 5 8 V 6 6 A F P S e r i e s ( F P - 2 8 D )
- H N 5 8 V 6 5 A T S e r i e s
H N 5 8 V 6 6 A T S e r i e s ( T F P - 2 8 D B )
HN58V65A Series
HN58V66A Series
64 k EEPROM (8-kword
8-bit)
Ready/
Busy function, RES function (HN58V66A)
ADE-203-539B (Z)
Rev. 2.0
Nov. 1997
Description
The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable
EEPROM's organized as 8192-word
8-bit. They have realized high speed, low power consumption
and high relisbility by employing advanced MNOS memory technology and CMOS process and
circuitry technology. They also have a 64-byte page programming function to make their write
operations faster.
Features
Single supply: 2.7 to 5.5 V
Access time:
100 ns (max) at 2.7 V
V
CC
< 4.5 V
70 ns (max) at 4.5 V
V
CC
5.5 V
Power dissipation:
Active: 20 mW/MHz (typ)
Standby: 110
W (max)
On-chip latches: address, data,
CE, OE, WE
Automatic byte write: 10 ms (max)
Automatic page write (64 bytes): 10 ms (max)
Ready/
Busy
Data polling and Toggle bit
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
HN58V65A Series, HN58V66A Series
Features (cont)
10
5
erase/write cycles (in page mode)
10 years data retention
Software data protection
Write protection by
RES pin (only the HN58V66A series)
Industrial versions (Temperatur range: 20 to 85C and 40 to 85C) are also available.
Ordering Information
Access time
Type No.
2.7 V
V
CC
< 4.5 V
4.5 V
V
CC
5.5 V
Package
HN58V65AP-10
100 ns
70 ns
600 mil 28-pin plastic DIP (DP-28)
HN58V66AP-10
100 ns
70 ns
HN58V65AFP-10
100 ns
70 ns
400 mil 28-pin plastic SOP (FP-28D)
HN58V66AFP-10
100 ns
70 ns
HN58V65AT-10
100 ns
70 ns
28-pin plastic TSOP(TFP-28DB)
HN58V66AT-10
100 ns
70 ns
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/
Busy
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
HN58V65AP Series
HN58V65AFP Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
RES
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/
Busy
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
HN58V66AP Series
HN58V66AFP Series
HN58V65A Series, HN58V66A Series
Pin Arrangement (cont)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
SS
A3
A4
A5
A6
A7
A12
RDY/
Busy
V
WE
NC
A8
A9
A11
OE
CC
(Top view)
HN58V65AT Series
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
SS
A3
A4
A5
A6
A7
A12
RDY/
Busy
V
WE
RES
A8
A9
A11
OE
CC
(Top view)
HN58V66AT Series
15
16
17
18
19
20
21
22
23
24
25
26
27
28
HN58V65A Series, HN58V66A Series
Pin Description
Pin name
Function
A0 to A12
Address input
I/O0 to I/O7
Data input/output
OE
Output enable
CE
Chip enable
WE
Write enable
V
CC
Power supply
V
SS
Ground
RDY/
Busy
Ready busy
RES
*
1
Reset
NC
No connection
Notes: 1. This function is supported by only the HN58V66A series.
Block Diagram
Notes: This function is supported by only the HN58V66A series.
V
V
OE
CE
A5
A0
A6
A12
WE
CC
SS
I/O0
I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/
Busy
RES
*
1
*
1
to
to
to
HN58V65A Series, HN58V66A Series
Operation Table
Operation
CE
OE
WE
RES
*
3
RDY/
Busy
I/O
Read
V
IL
V
IL
V
IH
V
H
*
1
High-Z
Dout
Standby
V
IH
*
2
High-Z
High-Z
Write
V
IL
V
IH
V
IL
V
H
High-Z to V
OL
Din
Deselect
V
IL
V
IH
V
IH
V
H
High-Z
High-Z
Write Inhibit
V
IH
--
--
V
IL
--
--
Data
Polling
V
IL
V
IL
V
IH
V
H
V
OL
Dout (I/O7)
Program reset
V
IL
High-Z
High-Z
Notes: 1. Refer to the recommended DC operating conditions.
2.
: Don't care
3. This function supported by only the HN58V66A series.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to V
SS
V
CC
0.6 to +7.0
V
Input voltage relative to V
SS
Vin
0.5*
1
to +7.0*
3
V
Operating temperature range *
2
Topr
0 to +70
C
Storage temperature range
Tstg
55 to +125
C
Notes: 1. Vin min : 3.0 V for pulse width
50 ns.
2. Including electrical characteristics and data retention.
3. Should not exceed V
CC
+ 1 V.
HN58V65A Series, HN58V66A Series
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
2.7
--
5.5
V
V
SS
0
0
0
V
Input voltage
V
IL
0.3*
1
--
0.6*
5
V
V
IH
1.9*
2
--
V
CC
+ 0.3*
3
V
V
H
*
4
V
CC
0.5
--
V
CC
+ 1.0
V
Operating temperature
Topr
0
--
70
C
Notes: 1. V
IL
min: 1.0 V for pulse width
50 ns.
2. V
IH
= 2.2 V for V
CC
= 3.6 to 5.5 V.
3. V
IH
max: V
CC
+ 1.0 V for pulse width
50 ns.
4. This function is supported by only the HN58V66A series.
5. V
IL
= 0.8 V for V
CC
= 3.6 V to 5.5 V
DC Characteristics (Ta = 0 to + 70C, V
CC
= 2.7 to 5.5 V)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
I
LI
--
--
2*
1
A
Vin = 0 V to V
CC
Output leakage current
I
LO
--
--
2
A
Vout = 0 V to V
CC
Standby V
CC
curren
I
CC1
--
1 to 2
5
A
CE
= V
CC
0.3 V to V
CC
+ 1.0 V
I
CC2
--
--
1
mA
CE
= V
IH
Operating V
CC
current
I
CC3
--
--
6
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1
s at V
CC
= 3.6 V
--
--
8
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1
s at V
CC
= 5.5 V
--
--
12
mA
Iout = 0 mA, Duty = 100%,
Cycle = 100 ns at V
CC
= 3.6 V
--
--
25
mA
Iout = 0 mA, Duty = 100%,
Cycle = 70 ns at V
CC
= 5.5 V
Output low voltage
V
OL
--
--
0.4
V
I
OL
= 2.1 mA
Output high voltage
V
OH
V
CC
0.8 --
--
V
I
OH
= 400
A
Note:
1. I
LI
on
RES
: 100
A max (only the HN58V66A series)
Capacitance (Ta = 25C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input capacitance
Cin*
1
--
--
6
pF
Vin = 0 V
Output capacitance
Cout*
1
--
--
12
pF
Vout = 0 V
Note:
1. This parameter is sampled and not 100% tested.
HN58V65A Series, HN58V66A Series
AC Characteristics (Ta = 0 to + 70C, V
CC
= 2.7 to 5.5 V)
Test Conditions
Input pulse levels : 0.4 V to 2.4 V (V
CC
= 2.7 to 3.6 V), 0.4 V to 3.0 V (V
CC
= 3.6 to 5.5 V)
0 V to V
CC
(
RES pin*
2
)
Input rise and fall time :
5 ns
Input timing reference levels : 0.8, 1.8 V
Output load : 1TTL Gate +100 pF
Output reference levels : 1.5 V, 1.5 V
Read Cycle 1 (V
CC
= 2.7 to 4.5 V)
HN58V65A/HN58V66A
-10
Parameter
Symbol
Min
Max
Unit
Test conditions
Address to output delay
t
ACC
--
100
ns
CE
=
OE
= V
IL
,
WE
= V
IH
CE
to output delay
t
CE
--
100
ns
OE
= V
IL
,
WE
= V
IH
OE
to output delay
t
OE
10
50
ns
CE
= V
IL
,
WE
= V
IH
Address to output hold
t
OH
0
--
ns
CE
=
OE
= V
IL
,
WE
= V
IH
OE
(
CE
) high to output float*
1
t
DF
0
40
ns
CE
= V
IL
,
WE
= V
IH
RES
low to output float*
1, 2
t
DFR
0
350
ns
CE
=
OE
= V
IL
,
WE
= V
IH
RES
to output delay*
2
t
RR
0
450
ns
CE
=
OE
= V
IL
,
WE
= V
IH
HN58V65A Series, HN58V66A Series
Write Cycle 1 (V
CC
= 2.7 to 4.5 V)
Parameter
Symbol
Min*
3
Typ
Max
Unit
Test conditions
Address setup time
t
AS
0
--
--
ns
Address hold time
t
AH
50
--
--
ns
CE
to write setup time (
WE
controlled)
t
CS
0
--
--
ns
CE
hold time (
WE
controlled)
t
CH
0
--
--
ns
WE
to write setup time (
CE
controlled)
t
WS
0
--
--
ns
WE
hold time (
CE
controlled)
t
WH
0
--
--
ns
OE
to write setup time
t
OES
0
--
--
ns
OE
hold time
t
OEH
0
--
--
ns
Data setup time
t
DS
50
--
--
ns
Data hold time
t
DH
0
--
--
ns
WE
pulse width (
WE
controlled)
t
WP
200
--
--
ns
CE
pulse width (
CE
controlled)
t
CW
200
--
--
ns
Data latch time
t
DL
100
--
--
ns
Byte load cycle
t
BLC
0.3
--
30
s
Byte load window
t
BL
100
--
--
s
Write cycle time
t
WC
--
--
10*
4
ms
Time to device busy
t
DB
120
--
--
ns
Write start time
t
DW
0*
5
--
--
ns
Reset protect time*
2
t
RP
100
--
--
s
Reset high time*
2, 6
t
RES
1
--
--
s
Notes: 1. t
DF
and t
DFR
are defined as the time at which the outputs achieve the open circuit conditions
and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. t
WC
must be longer than this value unless polling techniques or RDY/
Busy
are used. This
device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t
DW
if polling techniques or RDY/
Busy
are
used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of
WE
.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of
CE
.
9. See AC read characteristics.
HN58V65A Series, HN58V66A Series
Read Cycle 2 (V
CC
= 4.5 to 5.5 V)
HN58V65A/HN58V66A
-10
Parameter
Symbol
Min
Max
Unit
Test conditions
Address to output delay
t
ACC
--
70
ns
CE
=
OE
= V
IL
,
WE
= V
IH
CE
to output delay
t
CE
--
70
ns
OE
= V
IL
,
WE
= V
IH
OE
to output delay
t
OE
10
40
ns
CE
= V
IL
,
WE
= V
IH
Address to output hold
t
OH
0
--
ns
CE
=
OE
= V
IL
,
WE
= V
IH
OE
(
CE
) high to output float*
1
t
DF
0
30
ns
CE
= V
IL
,
WE
= V
IH
RES
low to output float*
1, 2
t
DFR
0
350
ns
CE
=
OE
= V
IL
,
WE
= V
IH
RES
to output delay*
2
t
RR
0
450
ns
CE
=
OE
= V
IL
,
WE
= V
IH
HN58V65A Series, HN58V66A Series
Write Cycle 2 (V
CC
= 4.5 to 5.5 V)
Parameter
Symbol
Min*
3
Typ
Max
Unit
Test conditions
Address setup time
t
AS
0
--
--
ns
Address hold time
t
AH
50
--
--
ns
CE
to write setup time (
WE
controlled)
t
CS
0
--
--
ns
CE
hold time (
WE
controlled)
t
CH
0
--
--
ns
WE
to write setup time (
CE
controlled)
t
WS
0
--
--
ns
WE
hold time (
CE
controlled)
t
WH
0
--
--
ns
OE
to write setup time
t
OES
0
--
--
ns
OE
hold time
t
OEH
0
--
--
ns
Data setup time
t
DS
50
--
--
ns
Data hold time
t
DH
0
--
--
ns
WE
pulse width (
WE
controlled)
t
WP
100
--
--
ns
CE
pulse width (
CE
controlled)
t
CW
100
--
--
ns
Data latch time
t
DL
50
--
--
ns
Byte load cycle
t
BLC
0.2
--
30
s
Byte load window
t
BL
100
--
--
s
Write cycle time
t
WC
--
--
10*
4
ms
Time to device busy
t
DB
120
--
--
ns
Write start time
t
DW
0*
5
--
--
ns
Reset protect time*
2
t
RP
100
--
--
s
Reset high time*
2, 6
t
RES
1
--
--
s
Notes: 1. t
DF
and t
DFR
are defined as the time at which the outputs achieve the open circuit conditions
and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. t
WC
must be longer than this value unless polling techniques or RDY/
Busy
are used. This
device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t
DW
if polling techniques or RDY/
Busy
are
used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of
WE
.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of
CE
.
9. See AC read characteristics.
HN58V65A Series, HN58V66A Series
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
t
ACC
t
CE
t
OE
t
OH
t
DF
t
RR
t
DFR
RES
*
2
HN58V65A Series, HN58V66A Series
Byte Write Timing Waveform(1) (
WE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
t
WC
t
CH
t
AH
t
CS
t
AS
t
WP
t
OEH
t
BL
t
OES
t
DS
t
DH
t
DB
t
RP
RES
*
2
V
CC
t
RES
High-Z
High-Z
t
DW
HN58V65A Series, HN58V66A Series
Byte Write Timing Waveform(2) (
CE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
t
WC
t
AH
t
WS
t
AS
t
OEH
t
WH
t
OES
t
DS
t
DH
t
DB
t
RP
RES
*
2
V
CC
t
CW
t
BL
t
DW
t
RES
High-Z
High-Z
HN58V65A Series, HN58V66A Series
Page Write Timing Waveform(1) (
WE Controlled)
Address
A0 to A12
WE
CE
OE
Din
RDY/
Busy
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
*
2
V
CC
t
CH
t
CS
t
WP
t
DL
t
BLC
t
DS
t
DW
High-Z
High-Z
*7
HN58V65A Series, HN58V66A Series
Page Write Timing Waveform(2) (
CE Controlled)
Address
A0 to A12
WE
CE
OE
Din
RDY/
Busy
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
*
2
V
CC
t
WH
t
WS
t
CW
t
DL
t
BLC
t
DS
t
DW
High-Z
High-Z
*8
HN58V65A Series, HN58V66A Series
Data Polling Timing Waveform
t
CE
t
OEH
t
WC
t
DW
t
OES
Address
CE
WE
OE
I/O7
t
OE
Din X
An
An
Dout
X
Dout X
*9
*9
An
HN58V65A Series, HN58V66A Series
Toggle Bit
This device provide another function to determine the internal programming cycle. If the EEPROM is
set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for
each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device
can be accessible for next read or program.
Toggle Bit Waveform
Notes: 1. I/O6 begining state is "1".
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
WE
t
OES
OE
CE
Dout
I/O6
Dout
Dout
Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1
*2
*2
Address
*3
*3
*4
Din
HN58V65A Series, HN58V66A Series
Software Data Protection Timing Waveform(1) (in protection mode)
V
CE
WE
Address
Data
1555
AA
0AAA
55
1555
A0
t
BLC
t
WC
CC
Write address
Write data
Software Data Protection Timing Waveform(2) (in non-protection mode)
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
1555
AA
0AAA
55
1555
80
1555
AA
0AAA
55
1555
20
HN58V65A Series, HN58V66A Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write
cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner.
Each additional byte load cycle must be started within 30
s from the preceding falling edge of
WE or
CE. When CE or W E is kept high for 100
s after data input, the EEPROM enters write mode
automatically and the input data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read
mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the
EEPROM is performing a write operation.
RDY/
Busy Signal
RDY/
B us y signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to V
OL
after the first write signal. At the end of a write
cycle, the RDY/
Busy signal changes state to high impedance.
RES Signal (only the HN58V66A series)
When
RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by
keeping
RES low when V
CC
is switched.
RES should be high during read and programming because it
doesn't provide a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit
Read inhibit
HN58V65A Series, HN58V66A Series
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of
WE or CE, and data is latched by the
rising edge of
WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 10
5
cycles in case of the page programming and 10
4
cycles in case of the byte
programming (1% cumulative failure rate). The data retention time is more than 10 years when a device
is page-programmed less than 10
4
cycles.
Data Protection
1. Data Protection against Noise on Control Pins (
CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake.
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is
15 ns or less.
Be careful not to allow noise of a width of more than 15 ns on the control pins.
WE
CE
OE
V
0 V
V
0 V
15 ns max
IH
IH
HN58V65A Series, HN58V66A Series
2. Data protection at V
CC
on/off
When V
CC
is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may
act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note:
The EEPROM shoud be kept in unprogrammable state during V
CC
on/off by using CPU RESET
signal.
V
CC
CPU
RESET
Unprogrammable
Unprogrammable
*
*
(1) Protection by
CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the table
below.
CE
V
CC
OE
V
SS
WE
V
CC
: Don't care.
V
CC
: Pull-up to V
CC
level.
V
SS
: Pull-down to V
SS
level.
HN58V65A Series, HN58V66A Series
(2) Protection by
RES (only the HN58V66A series)
The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the
EEPROM's
RES pin. RES should be kept V
SS
level during V
CC
on/off. The EEPROM breaks off
programming operation when
RES becomes low, programming operation doesn't finish correctly in
case that
RES falls low during programming operation. RES should be kept high for 10 ms after the last
data input.
V
CC
RES
WE
or
CE
100
s min
10 ms min
1
s min
Program inhibit
Program inhibit
HN58V65A Series, HN58V66A Series
3. Software data protection
To prevent unintentional programming caused by noise generated by external circuits, this device has
the software data protection function. In software data protection mode, 3 bytes of data must be input
before write data as follows. And these bytes can switch the non-protection mode to the protection
mode. SDP is enabled if only the 3 bytes code is input.
Data
AA
55
A0
Write data }
Address
1555
0AAA
1555
Write address
Normal data input
Software data protection mode can be cancelled by inputting the following 6 bytes. After that, this
device turns to the non-protection mode and can write data normally. But when the data is input in the
cancelling cycle, the data cannot be written.
Data
AA
55
80
AA
55
20
Address
1555
0AAA
1555
1555
0AAA
1555
The software data protection is not enabled at the shipment.
Note:
There are some differences between Hitachi's and other company's for enable/disable sequence
of software data protection. If there are any questions , please contact with Hitachi sales
offices.
HN58V65A Series, HN58V66A Series
Package Dimensions
HN58V65AP Series
HN58V66AP Series (DP-28)
0.51 Min
2.54 Min
0.25
+ 0.11
0.05
2.54
0.25
0.48
0.10
0
15
15.24
1.2
35.6
36.5 Max
13.4
14.6 Max
1
14
15
28
5.70 Max
1.9 Max
Hitachi Code
JEDEC Code
EIAJ Code
Weight (reference value)
DP-28
--
SC-510-28E
4.6 g
Unit: mm
HN58V65A Series, HN58V66A Series
Package Dimensions (cont)
HN58V65AFP Series
HN58V66AFP Series (FP-28D)
0
8
0.17
0.05
1.0
0.2
0.20
0.10
2.50 Max
8.4
18.3
18.8 Max
1.12 Max
28
15
1
14
11.8
0.3
1.7
0.20
0.15
M
1.27
0.40
0.08
0.38
0.06
0.15
0.04
Hitachi Code
JEDEC Code
EIAJ Code
Weight (reference value)
FP-28D
MO-059-AC
--
0.7 g
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58V65A Series, HN58V66A Series
Package Dimensions (cont)
HN58V65AT Series
HN58V66AT Series (TFP-28DB)
0.10
M
0.55
8.00
0.22
0.08
13.40
0.30
0.17
0.05
0.13
1.20 Max
11.80
0
5
28
1
14
15
8.20 Max
0.10
+0.07 0.08
0.50
0.10
0.80
0.45 Max
Hitachi Code
JEDEC Code
EIAJ Code
Weight (reference value)
TFP-28DB
--
--
0.23 g
0.20
0.06
0.15
0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58V65A Series, HN58V66A Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or
part of this document without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or
any other reasons during operation of the user's unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the
examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party
or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use the products in
MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Strae 3
D-85622 Feldkirchen
Mnchen
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 0628-585000
Fax: 0628-778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
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