HT24LC01/02
1K/2K 2-Wire CMOS Serial EEPROM
Block Diagram
Pin Assignment
Features
Operating voltage: 2.4V~5.5V
Low power consumption
Operation: 5mA max.
Standby: 5
A max.
Internal organization
1K (HT24LC01):128
8
2K (HT24LC02): 256
8
2-wire serial interface
Write cycle time: 5ms max.
Automatic erase-before-write operation
Partial page write allowed
8-byte Page write modes
Write operation with built-in timer
Hardware controlled write protection
40-year data retention
10
6
erase/write cycles per word
8-pin DIP/SOP package
8-pin TSSOP (HT24LC02 only)
Commerical temperature range
(0
C to +70
C)
General Description
The HT24LC01/02 is a 1K/2K-bit serial
read/write non-volatile memory device using
the CMOS floating gate process. Its 1024/2048
bits of memory are organized into 128/256
words and each word is 8 bits. The device is
optimized for use in many industrial and com-
mercial applications where low power and low
voltage operation are essential. Up to eight
HT24LC01/02 devices may be connected to the
same two-wire bus. The HT24LC01/02 is guar-
anteed for 1M erase/write cycles and 40-year
data retention.
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Pin Description
Pin Name
I/O
Description
A0~A2
I
Address inputs
SDA
I/O
Serial data inputs/output
SCL
I
Serial clock data input
WP
I
Write protect
VSS
--
Negative power supply
VCC
I
Positive power supply
Absolute Maximum Ratings
Operating Temperature (Commercial) .................................................................................. 0
C to 70
C
Storage Temperature ........................................................................................................ 50
C to 125
C
Applied VCC Voltage with Respect to VSS ....................................................................... 0.3V to 6.0V
Applied Voltage on any Pin with Respect to VSS
...................................................................
0.3V to V
CC
+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maxi-
mum Ratings" may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=0
C to 70
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Conditions
V
CC
Operating Voltage
--
--
2.4
--
5.5
V
I
CC1
Operating Current
5V
Read at 100kHz
--
--
2
mA
I
CC2
Operating Current
5V
Write at 100kHz
--
--
5
mA
V
IL
Input Low Voltage
--
--
1
--
0.3V
CC
V
V
IH
Input High Voltage
--
--
0.7V
CC
--
V
CC
+0.5
V
V
OL
Output Low Voltage
2.4V I
OL
=2.1mA
--
--
0.4
V
I
LI
Input Leakage Current
5V
V
IN
=0 or V
CC
--
--
1
A
I
LO
Output Leakage Current
5V
V
OUT
=0 or V
CC
--
--
1
A
I
STB1
Standby Current
5V
V
IN
=0 or V
CC
--
--
5
A
I
STB2
Standby Current
2.4V V
IN
=0 or V
CC
--
--
4
A
C
IN
Input Capacitance (See Note)
--
f=1MHz 25
C
--
--
6
pF
C
OUT
Output Capacitance (See Note)
--
f=1MHz 25
C
--
--
8
pF
Note: These parameters are periodically sampled but not 100% tested
HT24LC01/02
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A.C. Characteristics
Ta=0
C to 70
C
Symbol
Parameter
Remark
Standard Mode* V
CC
=5V
10%
Unit
Min.
Max.
Min.
Max.
f
SK
Clock Frequency
--
100
--
400
kHz
t
HIGH
Clock High Time
4000
--
600
--
ns
t
LOW
Clock Low Time
4700
--
1200
--
ns
t
R
SDA and SCL Rise Time
Note
--
1000
--
300
ns
t
F
SDA and SCL Fall Time
Note
--
300
--
300
ns
t
HD:STA
START Condition Hold
Time
After this period
the first clock pulse
is generated
4000
--
600
--
ns
t
SU:STA
START Condition
Setup Time
Only relevant for
repeated START
condition
4000
--
600
--
ns
t
HD:DAT
Data Input Hold Time
0
--
0
--
ns
t
SU:DAT
Data Input Setup Time
200
--
100
--
ns
t
SU:STO
STOP Condition Setup
Time
4000
--
600
--
ns
t
AA
Output Valid from
Clock
--
3500
--
900
ns
t
BUF
Bus Free Time
Time in which the
bus must be free
before a new
transmission can
start
4700
--
1200
--
ns
t
SP
Input Filter Time
Constant (SDA and SCL
Pins)
Noise suppression
time
--
100
--
50
ns
t
WR
Write Cycle Time
--
5
--
5
ms
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means V
CC
=2.4V to 5.5V
For relative timing, refer to timing diagrams
HT24LC01/02
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Functional Description
Serial clock (SCL)
The SCL input is used for positive edge clock
data into each EEPROM device and negative
edge clock data out of each device.
Serial data (SDA)
The SDA pin is bidirectional for serial data
transfer. The pin is open-drain driven and
may be wired-OR with any number of other
open-drain or open collector devices.
A0, A1, A2
The A2, A1 and A0 pins are device address
inputs that are hard wired for the
HT24LC01/02. As many as eight 1K/2K de-
vices may be addressed on a single bus system
(the device addressing is discussed in detail
under the Device Addressing section).
Write protect (WP)
The HT24LC01/02 has a write protect pin
that provides hardware data protection. The
write protect pin allows normal read/write
operations when connected to the V
SS
. When
the write protect pin is connected to Vcc, the
write protection feature is enabled and oper-
ates as shown in the following table.
WP Pin
Status
Protect Array
HT24LC01
HT24LC02
At V
CC
Full Array (1K)
Full Array (2K)
At V
SS
Normal Read/Write Operations
Memory organization
HT24LC01, 1K Serial EEPROM
Internally organized with 128 8-bit words, the
1K requires a 7-bit data word address for
random word addressing.
HT24LC02, 2K Serial EEPROM
Internally organized with 256 8-bit words, the
2K requires an 8-bit data word address for
random word addressing.
Device operations
Clock and data transition
Data transfer may be initiated only when the
bus is not busy. During data transfer, the data
line must remain stable whenever the clock
line is high. Changes in data line while the
clock line is high will be interpreted as a
START or STOP condition.
Start condition
A high-to-low transition of SDA with SCL high
is a start condition which must precede any
other command (refer to Start and Stop Defi-
nition Timing diagram).
Stop condition
A low-to-high transition of SDA with SCL high
is a stop condition. After a read sequence, the
stop command will place the EEPROM in a
standby power mode (refer to Start and Stop
Definition Timing Diagram).
Acknowledge
All addresses and data words are serially
transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a zero to acknow-
ledge that it has received each word. This
happens during the ninth clock cycle.
Device addressing
The 1K and 2K EEPROM devices all require an
8-bit device address word following a start con-
dition to enable the chip for a read or write
operation. The device address word consist of a
mandatory one, zero sequence for the first four
most significant bits (refer to the diagram show-
ing the Device Address). This is common to all
the EEPROM device.
The next three bits are the A2, A1 and A0 device
address bits for the 1K/2K EEPROM. These
three bits must compare to their corresponding
hard-wired input pins.
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The 8th bit of device address is the read/write
operation select bit. A read operation is initi-
ated if this bit is high and a write operation is
initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the
chip will return to a standby state.
Write operations
Byte write
A write operation requires an 8-bit data word
address following the device address word
and acknowledgment. Upon receipt of this ad-
dress, the EEPROM will again respond with a
zero and then clock in the first 8-bit data
word. After receiving the 8-bit data word, the
EEPROM will output a zero and the address-
ing device, such as a microcontroller, must
terminate the write sequence with a stop con-
dition. At this time the EEPROM enters an
internally-timed write cycle to the non-vola-
tile memory. All inputs are disabled during
this write cycle and EEPROM will not re-
spond until the write is completed (refer to
Byte write timing).
Page write
The 1K/2K EEPROM is capable of an 8-byte
page write.
A page write is initiated the same as byte
write, but the microcontroller does not send a
stop condition after the first data word is
clocked in. Instead, after the EEPROM ac-
knowledges the receipt of the first data word,
the microcontroller can transmit up to seven
more data words. The EEPROM will respond
with a zero after each data word received. The
microcontroller must terminate the page
write sequence with a stop condition.
The data word address lower three (1K/2K)
bits are internally incremented following the
receipt of each data word. The higher data
word address bits are not incremented, re-
taining the memory page row location (refer
to Page write timing).
Acknowledge polling
Since the device will not acknowledge during
a write cycle, this can be used to determine
when the cycle is complete (this feature can be
used to maximize bus throughput). Once the
stop condition for a write command has been
issued from the master, the device initiates
the internally timed write cycle. ACK polling
can be initiated immediately. This involves
the master sending a start condition followed
by the control byte for a write command
(R/W=0). If the device is still busy with the
HT24LC01/02
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