HT48E30

8-Bit I/O Type MCU (With EEPROM)

Block Diagram

Rev. 0.00

January 12, 2004

General Description

The HT48E30 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.

The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and

wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.

Features

Operating voltage:
f

SYS

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

Low voltage reset function

23 bidirectional I/O lines (max.)

1 interrupt input shared with an I/O line

8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler

On-chip crystal and RC oscillator

Watchdog Timer

2048

´14 program memory ROM (MTP)

128

´8 data memory EEPROM

´8 data memory RAM

Buzzer driving pair and PFD supported

HALT function and wake-up feature reduce power
consumption

4-level subroutine nesting

Up to 0.5

ms instruction cycle with 8MHz system clock

at V

=5V

Bit manipulation instruction

14-bit table read instruction

63 powerful instructions

erase/write cycles EEPROM data memory

EEPROM data retention > 10 years

All instructions in one or two machine cycles

In system programming (ISP)

24/28-pin SKDIP/SOP package

I N T / P G 0

O S C 2

O S C 1

R E S

V D D

M U X

T M R / P C 0

T M R 0 C

T M R 0

V S S

P r e s c a l e r

S Y S

P G 0

P r o g r a m

R O M

P r o g r a m

C o u n t e r

I n t e r r u p t

C i r c u i t

S T A C K

4 L e v e l s

I N T C

D A T A

M e m o r y

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D e c o d e r

S T A T U S

A L U

S h i f t e r

T i m i n g

G e n e r a t o r

A C C

M P

W D T S

W D T

W D T O S C

W D T P r e s c a l e r

E N / D I S

P G 1

P G 2

P G C

P G

P O R T G

P B C

P O R T B

P B 0 ~ P B 7

B Z / B Z

P B

P A C

P O R T A

P A 0 ~ P A 7

P A

P C

P O R T C

P C 0 ~ P C 5

P C C

S Y S

/ 4

P G 0

D a t a M e m o r y

E E P R O M

E E C R

Preliminary

Pin Assignment

Pad Assignment

* The IC substrate should be connected to VSS in the PCB layout artwork.

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5

1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4

P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 5
P C 4
P C 3
P C 2

P B 5
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2

P B 1 / B Z
P B 0 / B Z

V S S

P G 0 / I N T

P C 0 / T M R

P C 1

H T 4 8 E 3 0

2 8 S K D I P - A / S O P - A

2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3

1
2
3
4
5
6
7
8
9
1 0
1 1
1 2

H T 4 8 E 3 0

2 4 S K D I P - A / S O P - A

P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 2
P C 0 / T M R

P B 5
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2

P B 1 / B Z
P B 0 / B Z

V S S

P G 0 / I N T

( 0 , 0 )

2 5

2 6

2 7

2 8

2 9

3 0

3 1

5
6

7
8

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

2 0

1 9

1 8

2 4
2 3

2 2
2 1

T R I M 1

T R I M 2

T R I M 3

P A 1
P A 0

P B 3
P B 2

P B 1 / B Z

P B 0 / B Z

V S S

0
/
I
N

0
/
T
M

P C 5

R E S

V D D

O S C 1

O S C 2

P A 7

P A 6

Pad Description

Pad Name

I/O

Options

Description

PA0~PA7

I/O

Pull-high*

Wake-up

CMOS/Schmitt trigger

Input

Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by options. Software instructions determine the CMOS
output or Schmitt trigger or CMOS input (depends on options) with
pull-high resistor (determined by 1-bit pull-high options).

PB0/BZ
PB1/BZ
PB2~PB7

I/O

Pull-high*

PB0 or BZ
PB1 or BZ

Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (deter-
mined by pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively.
Once the PB0 or PB1 is selected as buzzer driving outputs, the output
signals come from an internal PFD generator (shared with timer/event
counter).

VSS

Negative power supply, ground

PG0/INT

I/O

Pull-high*

Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). This external interrupt input is pin-shared with PG0.
The external interrupt input is activated on a high to low transition.

PC0/TMR
PC1~PC5

I/O

Pull-high*

Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). The timer input are pin-shared with PC0.

RES

Schmitt trigger reset input. Active low.

VDD

Positive power supply

OSC1
OSC2

Crystal or RC

OSC1and OSC2 are connected to an RC network or Crystal (deter-
mined by options) for the internal system clock. In the case of RC oper-
ation, OSC2 is the output terminal for 1/4 system clock.

Note:

²*² The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by a 1-bit option.

CMOS or Schmitt trigger option of port A is controlled by a 1-bit option.

Absolute Maximum Ratings

Supply Voltage ...........................V

-0.3V to V

+6.0V

Storage Temperature ............................

-50°C to 125°C

Input Voltage..............................V

-0.3V to V

+0.3V

Operating Temperature...........................

-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under

²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

D.C. Characteristics

Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

Operating Voltage

¾ f

SYS

=4MHz

2.2

5.5

¾ f

SYS

=8MHz

3.3

5.5

DD1

Operating Current (Crystal OSC)

No load, f

SYS

=4MHz

0.6

1.5

DD2

Operating Current (RC OSC)

No load, f

SYS

=4MHz

0.8

1.5

2.5

DD3

Operating Current (Crystal OSC)

No load, f

SYS

=8MHz

STB1

Standby Current (WDT Enabled)

No load, system HALT

STB2

Standby Current (WDT Disabled)

No load, system HALT

IL1

Input Low Voltage for I/O Ports

0.3V

IH1

Input High Voltage for I/O Ports

0.7V

IL2

Input Low Voltage (RES)

0.4V

IH2

Input High Voltage (RES)

0.9V

LVR

Low Voltage Reset Voltage

¾ LVR enabled

2.7

3.0

3.3

I/O Port Sink Current

=0.1V

I/O Port Source Current

=0.9V

-2

-4

=0.9V

-5

-10

Pull-high Resistance

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

A.C. Characteristics

Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

SYS1

System Clock (Crystal OSC)

¾ 2.2V~5.5V

400

4000

kHz

¾ 3.3V~5.5V

400

8000

kHz

SYS2

System Clock (RC OSC)

¾ 2.2V~5.5V

400

4000

kHz

¾ 3.3V~5.5V

400

8000

kHz

TIMER

Timer I/P Frequency (TMR)

¾ 2.2V~5.5V

4000

kHz

¾ 3.3V~5.5V

8000

kHz

WDTOSC

Watchdog Oscillator Period

180

130

WDT1

Watchdog Time-out Period (WDT OSC)

Without WDT prescaler

WDT2

Watchdog Time-out Period (System Clock)

¾ Without WDT prescaler

1024

SYS

RES

External Reset Low Pulse Width

SST

System Start-up Timer Period

¾ Wake-up from HALT

1024

SYS

INT

Interrupt Pulse Width

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Functional Description

Execution Flow

The HT48E30 system clock is derived from either a
crystal or an RC oscillator and is internally divided into
four non-overlapping clocks. One instruction cycle con-
sists of four system clock cycles.

Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
This pipelining scheme ensures that instructions are ef-
fectively executed in one cycle. If an instruction changes
the contents of the program counter, two cycles are re-
quired to complete the instruction.

Program Counter

- PC

The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.

After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are

incremented by one. The program counter then points to
the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex-
ecution, loading into the PCL register, subroutine call or
return from subroutine, initial reset, internal interrupt,
external interrupt or return from interrupt, the PC manip-
ulates the program transfer by loading the address cor-
responding to each instruction.

The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.

The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.

When a control transfer takes place, an additional
dummy cycle is required.

Mode

Program Counter

*10

Initial Reset

External Interrupt

Timer/Event Counter Overflow

Skip

PC+2

Loading PCL

*10

Jump, Call Branch

#10

Return from Subroutine

S10

Program Counter

Note: *10~*0: Program counter bits

S10~S0: Stack register bits

#10~#0: Instruction code bits

@7~@0: PCL bits

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

O S C 2 ( R C o n l y )

P C

Execution Flow

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Instruction

Table Location

*10

TABRDC [m]

P10

TABRDL [m]

Table Location

Note: *10~*0: Table location bits

P10~P8: Current program counter bits

@7~@0: Table pointer bits

In System Programming

In system programming allows programming and repro-
gramming of HT48EXX microcontroller on application
circuit board, this will save time and money, both during
development in the lab. Using a simple 3-wire interface,
the ISP communicates serially with the HT48EXX
microcontroller, reprogramming program memory and
EEPROM data memory on the chip.

Pin Name Function

Description

PA0

SDATA

Serial data input/output

PA4

SCLK

Serial clock input

RES

RESET

Device reset

VDD

Power supply

VSS

Ground

ISP Pin Assignments

Program Memory

- ROM

The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into

2048

´14 bits, addressed by the program counter and ta-

ble pointer.

Certain locations in the program memory are reserved
for special usage:

Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at lo-
cation 000H.

Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.

Location 008H
This area is reserved for the timer/event counter inter-
rupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is en-
abled and the stack is not full, the program begins exe-
cution at location 008H.

Table location

Any location in the program memory space can be

used as look-up tables. The instructions

²TABRDC

[m]

² (the current page, one page=256 words) and

²TABRDL [m]² (the last page) transfer the contents of
the lower-order byte to the specified data memory,
and the higher-order byte to TBLH (08H). Only the
destination of the lower-order byte in the table is
well-defined, the other bits of the table word are trans-
ferred to the lower portion of TBLH, and the remaining

2-bits words are read as

²0². The Table Higher-order

byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the lo-
cation must be placed in the TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main rou-
tine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is
supposed to be disabled prior to the table read in-
struction. It will not be enabled until the TBLH has
been backed up. All table related instructions require

7 F F H

n F F H

P r o g r a m

M e m o r y

D e v i c e I n i t i a l i z a t i o n P r o g r a m

E x t e r n a l I n t e r r u p t S u b r o u t i n e

T i m e r / E v e n t C o u n t e r

I n t e r r u p t S u b r o u t i n e

L o o k - u p T a b l e ( 2 5 6 w o r d s )

N o t e : n r a n g e s f r o m 0 t o 7

n 0 0 H

0 0 8 H

0 0 4 H

0 0 0 H

1 4 b i t s

7 0 0 H

Program Memory

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.

Stack Register

- STACK

This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.

If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a

²CALL² is sub-

sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 4 return ad-
dresses are stored).

Data Memory

- RAM

The data memory has a capacity of 115

´8 bits and is di-

vided into two functional groups: special function regis-

ters and general purpose data memory (96

´8). Most

are read/write, but some are read only.

The special function registers include the indirect ad-
dressing registers (R0;00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis-
ter (PCL;06H), memory pointer registers (MP;01H), ac-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H, PG;1EH) and
I/O control registers (PAC;13H, PBC;15H, PCC;17H,
PGC;1FH). The remaining space before the 20H is re-
served for future expanded usage and reading these

locations will return the result

²00H². The general pur-

pose data memory, addressed from 20H to 7FH, is used
for data and control information under instruction com-
mands.

All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by

²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP). The control register of
the EEPROM data memory is located at [40H] in Bank 1.

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration on [00H] and [02H] access the RAM pointed to
by MP0 (01H) and MP1 (03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation. The
function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory in Bank 0, while MP1 can be applied to data
memory in Bank 0 and Bank1.

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 9 6 B y t e s )

S p e c i a l P u r p o s e
D A T A M E M O R Y

0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H

0 A H
0 B H

0 C H
0 D H

0 E H

0 F H

1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H

1 A H
1 B H

1 C H
1 D H

1 E H
1 F H

7 F H

: U n u s e d

R e a d a s " 0 0 "

2 0 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

B P

A C C

P C L

T B L P
T B L H

W D T S

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P G

P G C

8 0 H

F F H

RAM Mapping

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Accumulator

The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.

Arithmetic and logic unit

- ALU

This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation
but also changes the status register.

Status Register

- STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.

With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by a system power-up, a WDT

time-out or executing the

²CLR WDT² or ²HALT² in-

struction. The PDF flag can be affected only by exe-

cuting the

²HALT² or ²CLR WDT² instruction or

during a system power-up.

The Z, OV, AC and C flags generally reflect the status of
the latest operations.

In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine may cor-
rupt the status register, precautions must be taken to
save it properly.

Interrupt

The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable or disable and the interrupt request
flags.

Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related in-
terrupt is enabled, until the SP is decremented. If immedi-
ate service is desired, the stack must be prevented from
becoming full.

All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.

External interrupts are triggered by a high to low transi-
tion of the INT and the related interrupt request flag (EIF;
bit 4 of INTC) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a

Labels

Bits

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-
est-order bit, or vice versa; otherwise OV is cleared.

PDF

PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by ex-

ecuting the

²HALT² instruction.

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

Unused bit, read as

²0²

Unused bit, read as

²0²

Status Register

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.

The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the

²RETI² in-

struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine,

²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.

Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.

No.

Interrupt Source

Priority Vector

External Interrupt

04H

Timer/Event Counter Overflow

08H

The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), enable timer/event
counter interrupt bit (ETI), enable external interrupt bit
(EEI) and enable master interrupt bit (EMI) constitute an
interrupt control register (INTC) which is located at 0BH
in the data memory. EMI, EEI, ETI are used to control
the enabling/disabling of interrupts. These bits prevent
the requested interrupt from being serviced. Once the
interrupt request flags (TF, EIF) are set, they will remain
in the INTC register until the interrupts are serviced or
cleared by a software instruction.

It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.

If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-

aged once the

²CALL² operates in the interrupt subrou-

tine.

Oscillator Configuration

There are 2 oscillator circuits in the microcontroller.

All of them are designed for system clocks, namely, ex-
ternal RC oscillator and external Crystal oscillator,
which are determined by options. No matter what oscil-
lator type is selected, the signal provides the system
clock. The HALT mode stops the system oscillator and
ignores an external signal to conserve power.

If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must

range from 24k

W to 1MW. The system clock, divided by

4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of oscil-
lation may vary with VDD, temperatures and the chip it-
self due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.

If a Crystal oscillator is used, a crystal across OSC1 and
OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external compo-
nents are required. In stead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to obtain
a frequency reference, but two external capacitors in
OSC1 and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode and the sys-

Register

Bit No.

Label

Function

INTC

(0BH)

EMI

Controls the master (global) interrupt (1= enabled; 0= disabled)

EEI

Controls the external interrupt (1= enabled; 0= disabled)

ETI

Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)

Unused bit, read as

²0²

EIF

External interrupt request flag (1= active; 0= inactive)

Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)

Unused bit, read as

²0²

Unused bit, read as

²0²

INTC Register

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

N M O S O p e n D r a i n

O S C 2

S Y S

/ 4

4 7 0 p F

D D

O S C 1

System Oscillator

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

tem clock is stopped, the oscillator still works within a

period of 65

ms at 5V. The WDT oscillator can be dis-

abled by options to conserve power.

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by op-
tions. If the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a

period of 65

ms at 5V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-
riod of 18.6ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2, WS1,
and WS0 are all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.4s at 5V seconds. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by an external logic. The

high nibble and bit 3 of the WDTS are reserved for user

¢s

defined flags, which can be used to indicate some speci-
fied status.

If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.

WS2

WS1

WS0

Division Ratio

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

WDTS Register

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the

HALT mode, the overflow will initialize a

²warm reset²

and only the PC and SP are reset to zero. To clear the
contents of WDT (including the WDT prescaler), three
methods are adopted; external reset (a low level to

RES), software instruction and a

²HALT² instruction.

The software instruction includes

²CLR WDT² and the

other set

- ²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one can be active depend-

ing on the option

- ²CLR WDT times selection option². If

the

²CLR WDT² is selected (i.e. CLRWDT times equal

one), any execution of the

²CLR WDT² instruction will

clear the WDT. In the case that

²CLR WDT1² and ²CLR

WDT2

² are chosen (i.e. CLRWDT times equal two),

these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip as a result
of time-out.

Power Down Operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following...

The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).

The contents of the on chip RAM and registers remain
unchanged.

WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).

All of the I/O ports maintain their original status.

The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-

forms a

²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-

cuting the

²CLR WDT² instruction and is set when exe-

cuting the

²HALT² instruction. The TO flag is set if a

WDT time-out occurs, and causes a wake-up that only
resets the PC and SP; the others remain in their original
status.

S y s t e m C l o c k / 4

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, a regular interrupt re-
sponse takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 (system clock pe-
riod) to resume to normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.

To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

RES reset during normal operation

RES reset during HALT

WDT time-out reset during normal operation

The time-out during HALT is different from other chip re-

set conditions, since it can perform a

²warm reset² that

resets only the PC and SP, leaving the other circuits in
their original state. Some registers remain unchanged
during other reset conditions. Most registers are reset to

the

²initial condition² when the reset conditions are met.

By examining the PDF and TO flags, the program can

distinguish between different

²chip resets².

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for unchanged"

To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.

When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able an SST delay.

An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).

The functional unit chip reset status are shown below.

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,
WDT begins counting

Timer/Event Counter

Off

Input/Output Ports

Input mode

Stack Pointer, SP

Points to the top of the stack

R E S

D D

1 0 0 k W

1 0 k W

0 . 1 m F *

0 . 0 1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.

S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

S y s t e m R e s e t

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

Reset Configuration

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

The registers status is summarized in the following table.

Register

Reset

(Power On)

WDT Time-out

(Normal Operation)

RES Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

TMR

xxxx xxxx

uuuu uuuu

TMRC

00-0 1000

uu-u uuuu

Program
Counter

000H

-xxx xxxx

-uuu uuuu

ACC

xxxx xxxx

uuuu uuuu

TBLP

xxxx xxxx

uuuu uuuu

TBLH

--xx xxxx

--uu uuuu

STATUS

--00 xxxx

--1u uuuu

--uu uuuu

--01 uuuu

--11 uuuu

INTC

--00 0000

--uu uuuu

WDTS

0000 0111

uuuu uuuu

1111 1111

uuuu uuuu

PAC

1111 1111

uuuu uuuu

1111 1111

uuuu uuuu

PBC

1111 1111

uuuu uuuu

--11 1111

--uu uuuu

PCC

--11 1111

--uu uuuu

---- ---1

---- ---u

PGC

---- ---1

---- ---u

EECR

1000 ----

uuuu ----

Note:

²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²

Timer/Event Counter

Timer/event counters (TMR) is implemented in the
microcontroller. The timer/event counter contains an 8-bit
programmable count-up counter and the clock may come
from an external source or from the system clock by 4.

Using the internal clock sources, there are 2 reference
time-bases for the timer/event counter. The internal
clock source can be selected as coming from f

SYS

or by

options. Using an external clock input allows the user to
count external events, measure time internals or pulse
widths, or generate an accurate time base. While using
the internal clock allows the user to generate an accu-
rate time base.

The timer/event counter can generate PFD signals by
using external or internal clock and the PFD frequency

is determine by the equation f

INT

/[2

´(256-N)].

There are 2 registers related to the timer/event counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the start-
ing value be placed in the timer/event counter preload
register and reading TMR retrieves the contents of the
timer/event counter. The TMRC is a timer/event counter

control register, which defines some options.

The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the f

INT

clock. The

pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
counting is based on the f

INT

clock.

In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once over-
flow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt re-
quest flag (TF; bit 5 of INTC) at the same time.

In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a tran-

sient from low to high (or high to low if the TE bits is

²0²)

it will start counting until the TMR returns to the original
level and resets the TON. The measured result will re-
main in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Label (TMRC)

Bits

Function

PSC0~PSC2

0~2

Defines the prescaler stages, PSC2, PSC1, PSC0=
000: f

INT

SYS

001: f

INT

SYS

010: f

INT

SYS

011: f

INT

SYS

/16

100: f

INT

SYS

/32

101: f

INT

SYS

/64

110: f

INT

SYS

/128

111: f

INT

SYS

/256

Defines the TMR active edge of the timer/event counter 0
(0=active on low to high; 1=active on high to low)

TON

Enable or disable timer 0 counting
(0=disabled; 1=enabled)

Unused bit, read as

²0²

TM0
TM1

6
7

Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused

TMRC Register

T M 1

T M 0

T M R

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

T i m e r / E v e n t

C o u n t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

1 / 2

B Z
B Z

8 - s t a g e P r e s c a l e r

8 - 1 M U X

S Y S

I N T

P S C 2 ~ P S C 0

( 1 / 2 ~ 1 / 2 5 6 )

Timer/Event Counter

measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transient pulse. Note that, in this operat-
ing mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared au-
tomatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the opera-

tion mode is, writing a

²0² to ETI can disable the corre-

sponding interrupt services.

In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter (reading TMR) is
read, the clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this must be
taken into consideration by the programmer.

The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of the timer/event counter can be used
to generate PFD signals for buzzer driving.

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Input/Output Ports

There are 23 bidirectional input/output lines in the
microcontroller, labeled from PA to PC and PG, which
are mapped to the data memory of [12H], [14H], [16H]
and [1EH] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction

²MOV

A,[m]

² (m=12H, 14H, 16H or 1EH). For output operation,

all the data is latched and remains unchanged until the
output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,
PCC, PGC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the con-

trol register must write a

²1². The input source also de-

pends on the control register. If the control register bit is
²1², the input will read the pad state. If the control regis-
ter bit is

²0², the contents of the latches will move to the

i n t e r n a l b u s . T h e l a t t e r i s p o s s i b l e i n t h e
²read-modify-write² instruction.

For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 1FH.

After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set

or cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H or 1EH) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.

Each line of port A has the capability of waking-up the de-
vice. The highest 7-bit of port G are not physically imple-

mented; on reading them a

²0² is returned whereas writing

then results in no operation. See Application note.

There is a pull-high option available for all I/O lines (bit
option). Once the pull-high option of an I/O line is se-
lected, the I/O line has a pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.

The PB0 and PB1 are pin-shared with BZ and BZ sig-
nals, respectively. If the BZ/BZ option is selected, the
output signal in output mode of PB0/PB1 will be the PFD
signal generated by timer/event counter 0 overflow sig-
nal. The input mode always remain in its original func-
tions. Once the BZ/BZ option is selected, the buzzer
output signals are controlled by the PB0 data register
only.

The I/O functions of PB0/PB1 are shown below.

PB0 I/O

PB1 I/O

PB0 Mode

PB1 Mode

PB0 Data

PB1 Data

PB0 Pad Status

PB1 Pad Status

Note:

²I² input, ²O² output, ²D, D

, D

² data,

²B² buzzer option, BZ or BZ, ²x² don't care
²C² CMOS output

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

The PG0 is pin-shared with INT.

It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.

Low Voltage Reset

- LVR

The HT48E30 provides a low voltage reset circuit in or-
der to monitor the supply voltage of the device. If the
supply voltage is within the range 0.9V~V

LVR

, such as

while changing a battery, the LVR will automatically re-
set the device internally.

The LVR includes the following specifications:

Within the low voltage range (0.9V~V

LVR

), the device

remains in their original state until exceeding 1ms. If
the low voltage state does not exceed 1ms, the LVR
will ignore it and does not perform a reset function.

The LVR uses the

²OR² function with the external

RES signal to perform chip reset.

The relationship between V

and V

LVR

is shown below.

Note:

OPR

is the voltage range for proper chip opera-

tion at 4MHz system clock.

D D

P A 0 ~ P A 7

P B 0 ~ P B 7

P C 0 ~ P C 5

P G 0

B Z E N

( P B 0 , P B 1 O n l y )

O P 0 ~ O P 7

I N T f o r P G 0 O n l y

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

P B 0

B Z / B Z

( P B 0 , P B 1 O n l y )

C K

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

Input/Output Ports

5 . 5 V

3 . 3 V

2 . 4 V

0 . 9 V

D D

O P R

L V R

5 . 5 V

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

EEPROM Data Memory

The 128

´8 bits EEPROM data memory is readable and writable during normal operation. It is indirectly addressed

through the control register EECR ([40H] in Bank 1). The EECR can be read and written to only by indirect addressing
mode using MP1.

Label (EECR)

Bits

Function

0~3

Unused bit, read as

²0²

EEPROM data memory select

Serial clock input to EEPROM data memory

Serial data input to EEPROM data memory

Serial data output from EEPROM data memory

D D

5 . 5 V

L V R

0 . 9 V

0 V

R e s e t S i g n a l

R e s e t

* 1

* 2

N o r m a l O p e r a t i o n

R e s e t

L V R D e t e c t V o l t a g e

Low Voltage Reset

Note:

*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of

1024 system clock pulses before entering the normal operation.

*2: Since low voltage has to be maintained in its original state until exceeding 1ms, therefore after a 1ms

delay, the device enters a reset mode.

E E C R

C S

S K

D I

D O

D D

C o n t r o l

L o g i c

a n d

C l o c k

G e n e r a t o r

A d d r e s s R e g i s t e r

D I

C S

S K

D O

S a m e a s H T 9 3 L C 4 6

D a t a

R e g i s t e r

A d d r e s s D e c o d e r

M e m o r y C e l l A r r a y

1 K : ( 1 2 8 ´ 8 )

O u t p u t B u f f e r

EEPROM Data Memory Block Diagram

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

The EEPROM data memory is accessed via a
three-wire serial communication interface by writing to
EECR. It is arranged into 128 words by 8 bits. The
EEPROM data memory contains seven instructions:
READ, ERASE, WRITE, EWEN, EWDS, ERAL and
WRAL. These instructions are all made up of 10 bits
data: 1 start bit, 2 op-code bits and 7 address bits.

By writing CS, SK and DI, these instructions can be
given to the EEPROM. These serial instruction data pre-
sented at the DI will be written into the EEPROM data

memory at the rising edge of SK. During the READ cy-
cle, DO acts as the data output and during the WRITE or
ERASE cycle, DO indicates the BUSY/READY status.
When the DO is active for read data or as a BUSY/
READY indicator the CS pin must be high; otherwise
DO will be in a high state. For successful instructions,
CS must be low once after the instruction is sent. After
power on, the device is by default in the EWDS state.
And, an EWEN instruction must be performed before
any ERASE or WRITE instruction can be executed.

C S

S K

D O

D I

C D S

C S S

C S H

S K L

S K H

D I S

D I H

P D 1

P D 0

V a l i d D a t a

The following are the functional descriptions and timing diagrams of all seven instructions.

EECR A.C. Characteristics

Ta=25

°C

Symbol

Parameter

=5V

±10%

=2.2V

±10%

Unit

Min.

Max.

Min.

Max.

Clock Frequency

MHz

SKH

SK High Time

250

500

SKL

SK Low Time

250

500

CSS

CS Setup Time

100

CSH

CS Hold Time

CDS

CS Deselect Time

250

DIS

DI Setup Time

100

200

DIH

DI Hold Time

100

200

PD1

DO Delay to

²1²

250

500

PD0

DO Delay to

²0²

250

500

Status Valid Time

250

DO Disable Time

100

200

Write Cycle Time Per Word

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

READ

The READ instruction will stream out data at a specified
address on the DO. The data on DO changes during the
low-to-high edge of SK. The 8 bits data stream is pre-

ceded by a logical

²0² dummy bit. Irrespective of the

condition of the EWEN or EWDS instruction, the READ
command is always valid and independent of these two
instructions. After the data word has been read the in-
ternal address will be automatically incremented by 1 al-
lowing the next consecutive data word to be read out
without entering further address data. The address will
wrap around with CS High until CS returns to Low.

EWEN/EWDS

The EWEN/EWDS instruction will enable or disable the
programming capabilities. At both the power on and
power off state the device automatically entered the dis-
able mode. Before a WRITE, ERASE, WRAL or ERAL in-
struction is given, the programming enable instruction
EWEN must be issued, otherwise the ERASE/WRITE in-
struction is invalid. After the EWEN instruction is issued,
the programming enable condition remains until power is
turned off or an EWDS instruction is given. No data can be
written into the EEPROM data memory in the program-
ming disabled state. By so doing, the internal memory data
can be protected.

ERASE

The ERASE instruction erases data at the specified ad-
dresses in the programming enable mode. After the
ERASE op-code and the specified address have been
issued, the data erase is activated by the falling edge of
CS. Since the internal auto-timing generator provides all
timing signals for the internal erase, so the SK clock is
not required. During the internal erase, we can verify the
busy/ready status if CS is high. The DO will remain low
but when the operation is over, the DO will return to high
and further instructions can be executed.

WRITE

The WRITE instruction writes data into the EEPROM
data memory at the specified addresses in the program-
ming enable mode. After the WRITE op-code and the
specified address and data have been issued, the data
writing is activated by the falling edge of CS. Since the
internal auto-timing generator provides all timing signal
for the internal writing, so the SK clock is not required.
The auto-timing write cycle includes an automatic
erase-before-write capability. So, it is not necessary to
erase data before the WRITE instruction. During the in-
ternal writing, we can verify the busy/ready status if CS
is high. The DO will remain low but when the operation is
over, the DO will return to high and further instructions
can be executed.

ERAL

The ERAL instruction erases the entire 128

´8 memory

cells to a logical

²1² state in the programming enable

mode. After the erase-all instruction set has been is-
sued, the data erase feature is activated by the falling
edge of CS. Since the internal auto-timing generator
provides all timing signal for the erase-all operation, so
the SK clock is not required. During the internal erase-all
operation, we can verify the busy/ready status if CS is
high. The DO will remain low but when the operation is
over, the DO will return to high and further instruction
can be executed.

WRAL

The WRAL instruction writes data into the entire 128

´8

memory cells in the programming enable mode. After
the write-all instruction set has been issued, the data
writing is activated by the falling edge of CS. Since the
internal auto-timing generator provides all timing signals
for the write-all operation, so the SK clock is not re-
quired. During the internal write-all operation, we can
verify the busy/ready status if CS is high. The DO will re-
main low but when the operation is over the DO will re-
turn to high and further instruction can be executed.

EECR Control Timing Diagrams

READ

C S

S K

D O

D I

S t a r t b i t

( 1 )

C D S

* A d d r e s s p o i n t e r a u t o m a t i c a l l y c y c l e s t o t h e n e x t w o r d

A N

A 0

D 0 D X

D X

M o d e

A N
D X

( X 8 )

A 6
D 7

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

WRAL

EEPROM Data Memory Instruction Set Summary

Instruction

Comments

Start bit

Op Code

Address

Data

READ

Read data

A6~A0

D7~D0

ERASE

Erase data

A6~A0

WRITE

Write data

A6~A0

D7~D0

EWEN

Erase/Write Enable

11XXXXX

EWDS

Erase/Write Disable

00XXXXX

ERAL

Erase All

10XXXXX

WRAL

Write All

01XXXXX

D7~D0

Note:

²X² stands for ²don¢t care²

Options

The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.

Items

Options

WDT clock source: WDT oscillator or f

SYS

/4 or disable

CLRWDT instructions: 1 or 2 instructions

Timer/event counter clock source: f

SYS

PA bit wake-up enable or disable

PA CMOS or Schmitt input

PA, PB, PC, PG pull-high enable or disable (by port)

BZ/BZ enable or disable

LVR enable or disable

System oscillator: RC or crystal

C S

S K

D O

S t a n d b y

D I

( 1 )

S V

P R

C D S

B u s y

R e a d y

V e r i f y

D X

D 0

S t a r t b i t

Application Circuits

The following table shows the C1, C2 and R1 value according different crystal values.

Crystal or Resonator

C1, C2

4MHz Crystal

0pF

10k

4MHz Resonator (3 pin)

0pF

12k

4MHz Resonator (2 pin)

10pF

12k

3.58MHz Crystal

0pF

10k

3.58MHz Resonator (2 pin)

25pF

10k

2MHz Crystal & Resonator (2 pin)

25pF

10k

1MHz Crystal

35pF

27k

480kHz Resonator

300pF

9.1k

455kHz Resonator

300pF

10k

429kHz Resonator

300pF

10k

Note:

The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.

²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

H T 4 8 E 3 0

O S C 1
O S C 2

O S C

C i r c u i t

R E S

0 . 1 m F *

1 0 0 k W

V D D

V S S

0 . 1 m F

D D

0 . 0 1 m F *

1 0 k W

O S C C i r c u i t

P G 0 / I N T

P A 0 ~ P A 7
P B 2 ~ P B 7

P C 1 ~ P C 5

P B 0 / B Z

P B 1 / B Z

P C 0 / T M R

O S C 1

O S C 2

C r y s t a l S y s t e m O s c i l l a t o r

F o r t h e v a l u e s ,

s e e t a b l e b e l o w

R C S y s t e m O s c i l l a t o r

2 4 k W < R

O S C

< 1 M W

R 1

C 1

C 2

D D

O S C

O S C 1

O S C 2

4 7 0 p F

N M O S o p e n d r a i n

S e e R i g h t S i d e

Instruction Set Summary

Mnemonic

Description

Instruction

Cycle

Flag

Affected

Arithmetic

ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]

Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory

(1)

1
1

(1)

1
1

(1)

Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV

Logic Operation

AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]

AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC

1
1
1

(1)

1
1
1

(1)

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

Increment & Decrement

INCA [m]
INC [m]
DECA [m]
DEC [m]

Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory

(1)

Z
Z
Z
Z

Rotate

RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]

Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry

(1)

None
None

C
C

None
None

C
C

Data Move

MOV A,[m]
MOV [m],A
MOV A,x

Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC

(1)

None
None
None

Bit Operation

CLR [m].i
SET [m].i

Clear bit of data memory
Set bit of data memory

(1)

None
None

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Mnemonic

Description

Instruction

Cycle

Flag

Affected

Branch

JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI

Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt

(2)

(3)

(2)

2
2
2
2

None
None
None
None
None
None
None
None
None
None
None
None
None

Table Read

TABRDC [m]
TABRDL [m]

Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH

(1)

None
None

Miscellaneous

NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT

No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode

(1)

1
1
1

(1)

1
1

None
None
None

TO,PDF

(4)

,PDF

(4)

,PDF

(4)

None
None

TO,PDF

Note:

x: Immediate data

m: Data memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Ö: Flag is affected
-: Flag is not affected

(1)

: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle

(four system clocks).

(2)

: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more

cycle (four system clocks). Otherwise the original instruction cycle is unchanged.

(3)

(1)

and

(2)

(4)

: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the

²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Instruction Definition

ADC A,[m]

Add data memory and carry to the accumulator

Description

The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.

Operation

ACC

¬ ACC+[m]+C

Affected flag(s)

PDF

ADCM A,[m]

Add the accumulator and carry to data memory

Description

The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.

Operation

[m]

¬ ACC+[m]+C

Affected flag(s)

PDF

ADD A,[m]

Add data memory to the accumulator

Description

The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.

Operation

ACC

¬ ACC+[m]

Affected flag(s)

PDF

ADD A,x

Add immediate data to the accumulator

Description

The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.

Operation

ACC

¬ ACC+x

Affected flag(s)

PDF

ADDM A,[m]

Add the accumulator to the data memory

Description

The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.

Operation

[m]

¬ ACC+[m]

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

AND A,[m]

Logical AND accumulator with data memory

Description

Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.

Operation

ACC

¬ ACC ²AND² [m]

Affected flag(s)

PDF

AND A,x

Logical AND immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.

Operation

ACC

¬ ACC ²AND² x

Affected flag(s)

PDF

ANDM A,[m]

Logical AND data memory with the accumulator

Description

Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.

Operation

[m]

¬ ACC ²AND² [m]

Affected flag(s)

PDF

CALL addr

Subroutine call

Description

The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.

Operation

Stack

¬ PC+1

¬ addr

Affected flag(s)

PDF

CLR [m]

Clear data memory

Description

The contents of the specified data memory are cleared to 0.

Operation

[m]

¬ 00H

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

CLR [m].i

Clear bit of data memory

Description

The bit i of the specified data memory is cleared to 0.

Operation

[m].i

¬ 0

Affected flag(s)

PDF

CLR WDT

Clear Watchdog Timer

Description

The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.

Operation

WDT

¬ 00H

PDF and TO

¬ 0

Affected flag(s)

PDF

CLR WDT1

Preclear Watchdog Timer

Description

Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT

¬ 00H*

PDF and TO

¬ 0*

Affected flag(s)

PDF

CLR WDT2

Preclear Watchdog Timer

Description

Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT

¬ 00H*

PDF and TO

¬ 0*

Affected flag(s)

PDF

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1

¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

Operation

[m]

¬ [m]

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

CPLA [m]

Complement data memory and place result in the accumulator

Description

Each bit of the specified data memory is logically complemented (1

¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.

Operation

ACC

¬ [m]

Affected flag(s)

PDF

DAA [m]

Decimal-Adjust accumulator for addition

Description

The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.

Operation

If ACC.3~ACC.0 >9 or AC=1

then [m].3~[m].0

¬ (ACC.3~ACC.0)+6, AC1=AC

else [m].3~[m].0

¬ (ACC.3~ACC.0), AC1=0

and
If ACC.7~ACC.4+AC1 >9 or C=1

then [m].7~[m].4

¬ ACC.7~ACC.4+6+AC1,C=1

else [m].7~[m].4

¬ ACC.7~ACC.4+AC1,C=C

Affected flag(s)

PDF

DEC [m]

Decrement data memory

Description

Data in the specified data memory is decremented by 1.

Operation

[m]

¬ [m]-1

Affected flag(s)

PDF

DECA [m]

Decrement data memory and place result in the accumulator

Description

Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.

Operation

ACC

¬ [m]-1

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

HALT

Enter power down mode

Description

This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.

Operation

¬ PC+1

PDF

¬ 1

¬ 0

Affected flag(s)

PDF

INC [m]

Increment data memory

Description

Data in the specified data memory is incremented by 1

Operation

[m]

¬ [m]+1

Affected flag(s)

PDF

INCA [m]

Increment data memory and place result in the accumulator

Description

Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.

Operation

ACC

¬ [m]+1

Affected flag(s)

PDF

JMP addr

Directly jump

Description

The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.

Operation

¬addr

Affected flag(s)

PDF

MOV A,[m]

Move data memory to the accumulator

Description

The contents of the specified data memory are copied to the accumulator.

Operation

ACC

¬ [m]

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

MOV A,x

Move immediate data to the accumulator

Description

The 8-bit data specified by the code is loaded into the accumulator.

Operation

ACC

¬ x

Affected flag(s)

PDF

MOV [m],A

Move the accumulator to data memory

Description

The contents of the accumulator are copied to the specified data memory (one of the data
memories).

Operation

[m]

¬ACC

Affected flag(s)

PDF

NOP

No operation

Description

No operation is performed. Execution continues with the next instruction.

Operation

¬ PC+1

Affected flag(s)

PDF

OR A,[m]

Logical OR accumulator with data memory

Description

Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

ACC

¬ ACC ²OR² [m]

Affected flag(s)

PDF

OR A,x

Logical OR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.

Operation

ACC

¬ ACC ²OR² x

Affected flag(s)

PDF

ORM A,[m]

Logical OR data memory with the accumulator

Description

Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.

Operation

[m]

¬ACC ²OR² [m]

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

RET

Return from subroutine

Description

The program counter is restored from the stack. This is a 2-cycle instruction.

Operation

¬ Stack

Affected flag(s)

PDF

RET A,x

Return and place immediate data in the accumulator

Description

The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.

Operation

¬ Stack

ACC

¬ x

Affected flag(s)

PDF

RETI

Return from interrupt

Description

The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.

Operation

¬ Stack

EMI

¬ 1

Affected flag(s)

PDF

RL [m]

Rotate data memory left

Description

The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.

Operation

[m].(i+1)

¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0

¬ [m].7

Affected flag(s)

PDF

RLA [m]

Rotate data memory left and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i+1)

¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0

¬ [m].7

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

RLC [m]

Rotate data memory left through carry

Description

The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

[m].(i+1)

¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0

¬ C

¬ [m].7

Affected flag(s)

PDF

RLCA [m]

Rotate left through carry and place result in the accumulator

Description

Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.

Operation

ACC.(i+1)

¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0

¬ C

¬ [m].7

Affected flag(s)

PDF

RR [m]

Rotate data memory right

Description

The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.

Operation

[m].i

¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7

¬ [m].0

Affected flag(s)

PDF

RRA [m]

Rotate right and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i)

¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7

¬ [m].0

Affected flag(s)

PDF

RRC [m]

Rotate data memory right through carry

Description

The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

Operation

[m].i

¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7

¬ C

¬ [m].0

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

RRCA [m]

Rotate right through carry and place result in the accumulator

Description

Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.i

¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7

¬ C

¬ [m].0

Affected flag(s)

PDF

SBC A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.

Operation

ACC

¬ ACC+[m]+C

Affected flag(s)

PDF

SBCM A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.

Operation

[m]

¬ ACC+[m]+C

Affected flag(s)

PDF

SDZ [m]

Skip if decrement data memory is 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]

-1)=0, [m] ¬ ([m]-1)

Affected flag(s)

PDF

SDZA [m]

Decrement data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]

-1)=0, ACC ¬ ([m]-1)

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

SET [m]

Set data memory

Description

Each bit of the specified data memory is set to 1.

Operation

[m]

¬ FFH

Affected flag(s)

PDF

SET [m]. i

Set bit of data memory

Description

Bit i of the specified data memory is set to 1.

Operation

[m].i

¬ 1

Affected flag(s)

PDF

SIZ [m]

Skip if increment data memory is 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, [m]

¬ ([m]+1)

Affected flag(s)

PDF

SIZA [m]

Increment data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, ACC

¬ ([m]+1)

Affected flag(s)

PDF

SNZ [m].i

Skip if bit i of the data memory is not 0

Description

If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i

¹0

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

SUB A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.

Operation

ACC

¬ ACC+[m]+1

Affected flag(s)

PDF

SUBM A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.

Operation

[m]

¬ ACC+[m]+1

Affected flag(s)

PDF

SUB A,x

Subtract immediate data from the accumulator

Description

The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.

Operation

ACC

¬ ACC+x+1

Affected flag(s)

PDF

SWAP [m]

Swap nibbles within the data memory

Description

The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.

Operation

[m].3~[m].0

« [m].7~[m].4

Affected flag(s)

PDF

SWAPA [m]

Swap data memory and place result in the accumulator

Description

The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.3~ACC.0

¬ [m].7~[m].4

ACC.7~ACC.4

¬ [m].3~[m].0

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

SZ [m]

Skip if data memory is 0

Description

If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

PDF

SZA [m]

Move data memory to ACC, skip if 0

Description

The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

PDF

SZ [m].i

Skip if bit i of the data memory is 0

Description

If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i=0

Affected flag(s)

PDF

TABRDC [m]

Move the ROM code (current page) to TBLH and data memory

Description

The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.

Operation

[m]

¬ ROM code (low byte)

TBLH

¬ ROM code (high byte)

Affected flag(s)

PDF

TABRDL [m]

Move the ROM code (last page) to TBLH and data memory

Description

The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.

Operation

[m]

¬ ROM code (low byte)

TBLH

¬ ROM code (high byte)

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

XOR A,[m]

Logical XOR accumulator with data memory

Description

Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.

Operation

ACC

¬ ACC ²XOR² [m]

Affected flag(s)

PDF

XORM A,[m]

Logical XOR data memory with the accumulator

Description

Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.

Operation

[m]

¬ ACC ²XOR² [m]

Affected flag(s)

PDF

XOR A,x

Logical XOR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.

Operation

ACC

¬ ACC ²XOR² x

Affected flag(s)

PDF

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Carrier Tape Dimensions

SOP 24W

Symbol

Description

Dimensions in mm

Carrier Tape Width

24.0

±0.3

Cavity Pitch

12.0

±0.1

Perforation Position

1.75

±0.1

Cavity to Perforation (Width Direction)

11.5

±0.1

Perforation Diameter

1.55+0.1

Cavity Hole Diameter

1.5+0.25

Perforation Pitch

4.0

±0.1

Cavity to Perforation (Length Direction)

2.0

±0.1

Cavity Length

10.9

±0.1

Cavity Width

15.9

±0.1

Cavity Depth

3.1

±0.1

Carrier Tape Thickness

0.35

±0.05

Cover Tape Width

21.3

SOP 28W (300mil)

Symbol

Description

Dimensions in mm

Carrier Tape Width

24.0

±0.3

Cavity Pitch

12.0

±0.1

Perforation Position

1.75

±0.1

Cavity to Perforation (Width Direction)

11.5

±0.1

Perforation Diameter

1.5+0.1

Cavity Hole Diameter

1.5+0.25

Perforation Pitch

4.0

±0.1

Cavity to Perforation (Length Direction)

2.0

±0.1

Cavity Length

10.85

±0.1

Cavity Width

18.34

±0.1

Cavity Depth

2.97

±0.1

Carrier Tape Thickness

0.35

±0.01

Cover Tape Width

21.3

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

D 1

P 1

P 0

K 0

B 0

A 0

HT48E30

Rev. 0.00

January 12, 2004

Preliminary

Ó 2004 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek

¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.

Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw

Holtek Semiconductor Inc. (Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn

Holtek Semiconductor (Hong Kong) Ltd.
Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657

Holmate Semiconductor, Inc.
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com

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