HT0610
33120 LCD Driver
Rev. 1.00
1
February 24, 2004
Features
Operating voltage: 2.4V~3.5V
33 common/120 segment LCD driver output
33
120=3960 bits capacity of built-in graphic display
data RAM (BGDRAM)
Master and slave mode available for multi-chip
operation
8-bit Parallel interface with general MCU
On-chip oscillator circuit for display clock, external
clock can also be used
Selectable multiplex ratio: 1/16, 1/32, 1/33
Selectable bias ratio: 1/5 or 1/7
External driving circuit for external bias supply
On-chip selectable voltage doublers and tripler
Wide range of operating temperature:
-30C to 85C
S/W controlled electronic contrast control function
(16 levels)
External contrast control
Low power icon mode driven by com32
Four static icon driver circuit
High accuracy voltage regulator with temperature co-
efficient (0.00%,
-0.18%, -0.22%, -0.35%)
Low power consumption
-
Read/write mode 170
mA (Typical)
-
Display mode 160
mA (Typical)
-
Standby mode 15
mA (Typical; Display off; internal
oscillator enable)
-
Standby mode < 1
mA (Typical; Display off; external
oscillator enable)
CMOS process
TCP available
General Description
The HT0610 is a driver and controller LSI for graphic
dot-matrix liquid crystal display systems. It has 33 com-
mon and 120 segment driver circuits. This chip is con-
nected directly to an MCU, accepts 8-bit parallel display
data and stores an on-chip graphic display data RAM
(BGDRAM) of 33
120 bits. It provides a high-flexible
display section due to the one-to-one correspondence
between BGDRAM bits and LCD panel pixels. It per-
forms BGDRAM read/write operation with no externally
operating clock to minimize power consumption. In ad-
dition, because it contains power supply circuits neces-
sary to drive an LCD, it is possible to make a display
system with minimal components.
Block Diagram
Operation of LCD Driver
Description of block diagram module
Block
Description
Command Decoder and
Command Interface
This module determines whether the input data is interpreted as data or command.
Data is directed to this module based upon the input of the DCOM pin. If DCOM High,
then data is written to BGDRAM ( Built-in Graphic Display data RAM) . DCOM pin Low
indicates that the input at D0~D7 is interpreted as a Command.
CE is the master chip selection signal . A High input enable the input lines ready to sam-
ple signals.
RES pin of same function as Power On Reset (POR). Once RES received the reset sig-
nal, all internal circuitry will back to its initial status. Refer to Command Description
section for more information.
Parallel Interface
The parallel interface consists of 8 bi-directional data lines (D0~D7),RW, and CS. The
RW input High indicates a read operation from the BGDRAM . RW input Low indicates a
write to BGDRAM or Internal Command Registers depending on the status of DCOM
pin input.
The CS input serves as data latch signal (clock).
Built-in Graphic Display
data RAM (BGDRAM)
The BGDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The
size of the BGDRAM is determined by number of row times the number of column
(120
33 =3960 bits). Figure as follow is a description of the BGDRAM address map. For
mechanical flexibility, re-mapping on both Segment and Common outputs are provided
Display Timing Generator
This module is an on chip low power RC oscillator circuitry. The oscillator frequency can
be selected in the range of 15kHz to 50kHz by external resistor. One can enable the cir-
cuitry by software command. For external clock provided, feed the clock to OSC2 and
leave OSC1 open.
HT0610
Rev. 1.00
2
February 24, 2004
S t a t i c I c o n
C o n t r o l C i r c u i t
H i g h V o l t a g e C e l l L e v e l S h i f t e r
L e v e l
S e l e c t o r
1 5 5 B i t s L a t c h
( 3 3 B i t s & 1 2 0 B i t s )
T i m i n g G e n e r a t o r
f o r D i s p l a y
L C D D r i v i n g
V o l t a g e G e n e r a t o r
D o u b l e r & T r i p l e r
V o l t a g e R e g u l a t o r ,
V o l t a g e D i v i d e r ,
C o n t r a s t C o n t r o l ,
T e m p e r a t u r e
C o m p e n s a t i o n
C i r c u i t
B G D R A M
1 2 0 3 3 B i t s
C o m m a n d D e c o d e r C i r c u i t
C o m m a n d I n t e r f a c e
P a r a l l e l I n t e r f a c e
C S ( C L K ) D C O M
R E S C E
R W
D 0 ~ D 7
V D D
V S S
I B P
I C O N 0 ~ I C O N 3
S E G 0 ~ S E G 1 1 9
C O M 0 ~ C O M 3 2
V L L 2
V L L 6
V C C A 1
V R
V F
C 2 P
C 2 N
C 1 P
C 1 N
D U M 2
D U M 1
C +
C -
V D D A
O S C 1
O S C 2
Block
Description
Static Icon Control Circuit
This module generates the LCD waveform of the 4 annunciators and IBP signal. The
four independent static icons are enabled by software command. Icon signals are also
controlled by oscillator circuit, too.
LCD Driving Voltage
Generator
This module generates the LCD voltage needed for display output. It takes a single sup-
ply input and generates necessary bias voltages. It consists of:
Voltage doubler and voltage tripler
To generate the VCCA1 voltage. Either doubler or tripler can be enabled.
Voltage regulator
Feedback gain control for initial LCD voltage. It can also be used with external contrast
control.
Voltage divider
Divide the LCD display voltage (VLL2~VLL6) from the regulator output. This is low
power consumption circuit, which can save the most display current compare with tra-
ditional resistor ladder method.
Bias Ratio Selection circuitry
Software control of 1/5 and 1/7 bias ratios to match the characteristic of LCD panel.
Self adjust temperature compensation circuitry
Provide 4 different compensation grade selections to satisfy the various liquid crystal
temperature grades. The grading can be selected by software control.
Contrast Control Block
Software control of 16 voltage levels of LCD voltage.
External Contrast Control
By adjusting the gain control resistors connected externally, the contrast can be var-
ied.
All blocks can be individually turned off if external voltage generator is employed.
120 Bit Latch/33 Bit Latch
153 bit long registers, which carry the display signal information. First 33 bits are Com-
mon driving signals and other 120 bits are Segment driving signals. Data will be input to
the HV-buffer Cell for bumping up to the required level.
Level Selector
Level selector is a control of the display synchronization. Display voltage can be sepa-
rated into two sets and used with different cycles. Synchronization is important since it
selects the required LCD voltage level to the HV Buffer Cell for output signal voltage
pump.
HV Buffer Cell
(Level Shifter)
HV Buffer Cell works as a level shifter that translates the low voltage output signal to the
required driving voltage. The output is shifted out with an internal FRM clock, which co-
mes from the Display Timing Generator. The voltage levels are given by the level selec-
tor which is synchronized with the internal M signal.
HT0610
Rev. 1.00
3
February 24, 2004
Pin Assignment
HT0610
Rev. 1.00
4
February 24, 2004
D U M M Y
V S S
O S C 1
V S S
V R
V F
V C C A 1
C -
C +
D U M 2
O S C 2
D U M 1
V L L 6
V L L 5
V L L 4
V L L 3
V L L 2
C 2 N
C 2 P
C 1 N
C 1 P
V D D A
V S S
C E
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
V S S
C S ( C L K )
R W
D C O M
V S S
R E S
V D D
D U M M Y
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
1 9 7
1 9 6
1 9 5
1 9 4
1 9 3
1 9 2
1 8 4
1 8 3
1 8 2
1 8 1
1 8 0
1 7 9
1 7 8
1 7 7
1 7 6
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
C O M 3 2
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
C O M 1 2
C O M 1 3
C O M 1 4
C O M 1 5
S E G 0
S E G 1
S E G 2
S E G 3
S E G 4
S E G 1 1 7
S E G 1 1 8
S E G 1 1 9
C O M 3 2
C O M 3 1
C O M 3 0
C O M 2 9
C O M 2 8
C O M 1 9
C O M 1 8
C O M 1 7
C O M 1 6
I C O N 0
I C O N 1
I C O N 2
I C O N 3
I B P
D U M M Y
D U M M Y
Pin Description
Pin Name
I/O
Description
VDD
I
VDD is the positive supply to the digital control circuit and other circuitry in LCD bias voltage
generator (Must have same voltage level with VDDA)
RES
I
Active low reset pin; reset all internal status of circuit (Same as power on reset)
VSS
I
VSS is ground
DCOM
I
If pull this pin
High then D0~D7 bi-direction bus is used for data transferring; If DCOM pin is
Low then D0~D7 bi-direction bus is used for command transferring.
RW
I
If pull this pin high: Indicate we want to read the display data RAM or the internal state. If we
force this to Low: Indicate we want to write data to display data RAM or write some internal
state to registers.
CS
I
This pin is normal low clock input. Data on D0~D7 bi-direction data bus are latched at the fall-
ing edge of CS
D0~D7
B
Those bi-direction pins are used for DATA or command transferring.
CE
I
High input to this pin to enable the control pins on the driver.
OSC1
I
Oscillator input pin.
For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In
this mode, an external resistor of certain value is placed between the OSC1 and OSC2 pins.
For external oscillator mode, OSC1 pin should be left open
OSC2
O
Oscillator output pin
For internal oscillator mode, this is an output for the internal low power RC oscillator circuit.
External Oscillator input
For external oscillator mode, OSC2 will be an input pin for external clock and no external resis-
tor is needed.
C1P, C1N
If internal DC/DC converter is enabled, a capacitor is required to connect these two pins.
C2P, C2N
If internal tripler is enabled, a capacitor is required to connect these two pins. Otherwise, leave
these pin open.
VLL2~VLL6
O
Group of voltage level pins for driving the LCD panel. They can either be connected to external
driving circuit for external bias supply or connected internally to built-in divider circuit. For in-
ternal voltage divider enable, a 0.1
mF capacitor to VSS is required on each pin.
DUM1, DUM2
O
If internal voltage divider is enable with 1/7 bias selected, a capacitor to VSS is required on
each pin. Otherwise, pull these two pin to VSS
C+, C-
If internal divider circuit is enable, a capacitor is required to connect between these two pin
VCCA1
O
If internal DC/DC Converter is enabled, a 0.1
mF capacitor from this pin to VSS is required. It
can also be an external bias input pin if internal DC/DC converter is not used
VF, VR
This is a feedback path for the gain control (external contrast control) of VLL1 to VLL6. For ad-
justing the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a
gain control resistor placed between VF and VSS, a 10uF capacitor placed between VR and
VSS.
COM0~COM32
O
These pins provide the row driving signal to LCD panel
VDDA
I
VDDA is the positive supply to the noise sensitive circuitry and must have same voltage level
with VDD
ICON1~ICON4
O
There are four independent annunciator driving outputs
IBP
O
This pin combines with ICON1~ICON4 pins to form annunciator driving part.
SEG0~SEG119
O
These 120 pins provide LCD column driving signal to LCD panel.
HT0610
Rev. 1.00
5
February 24, 2004
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