HT1620
RAM Mapping 324 LCD Controller for I/O mC
Selection Table
HT162X
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4
4
8
8
8
8
16
16
16
SEG
32
32
32
32
48
64
48
64
64
Built-in Osc.
Crystal Osc.
1
July 26, 1999
Features
Logic operating voltage: 2.4V~3.3V
LCD voltage: 3.6V~4.9V
Low operating current <3mA at 3V
External 32.768kHz crystal oscillator
Selection of 1/2 or 1/3 bias, and selection of
1/2 or 1/3 or 1/4 duty LCD applications
Internal time base frequency sources
Two selectable buzzer frequencies
(2kHz/4kHz)
Built-in capacitor type bias charge pump
Time base or WDT overflow output
8 kinds of time base/WDT clock source
324 LCD driver
Built-in 324-bit display RAM
3-wire serial interface
Internal LCD driving frequency source
Software configuration feature
R/W address auto increment
Data mode and command mode
instructions
Three data accessing modes
General Description
The HT1620 is a 128 pattern (324), memory
mapping, and multi-function LCD driver. The
S/W configuration feature of the HT1620
makes it suitable for multiple LCD applica-
tions including LCD modules and display sub-
systems. Only three or four lines are required
for the interface between the host controller
and the HT1620. The HT1620 consumes low
operating current owing to adopting capacitor
type bias charge pump. The HT162X series
have many kinds of products that match vari-
ous applications.
Block Diagram
Notes: CS: Chip selection
BZ, BZ: Tone outputs
WR, RD, DATA: Serial interface
COM0~COM3, SEG0~SEG31: LCD outputs
IRQ: Time base or WDT overflow output
VO15N: Half voltage circuit output pin
VEE: Double voltage circuit output pin
CC1/CC2: External capacitor pin, for double voltage and half voltage circuit use
HT1620
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July 26, 1999
W a t c h d o g T i m e r
&
T i m e B a s e G e n e r a t o r
D i s p l a y R A M
L C D D r i v e r /
B i a s C i r c u i t
C o n t r o l
a n d
T i m i n g
C i r c u i t
D A T A
W R
O S C O
O S C I
C S
R D
C O M 0
C O M 3
S E G 0
S E G 3 1
T o n e F r e q u e n c y
G e n e r a t o r
B Z
B Z
I R Q
V S S
V D D
C C 2
C C 1
V O 1 5 N
V E E
Pin Assignment
HT1620
3
July 26, 1999
IR
Q
BZ
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
5 2
5 3
5 4
5 5
2 3
2 0 2 1 2 2
2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4 1
5 1
3 7
3 8
3 9
4 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
5 0
3 3
3 4
3 5
3 6
SE
G
1
1
NC
SE
G
9
SE
G
1
0
SE
G
1
2
SE
G
1
3
SE
G
1
4
SE
G
1
5
SE
G
1
6
SE
G
1
7
SE
G
1
8
SE
G
1
9
NC
N C
S E G 2 7
N C
N C
N C
N C
N C
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 0
N C
S E G 2 2
S E G 2 1
BZ
NC
CC1
VD
D
OSC
I
OSC
O
VS
S
DA
T
A
WR RD CS
N C
S E G 1
N C
C C 2
V O 1 5 N
V E E
C O M 0
C O M 1
C O M 2
C O M 3
S E G 0
S E G 2
S E G 3
S E G 4
S E G 5
S E G 8
N C
S E G 6
S E G 7
1
1 1
2
3
4
5
6
7
8
9
1 0
1 2
1 3
1 4
1 5
1 8
1 9
1 6
1 7
H T 1 6 2 0
6 4 Q F P
Pad Assignment
Chip size: 142 141 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
HT1620
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July 26, 1999
IR
Q
BZ
1
2 7
2
2 8
3
2 9
4
3 0
5
3 1
6
3 2
7
3 3
8
3 4
9
3 5
1 0
3 6
1 1
3 7
1 2
3 8
1 3
3 9
1 4
4 0
1 5
4 1
1 6
4 2
1 7
4 3
1 8
4 4
1 9
4 5
2 0
4 6
2 1
4 7
2 2
4 8
2 3
4 9
2 4
5 0
2 5
5 1
2 6
( 0 , 0 )
C C 2
V O 1 5 N
V E E
C O M 0
C O M 1
C O M 2
C O M 3
S E G 0
S E G 1
S E G 2
S E G 3
S E G 4
S E G 5
SE
G
6
SE
G
7
SE
G
8
SE
G
9
SE
G
1
0
SE
G
1
1
SE
G
1
2
SE
G
1
3
SE
G
1
4
SE
G
1
5
SE
G
1
6
SE
G
1
7
SE
G
1
8
SE
G
1
9
S E G 3 1
S E G 3 0
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 2 0
S E G 2 1
S E G 2 2
CC1
BZ
VD
D
OSC
I
OSC
O
VS
S
DA
T
A
WR
RD
CS
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
1
-61.58
63.62
27
25.29
-64.26
2
-61.83
50.83
28
66.98
-62.65
3
-61.83
43.73
29
66.98
-56.01
4
-61.83
37.10
30
66.98
-49.38
5
-61.83
30.47
31
66.98
-42.76
6
-61.83
23.84
32
66.98
-36.13
7
-61.83
17.21
33
66.98
-29.50
8
-61.83
10.58
34
66.98
-22.86
9
-61.83
3.95
35
66.98
-16.24
10
-61.83
-2.68
36
66.98
-9.60
11
-61.83
-9.31
37
66.98
-2.97
12
-61.83
-15.94
38
66.98
3.65
13
-61.83
-22.57
39
66.98
10.28
14
-60.90
-64.26
40
65.71
64.39
15
-54.27
-64.26
41
59.08
64.39
16
-47.64
-64.26
42
52.45
64.39
17
-41.01
-64.26
43
40.59
64.39
18
-34.38
-64.26
44
29.75
64.39
19
-27.75
-64.26
45
22.95
64.39
20
-21.12
-64.26
46
16.32
64.39
21
-14.49
-64.26
47
9.56
64.39
22
-7.86
-64.26
48
-2.21
64.30
23
-1.23
-64.26
49
-21.80
64.39
24
5.40
-64.26
50
-39.52
64.39
25
12.03
-64.26
51
-49.60
63.62
26
18.66
-64.26
HT1620
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July 26, 1999
Pad Description
Pad No.
Pad Name
I/O
Description
2
VO15N
O
Half voltage circuit output pin
3
VEE
Double voltage circuit output pin
4~7
COM0~COM3
O
LCD common outputs
8~39
SEG0~SEG31
O
LCD segment outputs
40
CS
I
Chip selection input with pull-high resistor
When the CS is logic high, the data and command, read from or
written to the HT1620 are disabled. The serial interface circuit is
also reset. But if the CS is at logic low level and is input to the CS
pad, the data and command transmission between the host con-
troller and the HT1620 are all enabled.
41
RD
I
READ clock input with pull-high resistor
Data in the RAM of the HT1620 are clocked out on the falling
edge of the RD signal. The clocked out data will appear on the
DATA line. The host controller can use the next raising edge to
latch the clocked out data.
42
WR
I
WRITE clock input with pull-high resistor
Data on the DATA line are latched into the HT1620 on the rising
edge of the WR signal.
43
DATA
I/O Serial data input/output with pull-high resistor
44
VSS
Negative power supply, Ground
45
OSCO
O
The OSCI and OSCO pads are connected to a 32.768kHz crystal
in order to generate a system clock.
46
OSCI
I
47
VDD
Positive power supply
48
IRQ
O
Time base or WDT overflow flag, NMOS open drain output
49, 50
BZ, BZ
O
2kHz or 4kHz tone frequency output pair (tri-state output buffer)
51, 1
CC1, CC2
I
External capacitor pin, for double voltage and half voltage circuit
use
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 3.6V
Storage Temperature.................-50
o
C to 125
o
C
Input Voltage.................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...............-25
o
C to 75
o
C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-
mum Ratings may cause substantial damage to the device. Functional operation of this de-
vice at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
HT1620
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July 26, 1999
D.C. Characteristics
Ta=25C
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
V
DD
Operating Voltage
2.4
3.3
V
I
DD
Operating Current
3V
No load*
2
3
mA
I
STB
Standby Current
3V
No load*
1
mA
V
IL
Input Low Voltage
3V
DATA, WR, CS, RD
0.6
V
V
IH
Input High Voltage
3V
DATA, WR, CS, RD
2.4
3.0
V
I
OL1
DATA, BZ, BZ, IRQ
3V
V
OL
=0.3V
0.8
1.6
mA
I
OH1
DATA, BZ, BZ
3V
V
OH
=2.7V
-0.6
-1.2
mA
I
OL2
LCD Common Sink
Current
3V
V
OL
=0.3V
80
150
mA
I
OH2
LCD Common Source
Current
3V
V
OH
=2.7V
-70
-120
mA
I
OL3
LCD Segment Sink
Current
3V
V
OL
=0.3V
70
140
mA
I
OH3
LCD Segment Source
Current
3V
V
OH
=2.7V
-30
-60
mA
R
PH
Pull-high Resister
3V
DATA, WR, CS, RD
40
80
150
kW
* No load: LCD OFF, Buzzer OFF, CS=WR=RD=High
A.C. Characteristics
Ta=25C
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
f
SYS
System Clock
3V Crystal 32kHz
32
kHz
f
LCD
LCD Frame Frequency
Crystal 32kHz
64
Hz
LCD Frame Frequency 1/2 Duty
64
Hz
LCD Frame Frequency 1/3 Duty
56
Hz
LCD Frame Frequency 1/4 Duty
64
Hz
t
COM
LCD Common Period
n: Number of COM
n/f
LCD
s
f
CLK
Serial Data Clock
3V
Write mode
150 kHz
Read mode
75
kHz
f
TONE
Tone Frequency
2 or 4
kHz
HT1620
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July 26, 1999
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
t
CS
Serial Interface Reset Pulse
Width
(Figure 3) CS
250
ns
t
CLK
WR, RD Input Pulse Width
(Figure 1) 3V
Write mode
3.34
ms
Read mode
6.67
t
r
, t
f
Rise/Fall Time Serial Data Clock
Width
(Figure 1) 3V
120
ns
t
su
Setup Time for DATA to WR, RD
Clock Width
(Figure 2) 3V
120
ns
t
h
Hold Time for DATA to WR, RD
Clock Width
(Figure 2) 3V
120
ns
t
su1
Setup Time for CS to WR,RD
Clock Width
(Figure 3) 3V
100
ns
t
h1
Hold Time for CS to WR, RD Clock
Width
(Figure 3) 3V
100
ns
HT1620
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July 26, 1999
9 0 %
5 0 %
1 0 %
G N D
W R , R D
C l o c k
t
f
t
r
t
C L K
t
C L K
V
D D
Figure 1
5 0 %
V A L I D D A T A
5 0 %
D B
W R , R D
C l o c k
G N D
t
s u
t
h
V
D D
V
D D
G N D
Figure 2
C S
G N D
5 0 %
5 0 %
F I R S T
C l o c k
L A S T
C l o c k
G N D
W R , R D
C l o c k
t
s u 1
t
h 1
t
C S
V
D D
V
D D
Figure 3
HT1620
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July 26, 1999
Functional Description
Display memory - RAM structure
The static display RAM is organized into 324
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be ac-
cessed by the READ, WRITE and READ-MOD
IFY-WRITE commands. The following is a map-
ping from the RAM to the LCD patterns.
Time base and watchdog timer - WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will stay at a logic
low level until the CLR WDT or the IRQ DIS
command is issued.
Buzzer tone output
A simple tone generator is implemented in the
HT1620. The tone generator can output a pair
of differential driving signals on the BZ and BZ
which are used to generate a single tone.
LCD driver
The HT1620 is a 128 (324) pattern LCD driver.
It can be configured as 1/2 or 1/3 bias and 2 or 3
or 4 commons of LCD driver by the S/W configu-
ration. This feature makes the HT1620 suitable
for multiple LCD applications. The LCD driving
clock is derived from the system clock. The value
of the driving clock is always 256Hz even when it
is at a 32.768kHz crystal oscillator frequency. The
LCD corresponding commands are summarized
in the table.
The bold form of 1 0 0, namely 1 0 0, indicates
the command mode ID. If successive commands
have been issued, the command mode ID will be
omitted, except for the first command. The LCD
OFF command turns the LCD display off by dis-
abling the LCD bias generator. The LCD ON
command, on the other hand, turns the LCD
display on by enabling the LCD bias generator.
The BIAS and COM are the LCD panel related
commands. With the use of the LCD related
commands, the HT1620 can be compatible with
most types of LCD panels.
W D T E N / D I S
I R Q E N / D I S
D
C K
Q
R
C L R W D T
C l o c k S o u r c e
/ 4
/ 2 5 6
T i m e B a s e
C L R T i m e r
I R Q
W D T
V D D
T I M E R E N / D I S
Timer and WDT configurations
S E G 0
S E G 1
S E G 2
S E G 3
S E G 3 1
C O M 0
C O M 1
C O M 2
C O M 3
D 3
D 2
D 1
D 0
D a t a
A d d r
3 1
0
1
2
3
A d d r e s s 6 b i t s
( A 5 , A 4 , . . . , A 0 )
D a t a 4 b i t s
( D 3 , D 2 , D 1 , D 0 )
RAM mapping
HT1620
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July 26, 1999
Name
Command Code
Function
LCD OFF
1 0 0 0 0 0 0 0 0 1 0 X
Turn off LCD outputs
LCD ON
1 0 0 0 0 0 0 0 0 1 1 X
Turn on LCD outputs
BIAS and COM 1 0 0 0 0 1 0 a b X c X
c=0: 1/2 bias option
c=1: 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
Command format
The HT1620 can be configured by the S/W set-
ting. There are two mode commands to configure
the HT1620 resources and to transfer the LCD
display data. The configuration mode of the
HT1620 is called command mode, and its com-
mand mode ID is 1 0 0. The command mode con-
sists of a system configuration command, a
system frequency selection command, an LCD
configuration command, a tone frequency selec-
tion command, a timer/WDT setting command,
and an operating command. The data mode, on
the other hand, includes READ, WRITE, and
READ-MODIFY-WRITE operations. The follow-
ing are the data mode IDs and the command
mode ID:
Operation
Mode
ID
READ
Data
1 1 0
WRITE
Data
1 0 1
READ-MODIFY-WRITE
Data
1 0 1
COMMAND
Command 1 0 0
The mode command should be issued before the
data or command is transferred. If successive
commands have been issued, the command
mode ID, 1 0 0, can be omitted. While the sys-
tem is operating in the non-successive com-
mand or the non-successive address data mode,
the CS pin should be set to 1 and the previous
operation mode will be reset also. Once the CS
pin returns to 0, a new operation mode ID
should be issued first.
Interfacing
Only four lines are required to interface with
the HT1620. The CS line is used to initialize the
serial interface circuit and to terminate the com-
munication between the host controller and the
HT1620. If the CS pin is set to 1, the data and
command issued between the host controller and
the HT1620 are first disabled and then initial-
ized. Before issuing a mode command or mode
switching, a high level pulse is required to initial-
ize the serial interface of the HT1620. The DATA
line is the serial data input/output line. Data to
be read or written or commands to be written
have to be passed through the DATA line. The RD
line is the READ clock input. Data in the RAM
are clocked out on the falling edge of the RD sig-
nal, and the clocked out data will then appear on
the DATA line. It is recommended that the host
controller read in correct data during the interval
between the rising edge and the next falling edge
of the RD signal. The WR line is the WRITE clock
input. The data, address, and command on the
DATA line are all clocked into the HT1620 on the
rising edge of the WR signal. There is an optional
IRQ line to be used as an interface between the
host controller and the HT1620. The IRQ pin can
be selected as a timer output or a WDT overflow
flag output by the S/W setting. The host control-
ler can perform the time base or the WDT func-
tion by connecting with the IRQ pin of the
HT1620.
Timing Diagrams
READ mode (command code: 1 1 0)
READ mode (successive address reading)
WRITE mode (command code: 1 0 1)
HT1620
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July 26, 1999
R D
D A T A
W R
1
1
0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 1 ( M A 1 )
D a t a ( M A 2 )
1
1
0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
D a t a ( M A 1 )
M e m o r y A d d r e s s 2 ( M A 2 )
C S
R D
D A T A
C S
W R
1
1
0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s ( M A )
D a t a ( M A )
D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a t a ( M A + 1 )
D a t a ( M A + 2 )
D a t a ( M A + 3 )
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 1 ( M A 1 )
D a t a ( M A 1 )
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 2 ( M A 2 )
D a t a ( M A 2 )
WRITE mode (successive address writing)
Note: It is recommended that the host controller should read with the data from the DATA line
between the raising edge of the RD line and the falling edge of the next RD line.
READ-MODIFY-WRITE mode (command code: 1 0 1)
READ-MODIFY-WRITE mode (successive address accessing)
HT1620
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July 26, 1999
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s ( M A ) D a t a ( M A )
D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a t a ( M A + 1 )
D a t a ( M A + 2 )
D a t a ( M A + 3 )
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 1 ( M A 1 )
D a t a ( M A 1 )
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 2 ( M A 2 )
D a t a ( M A 2 )
1
0
1
R D
D 0 D 1 D 2 D 3
D a t a ( M A 1 )
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s ( M A )
D a t a ( M A )
D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a t a ( M A )
D a t a ( M A + 1 )
D a t a ( M A + 1 )
R D
D 1 D 2 D 3 D 0
D a t a ( M A + 2 )
Command mode (command code: 1 0 0)
Mode (data and command mode)
HT1620
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July 26, 1999
D A T A
C S
W R
1
0
0 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0
C o m m a n d 1
C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0
C o m m a n d i
C o m m a n d . . .
C o m m a n d
o r
D a t a M o d e
R D
D A T A
C S
W R
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
Application Circuits
* Notes: The connection of the IRQ and RD pin is selectable depending on the requirement of the mC.
V
DD
=2.4V~3.3V, V
EE
=-1/2 V
DD
, V
LCD
(LCD voltage)=V
DD
-V
EE
=3/2 V
DD
=3.6V~4.9V.
Adjust R (external pull-high resistance) to fit users time base clock.
HT1620
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July 26, 1999
0 . 1 m F
I R Q
D A T A
C S
R D
W R
m C
H T 1 6 2 0
L C D P a n e l
B Z
O S C I
O S C O
B Z
C r y s t a l
3 2 7 6 8 H z
O s c i l l a t o r
C O M 0 ~ C O M 3
S E G 0 ~ S E G 3 1
C C 1
C C 2
V E E
V O 1 5 N
V D D
V D D
*
P i e z o
1 / 2 o r 1 / 3 B i a s ; 1 / 2 , 1 / 3 o r 1 / 4 D u t y
R
*
3 M W
0 . 1 m F
0 . 1 m F
Command Summary
Name
ID
Command Code
D/C
Function
Def.
READ
1 1 0 A5A4A3A2A1A0D0D1D2D3
D
Read data from the RAM
WRITE
1 0 1 A5A4A3A2A1A0D0D1D2D3
D
Write data to the RAM
READ
MODIFY
WRITE
1 0 1 A5A4A3A2A1A0D0D D2D3
D
Read and write to the RAM
SYS DIS
1 0 0 0000-0000-X
C
Turn off both system oscillator
and LCD bias generator
Yes
SYS EN
1 0 0 0000-0001-X
C
Turn on system oscillator
LCD OFF
1 0 0 0000-0001-X
C
Turn off LCD bias generator
Yes
LCD ON
1 0 0 0000-0011-X
C
Turn on LCD bias generator
TIMER DIS 1 0 0 0000-0100-X
C
Disable time base output
Yes
WDT DIS
1 0 0 0000-0101-X
C
Disable WDT time-out flag
output
Yes
TIMER EN 1 0 0 0000-0010-X
C
Enable time base output
WDT EN
1 0 0 0000-0111-X
C
Enable WDT time-out flag
output
TONE OFF 1 0 0 0000-1000-X
C
Turn off tone outputs
Yes
CLR TIMER 1 0 0 0000-1101-X
C
Clear the contents of the time base
generator
CLR WDT
1 0 0 0000-111X-X
C
Clear the contents of the WDT
stage
BIAS 1/2
1 0 0 0010-abX0-X
C
LCD 1/2 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
BIAS 1/3
1 0 0 0010-abX1-X
C
LCD 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
TONE 4K
1 0 0 010X-XXXX-X
C
Tone frequency, 4kHz
TONE 2K
1 0 0 0110-XXXX-X
C
Tone frequency, 2kHz
IRQ DIS
1 0 0 100X-0XXX-X
C
Disable IRQ output
Yes
IRQ EN
1 0 0 100X-1XXX-X
C
Enable IRQ output
HT1620
15
July 26, 1999
Name
ID
Command Code
D/C
Function
Def.
F1
1 0 0 101X-0000-X
C
Time base clock output: 1Hz
The WDT time-out flag after: 4s
F2
1 0 0 101X-0001-X
C
Time base clock output: 2Hz
The WDT time-out flag after: 2s
F4
1 0 0 101X-0010-X
C
Time base clock output: 4Hz
The WDT time-out flag after: 1s
F8
1 0 0 101X-0011-X
C
Time base clock output: 8Hz
The WDT time-out flag after: 1/2 s
F16
1 0 0 101X-0100-X
C
Time base clock output: 16Hz
The WDT time-out flag after: 1/4 s
F32
1 0 0 101X-0101-X
C
Time base clock output: 32Hz
The WDT time-out flag after: 1/8 s
F64
1 0 0 101X-0110-X
C
Time base clock output: 64Hz
The WDT time-out flag after: 1/16 s
F128
1 0 0 101X-0111-X
C
Time base clock output: 128Hz
The WDT time-out flag after:1/32 s Yes
TEST
1 0 0 1110-0000-X
C
Test mode, user dont use.
NORMAL
1 0 0 1110-0011-X
C
Normal mode
Yes
Notes: X : Don
,
t care
A5~A0 : RAM addresses
D3~D0 : RAM data
D/C : Data/command mode
Def. : Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the
command mode ID. If successive commands have been issued, the command mode ID except for the
first command will be omitted. The source of the tone frequency and of the time base/WDT clock fre-
quency can be derived from a 32.768kHz crystal oscillator. Calculation of the frequency is based on
the system frequency sources as stated above. It is recommended that the host controller should ini-
tialize the HT1620 after power on reset, for power on reset may fail, which in turn leads to malfunc-
tioning of the HT1620.
HT1620
16
July 26, 1999
HT1620
17
July 26, 1999
Copyright 1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Microelectronics Enterprises Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
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